JPS5816277B2 - Rensoukiokusuhouchino Godousakenshiyutsuhoshiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for detecting malfunctions in an associative memory device composed of a data section and a parity section.

As is well known, an associative memory device is a TLB (
translation lookaside buffer), B
It is widely used as AA (buffer address array), ASR (associative register), etc.

FIG. 1 is a schematic diagram for explaining the operation of this type of content addressable memory device.

In the figure, SR indicates a source information register, KR indicates a sink information register, and AM(i) indicates one entry in the associative memory.

Each entry in the associative memory has a pair of source information and sink information associated with the source information, for each source field AMS(i) and sink field A M K
(i), and the source information is used to associate the sink information by searching the information pair in the associative memory.

The process of associating sink information from source information is as follows.

Source information IS set in source information register SR
R is compared with the source field AMS(i) of each entry in the associative memory by a comparison circuit C(i) provided for each entry AM(i) of the associative memory, and the comparison result is This is reflected in the output signal cGl) of each comparison circuit.

The signal CG(i) controls the input data G(i) of the sync information register KR to set the contents of the sync field AMK(i) of the matched entry, that is, the sync information, in the sync information register KR. .

By the way, if a malfunction occurs in such an associative memory device, information that should be correctly associated may not be associated,
This results in completely different information being associated, and as a result, the operation of the entire system including the associative memory device becomes completely incorrect.

Therefore, if a malfunction occurs in the associative memory device, it is necessary to know it promptly.

Conventionally, the following methods are known for detecting malfunctions in content addressable memory devices.

The first method deals with malfunctions in the source field of each entry in the content addressable memory, and as shown in Figure 2, the source field AMS (
A parity bit Ps(i) is provided in the source field AMS(i), and each time the content addressable memory device is referred, a parity check circuit PC(i) provided for each entry
By performing the parity check of i), a malfunction in the source field is detected and the malfunction occurrence information EM(i
) to report to the system the occurrence of a malfunction in the associative memory device.

In the second method, as shown in Fig. 3, the source is Field parity-check circuit PC(i
), two types of comparison circuits are provided, CiM and CiS, and both comparison circuits simultaneously compare the source information ISR and the source field AMS(i), and the output signals CG(i) and CGS of both comparison circuits are (i) Malfunctions in the comparator circuit can also be detected by checking O match/mismatch;
Malfunction occurrence information EM in source field AMS(i)
(i) and malfunction information EC(i) in the comparator circuit to report the occurrence of malfunction in the content addressable memory device to the system.

The third method is a further development of the second method to deal with the case where a malfunction occurs in the source information register.

That is, as shown in FIG. 4, in addition to providing a parity check circuit PC(i) and duplex comparison circuits CiS and CiM for each entry of the content addressable memory device, a parity bit is also provided in the source information register SR. PSR and parity
A check circuit PC8(i) is provided to detect a malfunction of the source information register by checking the performance of the source information register SR every time the associative memory is referred, and to detect malfunction occurrence information E in the source field.
The occurrence of a malfunction in the content addressable memory device is reported to the system using M(i), comparator circuit CiS, malfunction occurrence information EC(i) in SiM, and malfunction occurrence information ES(i) in the source information register SR. It is something.

However, in the conventional malfunction detection method for associative memory devices as described above, it is necessary to provide a source field parity check circuit for each entry.
Furthermore, in order to detect malfunctions in the comparator circuit, it is necessary to provide two comparator circuits for each entry.Furthermore, in order to detect malfunctions in the source information register, a parity check circuit must be installed in the source information register. , which requires a large amount of hardware.

In addition, in conventional malfunction detection methods, if a parity error occurs in an entry unrelated to the source information even though a normal associative operation was performed in the corresponding entry, an error occurs in the entire associative memory device. As,
The problem is that the occurrence of a malfunction is reported as a machine check, and the processing device performs the machine check process, which requires extra overhead such as initializing the content of the content addressable memory device.

An object of the present invention is to provide an economical malfunction detection method with a high detection rate in an associative memory device, thereby increasing the availability of the associative memory device.

Simply put, the feature of the present invention is that the associative memory device has two
When associating sink information from source information, only entries for which the source information matches the information stored in the associative memory, the information stored in the associative memory, the comparison circuit, and the malfunction of the source information are detected. Unlike the conventional method, there is no need to provide a parity check circuit for the information stored in the associative memory and a duplicate comparison circuit for each entry.
Comparison with the source information Only entries with a match are checked for a match between the parity bit of the source information and the parity bit of the information stored in the associative memory, thereby detecting malfunctions of the associative memory device and source information register. There is a particular thing.

That is, in general, most malfunctions are 1-bit errors, and errors of 2 or more bits are rare (the parity check is based on this idea).

In this case, for example, if there is a 1-bit error in the data bit, it may not match the information in the associative memory, or it may match with other information due to a 1-bit error, but the former is originally Since they do not match, there is no problem; in the latter case, a match has been achieved by mistake; however, in this case, the parity bits will always be mismatched, so a malfunction will be detected.

Furthermore, if there is an error in the parity bits, it is detected as a mismatch in the parity bits when the data match.

Hereinafter, the content of the present invention will be explained in detail with reference to Examples.

FIG. 5 shows one embodiment of the present invention, in particular only one end ')-AM(i) of the content addressable memory device is shown.

In FIG. 5, A(i) represents the parity bit Ps□ of the source information ISR set in the source information register SR and the parity bit Ps□ of the information AMS(i) stored in the source field of each entry of the associative memory. This is an exclusive OR gate that checks for coincidence with bit Psi, and when both signals PSR and Psi do not match, the output signal D(i) of the gate A(i) becomes "1".

B(i) is the output amount D(i) of the gate A(i)
, source information ISR and source field AMS(i)
The output signal CG(i
), a match is taken between the comparator circuit C(i) source information ISR and the source field AMS(i), and the parity bit P of the source information ISR is
When a mismatch occurs between sB and the parity bit Psi of source-filled AMS(i), the signal E(i) indicating that a malfunction has occurred in the associative memory device is set to "1" to indicate that a malfunction has occurred in the system. This is to be reported.

Parity bit Psi is added when registering information AMS(i). For example, if odd parity is assumed, and the number of "1"s in AMS(i) is even, Psi
= 1, if the number of “1” in AMS(i) is odd, Psi
=O.

Furthermore, the parity bit PS□ is added when the source information ISR for referencing the content addressable memory device is issued. For example, if odd parity is assumed, the number of "1"s in the ISR is If the number is even, P8R=1, IS
If the number of 1''s in R is an odd number, p3R=o.

Detection of malfunction in the associative memory device in the case shown in FIG. 5 is as follows.

When a parity error (generally an odd bit error, here we focus on a 1-bit error) occurs in the source information register SR, a match is mistakenly made with an unrelated entry in the associative memory. There is.

For example, if a 1-bit error occurs in the source information ISR, the AMS(i) of the entry AM(i) in the associative memory
Suppose that it matches.

In this case, a mismatch occurs between the parity -P8R of the source information ISR and the parity Psi of the source field AMs(i) of the matched entry AM(i).

Therefore, the output signal D(i) of exclusive OR gate A(i)
) is “1”, and the output signal CG(i) of the comparator circuit C(i) is “1”, so the AND gate B(
The output signal E(i) of i) becomes "1", and the occurrence of the malfunction is reported to the system.

Next, if a 1-bit error occurs in the source field AMS(i) in the associative memory, a match with the source information ISR may be taken by mistake.

In this case, as before, the parity of the source information ISR is
Since a mismatch occurs between the bit PSR and the parity bit Psi of the source field AMS(i), the gate
A(i) and B(i) operate, and the occurrence of a malfunction is reported to the system by signal E(i).

In addition, a comparison circuit C(i
)≠, if an erroneous operation occurs, it is conceivable that a match may be mistakenly taken between completely unrelated source information and a source field.

In this case as well, since most of the errors are 1-bit errors, the parity bit P8R of the source information ISR,
Parity bit P of source source AMS(i)
Since there is a mismatch between si, gates A(i) and B(
i) is activated, and the occurrence of a malfunction is reported to the system by signal E(i).

As described above, according to the malfunction detection method of the present invention, two gate circuits provided for each entry are used to detect parity errors in the source information register, parity errors in the source field in the associative memory, and compare It is possible to detect malfunctions in circuits.

Furthermore, in the method of the present invention, malfunction detection of stored information and comparison circuits is only performed in entries that match source information, and malfunctions of stored information and comparison circuits of entries unrelated to source information are detected. Normal operation is guaranteed without causing the system to stop unnecessarily.

Furthermore, in an associative memory device, if all entries are not matched with the source information, a re-registration operation is performed since the corresponding information pair is not registered in the associative memory.

Therefore, according to the present invention, even if all entries and source information are not matched due to a malfunction, recovery from the malfunction can be expected through the re-registration operation.

Note that although the present invention is powerless against errors in even-numbered bits, such errors are rare, and in actual operation,
Rather than causing a serious problem, it is more problematic to prepare a large amount of hardware for a rare error and have to detect unnecessary malfunctions, and it is also not advisable in terms of cost.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram for explaining the operation of an associative memory device, FIGS. 2 to 4 are block diagrams showing a conventional example of a malfunction detection method for an associative memory device, and FIG. 5 is an embodiment of the present invention. FIG. 2 is a block diagram illustrating an example. SR...Source information register, ISR...Source information, PsR...Source information parity bit, AM
(i)...1 entry of associative memory, AMS(i)
... Source field, Psi ... Source field parity bit, AMK (i) ... Synthesis field, C (i) ... Comparison circuit, A (i) ... Exclusive OR gate B (i)...Logic gate.

Claims (1)

[Claims] 1. In an associative memory device that is composed of a data section and a parity section for each entry, a match with input information is first compared between the data section corresponding to each entry in the associative memory device and the data section of the input information. After that, the parity part of the stored content that matches the data part is compared with the parity part of the input information, and if the two do not match, a machine check is generated as a parity error. A malfunction detection method for associative memory devices.