JPS58159369A - Complementary mos integrated circuit device - Google Patents
Complementary mos integrated circuit deviceInfo
- Publication number
- JPS58159369A JPS58159369A JP57043150A JP4315082A JPS58159369A JP S58159369 A JPS58159369 A JP S58159369A JP 57043150 A JP57043150 A JP 57043150A JP 4315082 A JP4315082 A JP 4315082A JP S58159369 A JPS58159369 A JP S58159369A
- Authority
- JP
- Japan
- Prior art keywords
- well
- substrate
- region
- conductivity type
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000295 complement effect Effects 0.000 title abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000010409 thin film Substances 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 8
- 238000012423 maintenance Methods 0.000 claims 2
- 238000000034 method Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 abstract 1
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- OTLGFUHTYPXTTG-UHFFFAOYSA-M indium(3+);oxygen(2-);hydroxide Chemical compound [OH-].[O-2].[In+3] OTLGFUHTYPXTTG-UHFFFAOYSA-M 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009182 swimming Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は相補ａｌ１ＭＯ８集積回路洟置に関する。[Detailed description of the invention] The present invention relates to a complementary a1MO8 integrated circuit arrangement.
従来、相補型ＭＯ８集積回路１ｍ（以下ＣＭＯ８−ＩＣ
と紀す）では、その動作中に入力端子及び出力端子にイ
ンパルス状の雑音が加わると電源端子ｖｎｏと ■Ｉと
の間に数ｍＡから数十ｍＡの異常なＷ流が定常的に流れ
一度電源を切らないと止まらない、この現象をラッチア
ップ現象という。Conventionally, complementary MO8 integrated circuit 1m (hereinafter referred to as CMO8-IC
When impulse-like noise is applied to the input and output terminals during operation, an abnormal W current of several mA to several tens of mA flows steadily between the power supply terminals vno and I. This phenomenon, which does not stop unless the power is turned off, is called the latch-up phenomenon.
この異常電流は電池の寿命を短かくするばかりでな（Ｉ
Ｃ自体の永久的な破壊をまねくこととなる。This abnormal current not only shortens the life of the battery (I
This will lead to the permanent destruction of C itself.
第１図は従来の０ＭＯ８−ＩＣの一例の断面図である。FIG. 1 is a sectional view of an example of a conventional 0MO8-IC.
ＮＷ午導体基板１にＰ十鉦ノース及びドレイン領域８，
９とゲート電極２を設けてＰチャンネルＭＯ８ＦＥＴを
作る。またＰウェル７、、７’を設け、Ｐウェル７内に
Ｎ十型ソース及びドレイン領域１０．１１を設け、絶縁
膜を介（７てゲート２／電極をつけてＮチャンネルＭＯ
８ＦＥＴを作る。NW conductor substrate 1 is provided with P ten key north and drain regions 8,
9 and a gate electrode 2 are provided to form a P-channel MO8FET. In addition, P wells 7, 7' are provided, and N0-type source and drain regions 10 and 11 are provided in the P well 7, and an N-channel MO
Make 8FET.
を九、半導体基板にＰ＋領域１２を設けて基板側入力保
護ダイオードを作９、Ｐウェル７′内にＮ＋領域１３を
設けてＰウェル側入力保−ダイオードを作る。9. A P+ region 12 is provided on the semiconductor substrate to form a substrate side input protection diode (9), and an N+ region 13 is provided in the P well 7' to form a P well side input protection diode.
このように一つの半導体基板にＰ＋領域とＮ＋領領域多
数形成すると、多くの寄生素子が存在することになる。When a large number of P+ regions and N+ regions are formed on one semiconductor substrate in this way, many parasitic elements will be present.
即ち、Ｐ＋領域８を工ばツタ、基板６をペース、Ｐウェ
ル７をコレクタとするＰ十ＮＰ）ランジスタＴ、Ｐ十
領域９ｔ−エミッタ、基板６をペース、Ｐウェル７をコ
レクタとするＰ十ＮＰ）ランジスタＴ、、Ｎ十 領域１
１を工きツタ、Ｐウェル７をペース、基板６をコレクタ
とするＮ十ＰＮ）ランジスタＴ１、Ｎ十 領域１１をエ
ミッタ、Ｐウェル７をペース、基板６をコレクタとする
Ｎ＋ＰＮ）ランジスタＴ４、Ｎ十 領域１３ｔ−エミッ
タ、Ｐウェル７′をペース、基板６をコレクタとするＮ
＋ＰＮトランジスタＴ、等の寄生トランジスタが存在す
る。That is, if the P+ region 8 is fabricated, the transistors T, P1 and NP2, with the substrate 6 as the paste and the P well 7 as the collector, will be formed.
Region 9t - emitter, substrate 6 as a base, P well 7 as collector P0NP) transistor T,, N0 Region 1
N+PN) transistor T1, N0 with region 11 as emitter, P well 7 as paste, and substrate 6 as collector) transistor T4, N 10 Region 13t - N with emitter, P well 7' as pace, substrate 6 as collector
There are parasitic transistors such as +PN transistor T.
ツブ現象に関係する部分の轡価回路図である。FIG. 3 is a circuit diagram of a portion related to the bulge phenomenon.
第２図において、Ｒ１〜Ｒ，はＮＷ基板６の抵抗成分に
よる抵抗、Ｒ４，ｆ’Ｌ、はＰウェル７に含すれる抵抗
成分ＦＬ、はＰウェル７′に含まれる抵抗成分による抵
抗である。この場合、トランジスタＴＩＫｒＩＬれる電
流がトリガとなＬ トランジスタＴ１及びトラ〃スタＴ
４が常時導通状態となり定常電流が流れる。In FIG. 2, R1 to R are the resistances due to the resistance components of the NW substrate 6, R4, f'L are the resistance components FL included in the P well 7, and resistance components FL are included in the P well 7'. be. In this case, the current flowing through the transistor TIKrIL acts as a trigger.
4 is always in a conductive state and a steady current flows.
従来、この現象を防止するために、トランジスタＴ、
及びトランジスタＴ４ のベース幅を大きくとっそ、ト
ランジスタの電流増幅率を１以下にす・ネルＭＯ８ＦＥ
Ｔの間隔を広くする。又は、Ｐウェル７．７′下にＰ＋
の埋め込み鳴を設ける等の処置が考えられていた。これ
らの方法は常時導通状態となるトランジスタの規制で＃
）夛、この効果を得るためにはチップサイズが増大し、
工程が複雑とな！ｌ、０ＭＯ８−ＩＣのコストが鳥くな
るという欠点があった。Conventionally, in order to prevent this phenomenon, transistors T,
And increase the base width of transistor T4 to make the current amplification factor of the transistor less than 1.
Increase the distance between T. Or P+ under P well 7.7'
Measures such as installing an embedded sound were considered. These methods are used to regulate transistors that are always conductive.
) To obtain this effect, the chip size increases,
The process is complicated! 1,0 MO8-IC has the drawback of being expensive.
本発明の目的は上記欠点を除き、ラッチアップ現象を引
き起こすトランジスタの工ｉｙり電流を減少させること
によりラッチアップ現象を起こ１゜に＜＜、かつ小型で
安価に製造できる相補観入４０８集積回ｗＩ裟置を提供
することにある。An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a complementary circuit 408 integrated circuit which can reduce the latch-up phenomenon by reducing the current of the transistor that causes the latch-up phenomenon, and which can be manufactured compactly and at low cost. The aim is to provide the right facilities.
本発明の相補１１ＭＯ８集積回路装置は、−導電型半導
体基板に設けられ該半導体基板と逆導電型の＠１及び第
２のウェルと、 ｍｅｉ＝第１のウェルに設けられた一
導電１１Ｍ０８）ランジスタと、前記第１及び第２のウ
ェル以外の前記＃ｆ−４体基板に設けられた反対導′醋
型ＭＯ８）ランジスタと、前記第１及び第２のウェル以
外の咄記午導体基板に設けられた逆導電を領域と前記半
導体基板とで形成される基板側入力保護ダイオードと、
前記第２のウェル内に設けられた一４′＃ＩＬ型領域と
ＩｉＩ記第２のウェルとで形成されるウェル側入力保躾
ダイオードと、前記半導体基板上に選択的に設けられた
絶縁膜と、該絶縁膜により＃１手導体基板から絶縁分離
されかつ前記基板側及びウェル側人力保麹ダイオードの
逆導電型領域と一導電Ｉｊ＆領域とを接続する導電性＊
＠と、該導電性薄線に接続される入力端子とを富んで＃
ｌ成される。The complementary 11MO8 integrated circuit device of the present invention includes @1 and second wells provided in a -conductivity type semiconductor substrate and of opposite conductivity type to the semiconductor substrate, and a -conductivity 11M08) transistor provided in the first well. and an opposite conductor type MO8) transistor provided on the #f-4 body substrate other than the first and second wells, and an opposite conductor type MO8) transistor provided on the #f-4 body substrate other than the first and second wells. a substrate-side input protection diode formed by the semiconductor substrate and the reverse conductivity region;
a well-side input protection diode formed by a 4'#IL type region provided in the second well and the second well; and an insulating film selectively provided on the semiconductor substrate. and a conductive layer which is insulated and separated from the #1 conductor substrate by the insulating film and connects the reverse conductivity type region and the one conductivity Ij& region of the substrate-side and well-side human-powered koji diodes.
Connect @ and the input terminal connected to the conductive thin wire with #
l will be created.
本発明の実施列について図面を用いて説明する。Embodiments of the present invention will be explained using the drawings.
鶴３図は本発明の一実總Ｈの断面図である。Figure 3 is a sectional view of one piece H of the present invention.
一部電一をＮＷと１．て説明する。−導電一がＰ鈑のと
きは都電ａｔ逆にすれば良い。Some Denichi is NW and 1. I will explain. - When the conductivity is P plate, just reverse the Toden AT.
Ｎ映中４座基徐にＰ誠の帆ｌのウェル７と県２のウェル
７／とｔ設ける。′＃Ｉ４１．＠２のウェル７゜７ノ以
外の＃ｐ４体基敏にＰ十鉦のソース及びドレイン誤植８
，９とゲート２とを設けてＰチャンネルＭ（Ｊ８ＦＥＴ
を作る。ｉｌ！１のウェル７内にＮ１０のソース及びド
レイン領域１０．１１とゲート２１とを設けてＮ？ヤン
ネルＭＯ８ＦＥＴを形成する。画板６にＰ＋領域１２を
設けて基板６とＰ＋−域１２とでｌｋ＆−人カ僚−ダイ
オードを作る０、鉋２Ｏウ、 Ａ、 ７／ ＫＮ” Ｉ
ＩＩＬ域１８１ｔＷｊｌＦＴ、＠２のウェル７１とＮ＋
１１１１１域１３とでフェル調入力泳媛暢ダイオードを
作る。基板６の裏面に絶縁１μを設＆ｊ１各−城に開口
を設け、アル（＝ラム積１６に一装置してコンタクトを
形成する。絶縁膜１５の表面に導電性薄膜１４を設ける
。導電性薄膜１４とＰ十領域１２．Ｎ＋領域１３とを電
気的に接続し、また導電性薄膜１４に入力端子４を接続
する。Well 7 of P Makoto's sail l and well 7 of prefecture 2 will be set up in the 4th base of N-ei. '#I41. @2 well 7゜P4 body base other than #p4 source and drain misprint 8
, 9 and gate 2 to form a P-channel M (J8FET
make. Il! N10 source and drain regions 10.11 and gate 21 are provided in the well 7 of N?1. Form a Jannel MO8FET. A P+ region 12 is provided on the drawing board 6, and a lk&-force diode is made from the substrate 6 and the P+- region 12.
IIL area 181tWjlFT, @2 well 71 and N+
11111 area 13 and make a Fer type input swimming diode. An insulator 1μ is provided on the back surface of the substrate 6, and an opening is provided in each hole, and a contact is formed in the aluminum (=ram product 16).A conductive thin film 14 is provided on the surface of the insulating film 15.A conductive thin film 14 and the P+ region 12.N+ region 13 are electrically connected, and the input terminal 4 is connected to the conductive thin film 14.
ここで、導電性薄膜１４はｌｏＫＯ以上の抵抗値である
ようにする。導電性薄膜の材料としてはポリシリコン、
タングステン、モリブデン、タンクに、酸化ｆタン、二
酸化−，三酸化インジウム尋が適当でおる。Here, the conductive thin film 14 is made to have a resistance value of loKO or more. The material for the conductive thin film is polysilicon,
Tungsten, molybdenum, tan oxide, indium dioxide, and indium trioxide are suitable for the tank.
このような構造にすると、入力端子４と保−ダイオード
との間にＩＯＫΩ以上の抵抗値の抵抗が直夕１ｊ接続さ
れたことになり、＠２図のトランジスタＴ、 ０４４１
１流による抵抗成分Ｒ１の電圧降下を小さくすることが
できる。即ち、トランジスタＴ１ のベース・工ずツ
タ接合バイアスが小さくなってトランジスタＴ、は遮断
状態となってラッチアップ現象は抑制される。With such a structure, a resistor with a resistance value of IOKΩ or more is directly connected between the input terminal 4 and the holding diode, and the transistor T in Figure @2, 0441
The voltage drop of the resistance component R1 due to the first current can be reduced. That is, the base-to-edge junction bias of the transistor T1 is reduced, the transistor T is cut off, and the latch-up phenomenon is suppressed.
以上拝細に説明したように、本発明によれば、ラッチア
ップ現象を抑制し、小型で安価な相補型ＭＯ８集積回路
鋲置装得られるのでその効果は大きい。As described in detail above, according to the present invention, the latch-up phenomenon can be suppressed and a compact and inexpensive complementary MO8 integrated circuit riveting device can be obtained, so that the present invention is highly effective.
＠１図は従来の０ＭＯ８−１０の一列の断面図、給２し
１は観１図に示す０ＭＯ８−ＩＣのラッチアップ１Ａｗ
７１に関係する部分の蝉価回略図、第３図は本発明の一
寮總列の断面図である。@Figure 1 is a cross-sectional view of one row of conventional 0MO8-10, and supply 2 and 1 are latch-up 1Aw of 0MO8-IC shown in Figure 1.
FIG. 3 is a schematic diagram of a portion related to 71, and a cross-sectional view of a single dormitory row according to the present invention.
１°°°・・’ＶＤＤ電＃瑞子、２．２′・・・・・・
ゲート重砲、３・・・・・・インバータ出力４子、４・
・・・・・入力端子、５・・・・・・ＶａＳイ源４子、
６・・・・・・Ｎ馨中導体基板、フ・・・・・・４ｇ１
１） Ｐ ウェル、７′・・・・・・第２０Ｐウエル、
８・ ・・・・・・ＦナヤンネルＭＯ８のソース領域％
９・・・・・・ＰチャンネルＭＯ８のドレイン１［１
＊、１０・・・・・・Ｎ？キャンルＮ１０８のドレイン
鎖板、１１・・・・・・Ｎデャン不ルＭＯ８のソースＶ
ｊｌｉＩ域、１２・・・・・・基板−人カ保捏ダイオー
ド％ １３・・・・・・Ｐウェル鉤人力保謙ダイオード
、１４・曲・導電性１１１ｍ、１５・・・・・・酸化験
。1°°°...'VDD #Mizuko, 2.2'...
Gate heavy artillery, 3... Inverter output 4, 4.
...Input terminal, 5...VaS source 4,
6...N conductor board, F...4g1
1) P well, 7'...20th P well,
8. ... Source area % of F nayan channel MO8
9...Drain 1[1 of P channel MO8
*, 10...N? Drain chain plate of Candle N108, 11... Source V of Ndanfuru MO8
jliI area, 12...Substrate - human power protection diode % 13...P well hook human power protection diode, 14, bend, conductivity 111m, 15...oxidation test .
１６・・・・・・アルイニク五績。16...Aruinik's fifth score.
Claims (1)
電型の第１及び第２のウェルと、前記＠ｌのウェルに設
けられた一導電型ＭＯ８）ランジスタと、＃紀第１及び
第２のウェル以外の前記半導体基板に設けられた反対導
電−ＭＯＳトランジスタと、前記第１及び第２のウェル
以外の前記半導体基板に設けられた逆導電型値域と前記
！Ｐ導体基板とで形成される基板側入力床−ダイオード
と、前記＠２のウェル内に設けられた一導電ａ領域と前
記＠２のウェルとで形成されるウェル側人力保線ダイオ
ードと、藺紀牛導体基板上に選択的に設けられた絶縁膜
と、該絶縁膜により＃起生導体基板から絶縁分離されか
つ前記基板側及びウェル鉤入力保護ダイオードの逆導電
型領域と一尋電Ｕａ域とを接続する導電性薄膜と、該導
電性薄膜に接続される入力端子とを含むことを特徴とす
る相補型ＭＯ８集積回路談置０First and second wells provided in one conductivity type semiconductor substrate and opposite conductivity type to the IP4 body substrate; one conductivity type MO8) transistor provided in the well @l; an opposite conductivity type MOS transistor provided in the semiconductor substrate other than the first and second wells, an opposite conductivity type range provided in the semiconductor substrate other than the first and second wells, and the !P conductor substrate; a board-side input floor diode, a well-side human power line maintenance diode formed by one conductive a region provided in the @2 well and the @2 well, and a well-side human power line maintenance diode selectively provided on the Aikigyu conductor substrate. a conductive thin film which is insulated and separated from the generated conductive substrate by the insulating film and which connects the opposite conductivity type region of the substrate side and the well hook input protection diode to the first electric conductor Ua region; and an input terminal connected to a conductive thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57043150A JPS58159369A (en) | 1982-03-18 | 1982-03-18 | Complementary mos integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57043150A JPS58159369A (en) | 1982-03-18 | 1982-03-18 | Complementary mos integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58159369A true JPS58159369A (en) | 1983-09-21 |
| JPS6361784B2 JPS6361784B2 (en) | 1988-11-30 |
Family
ID=12655807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57043150A Granted JPS58159369A (en) | 1982-03-18 | 1982-03-18 | Complementary mos integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58159369A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51146188A (en) * | 1975-06-11 | 1976-12-15 | Fujitsu Ltd | Diode device |
| JPS5376679A (en) * | 1976-12-17 | 1978-07-07 | Nec Corp | Semiconductor device |
-
1982
- 1982-03-18 JP JP57043150A patent/JPS58159369A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51146188A (en) * | 1975-06-11 | 1976-12-15 | Fujitsu Ltd | Diode device |
| JPS5376679A (en) * | 1976-12-17 | 1978-07-07 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6361784B2 (en) | 1988-11-30 |
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