JPS6361784B2 - - Google Patents
Info
- Publication number
- JPS6361784B2 JPS6361784B2 JP57043150A JP4315082A JPS6361784B2 JP S6361784 B2 JPS6361784 B2 JP S6361784B2 JP 57043150 A JP57043150 A JP 57043150A JP 4315082 A JP4315082 A JP 4315082A JP S6361784 B2 JPS6361784 B2 JP S6361784B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- semiconductor substrate
- well
- region
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 21
- 239000010408 film Substances 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 10
- 230000000295 complement effect Effects 0.000 claims description 6
- 230000002159 abnormal effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 本発明は相補型MOS集積回路装置に関する。[Detailed description of the invention] The present invention relates to a complementary MOS integrated circuit device.
従来、相補型MOS集積回路装置（以下CMOS
−ICと記す）では、その動作中に入力端子及び
出力端子にインパルス状の雑音が加わると電源端
子VDDとVSSとの間に数ｍＡから数十ｍＡの異常
な電流が定常的に流れ一度電源を切らないと止ま
らない。この現象をラツチアツプ現象という。こ
の異常電流は電池の寿命を短かくするばかりでな
くIC自体の永久的な破壊をまねくこととなる。 Conventionally, complementary MOS integrated circuit devices (hereinafter referred to as CMOS
- IC), if impulse noise is applied to the input and output terminals during operation, an abnormal current of several mA to several tens of mA will constantly flow between the power supply terminals V DD and V SS . It won't stop unless you turn off the power. This phenomenon is called the latch-up phenomenon. This abnormal current not only shortens the life of the battery, but also permanently destroys the IC itself.
第１図は従来のCMOS−ICの一例の断面図で
ある。 FIG. 1 is a sectional view of an example of a conventional CMOS-IC.
Ｎ型半導体基板１にP+型ソース及びドレイン
領域８，９とゲート電極２を設けてＰチヤンネル
MOSFETを作る。またＰウエル７，７′を設け、
Ｐウエル７内にN+型ソース及びドレイン領域１
０，１１を設け、絶縁膜を介してゲート２′電極
をつけてＮチヤンネルMOSFETを作る。また、
半導体基板にP+領域１２を設けて基板側入力保
護ダイオードを作り、Ｐウエル７′内にN+領域１
３を設けてＰウエル側入力保護ダイオードを作
る。 A P channel is formed by providing P + type source and drain regions 8 and 9 and a gate electrode 2 on an N type semiconductor substrate 1.
Make a MOSFET. In addition, P wells 7 and 7' are provided,
N + type source and drain region 1 in P well 7
0 and 11 are provided, and a gate 2' electrode is attached via an insulating film to form an N-channel MOSFET. Also,
A P + region 12 is provided on the semiconductor substrate to create a substrate side input protection diode, and an N + region 1 is provided in the P well 7'.
3 to create a P-well side input protection diode.
このように一つの半導体基板にP+領域とN+領
域を多数形成すると、多くの寄生素子が存在する
ことになる。即ち、P+領域８をエミツタ、基板
６をベース、Ｐウエル７をコレクタとするP+NP
トランジスタT1、P+領域９をエミツタ、基板６
をベース、Ｐウエル７をコレクタとするP+NPト
ランジスタT2、N+領域１１をエミツタ、Ｐウエ
ル７をベース、基板６をコレクタとするN+PNト
ランジスタT3、N+領域１１をエミツタ、Ｐウエ
ル７をベース、基板６をコレクタとするN+PNト
ランジスタT4、N+領域１３をエミツタ、Ｐウエ
ル７′をベース、基板６をコレクタとするN+PN
トランジスタT5等の寄生トランジスタが存在す
る。 If a large number of P + regions and N + regions are formed in one semiconductor substrate in this way, many parasitic elements will be present. That is, P + NP with P + region 8 as emitter, substrate 6 as base, and P well 7 as collector .
Transistor T 1 , P + region 9 as emitter, substrate 6
P + NP transistor T 2 with base and P well 7 as collector, N + PN transistor T 3 with N + region 11 as emitter, P well 7 as base and substrate 6 as collector, N + region 11 as emitter, N + PN transistor T 4 with P well 7 as base and substrate 6 as collector; N + PN transistor with N + region 13 as emitter, P well 7' as base and substrate 6 as collector
There are parasitic transistors such as transistor T5 .
第２図は第１図に示すCMOS−ICのラツチア
ツプ現象に関係する部分の等価回路図である。 FIG. 2 is an equivalent circuit diagram of a portion related to the latch-up phenomenon of the CMOS-IC shown in FIG. 1.
第２図において、R1〜R3はＮ型基板６の抵抗
成分による抵抗、R4，R6はＰウエル７に含まれ
る抵抗成分R5はＰウエル７′に含まれる抵抗成分
による抵抗である。この場合、トランジスタT5
に流れる電流がトリガとなり、トランジスタT1
及びトランジスタT4が常時導通状態となり定常
電流が流れる。 In Fig. 2, R 1 to R 3 are the resistances due to the resistance component of the N-type substrate 6, and R 4 and R 6 are the resistance components included in the P-well 7. R 5 is the resistance due to the resistance component included in the P-well 7'. be. In this case, the transistor T5
The current flowing through the transistor T 1 acts as a trigger.
The transistor T4 is always conductive and a steady current flows.
従来、この現象を防止するために、トランジス
タT1及びトランジスタT4のベース幅を大きくと
つて、トランジスタの電流増幅率を１以下にする
方法、即ちＰウエル７，７′の深さを大きくする、
あるいはＰチヤンネルMOSFETとＮチヤンネル
MOSFETの間隔を広くする。又は、Ｐウエル
７，７′下にP+の埋め込み層を設ける等の処置が
考えられていた。これらの方法は常時導通状態と
なるトランジスタの規制であり、この効果を得る
ためにはチツプサイズが増大し、工程が複雑とな
り、CMOS−ICのコストが高くなるという欠点
があつた。 Conventionally, in order to prevent this phenomenon, the base widths of the transistors T1 and T4 are increased to make the current amplification factor of the transistors less than 1, that is, the depth of the P-wells 7 and 7' is increased. ,
Or P channel MOSFET and N channel
Widen the MOSFET spacing. Alternatively, measures such as providing a P + buried layer under the P wells 7 and 7' have been considered. These methods restrict transistors to be always conductive, and in order to obtain this effect, the chip size increases, the process becomes complicated, and the cost of CMOS-IC increases.
本発明の目的は上記欠点を除き、ラツチアツプ
現象を引き起こすトランジスタのエミツタ電流を
減少させることによりラツチアツプ現象を起こし
にくく、かつ小型で安価に製造できる相補型
NOS集積回路装置を提供することにある。 The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to provide a complementary type that is less likely to cause latch-up by reducing the emitter current of a transistor that causes latch-up, and that can be manufactured in a small size and at low cost.
Our objective is to provide NOS integrated circuit devices.
本発明の相補型MOS集積回路装置は、一導電
型半導体基板に設けられ該半導体基板と逆導電型
の第１及び第２のウエルと、前記第１のウエルに
設けられた一導電型MOSトランジスタと、前記
第１及び第２のウエル以外の前記半導体基板に設
けられた反対導電型MOSトランジスタと、前記
第１及び第２のウエル以外の前記半導体基板に設
けられた逆導電型領域と前記半導体基板とで形成
される基板側入力保護ダイオードと、前記第２の
ウエル内に設けられた一導電型領域と前記第２の
ウエルとで形成されるウエル側入力保護ダイオー
ドと、前記半導体基板上に選択的に設けられた絶
縁膜と、該絶縁膜により前記半導体基板から絶縁
分離されかつ前記基板側及びウエル側入力保護ダ
イオードの逆導電型領域と一導電型領域とを接続
する導電性薄膜と、該導電性薄膜に接続される入
力端子とを含んで構成される。 A complementary MOS integrated circuit device of the present invention includes first and second wells provided in a semiconductor substrate of one conductivity type and having a conductivity type opposite to that of the semiconductor substrate, and a MOS transistor of one conductivity type provided in the first well. , an opposite conductivity type MOS transistor provided in the semiconductor substrate other than the first and second wells, an opposite conductivity type region provided in the semiconductor substrate other than the first and second wells, and the semiconductor a substrate side input protection diode formed by the substrate, a well side input protection diode formed by the one conductivity type region provided in the second well and the second well, and a well side input protection diode formed by the second well; a selectively provided insulating film; a conductive thin film that is insulated and isolated from the semiconductor substrate by the insulating film and connects opposite conductivity type regions and one conductivity type region of the substrate side and well side input protection diodes; and an input terminal connected to the conductive thin film.
本発明の実施例について図面を用いて説明す
る。 Embodiments of the present invention will be described with reference to the drawings.
第３図は本発明の一実施例の断面図である。 FIG. 3 is a sectional view of one embodiment of the present invention.
一導電型をＮ型として説明する。一導電型がＰ
型のときは導電型を逆にすれば良い。 One conductivity type will be explained as N type. One conductivity type is P
When using a mold, the conductivity type can be reversed.
Ｎ型半導体基板にＰ型の第１のウエル７と第２
のウエル７′とを設ける。第１、第２のウエル７，
７′以外の半導体基板にP+型のソース及びドレイ
ン領域８，９とゲート２とを設けてＰチヤンネル
MOSFETを作る。第１のウエル７内にN+型のソ
ース及びドレイン領域１０，１１とゲート２′と
を設けてＮチヤンネルMOSFETを形成する。基
板６にP+領域１２を設けて基板６とP+領域１２
とで基板側入力保護ダイオードを作る。第２のウ
エル７′にN+型領域１３を設け、第２のウエル
７′とN+型領域１３とでウエル側入力保護ダイオ
ードを作る。基板６の裏面に絶縁膜を設け、各領
域に開口を設け、アルミニウム膜１６を配置して
コンタクトを形成する。絶縁膜１５の表面に導電
性薄膜１４を設ける。導電性薄膜１４とP+領域
１２、N+領域１３とを電気的に接続し、また導
電性薄膜１４に入力端子４を接続する。ここで、
導電性薄膜１４は10KΩ以上の抵抗値であるよう
にする。導電性薄膜の材料としてはポリシリコ
ン、タングステン、モリブデン、タンタル、酸化
チタン、二酸化錫、三酸化インジウム等が適当で
ある。 A P-type first well 7 and a second P-type well 7 are formed in an N-type semiconductor substrate.
A well 7' is provided. first and second wells 7,
P + type source and drain regions 8, 9 and gate 2 are provided on the semiconductor substrate other than 7' to form a P channel.
Make a MOSFET. N + type source and drain regions 10 and 11 and a gate 2' are provided in the first well 7 to form an N-channel MOSFET. A P + region 12 is provided on the substrate 6, and the P + region 12 is connected to the substrate 6.
Make an input protection diode on the board side with and. An N + type region 13 is provided in the second well 7', and the second well 7' and the N + type region 13 form a well-side input protection diode. An insulating film is provided on the back surface of the substrate 6, an opening is provided in each region, and an aluminum film 16 is arranged to form a contact. A conductive thin film 14 is provided on the surface of the insulating film 15. The conductive thin film 14 is electrically connected to the P + region 12 and the N + region 13, and the input terminal 4 is connected to the conductive thin film 14. here,
The conductive thin film 14 is designed to have a resistance value of 10KΩ or more. Suitable materials for the conductive thin film include polysilicon, tungsten, molybdenum, tantalum, titanium oxide, tin dioxide, and indium trioxide.
このような構成にすると、入力端子４と保護ダ
イオードとの間に10KΩ以上の抵抗値の抵抗が直
列接続されたことになり、第２図のトランジスタ
T5の導通電流による抵抗成分R1の電圧降下を小
さくすることができる。即ち、トランジスタT1
のベース・エミツタ接合バイアスが小さくなつて
トランジスタT1は遮断状態となつてラツチアツ
プ現象は抑制される。 With this configuration, a resistor with a resistance value of 10KΩ or more is connected in series between the input terminal 4 and the protection diode, and the transistor shown in Figure 2
The voltage drop across the resistance component R 1 due to the conduction current of T 5 can be reduced. That is, transistor T 1
The base-emitter junction bias of T1 is reduced, the transistor T1 is cut off, and the latch-up phenomenon is suppressed.
以上詳細に説明したように、本発明によれば、
ラツチアツプ現象を抑制し、小型で安価な相補型
MOS集積回路装置が得られるのでその効果は大
きい。 As explained in detail above, according to the present invention,
Compact and inexpensive complementary type that suppresses latch-up phenomenon
The effect is great because a MOS integrated circuit device can be obtained.
第１図は従来のCMOS−ICの一例の断面図、
第２図は第１図に示すCMOS−ICのラツチアツ
プ現象に関係する部分の等価回路図、第３図は本
発明の一実施例の断面図である。
１……VDD電源端子、２，２′……ゲート電極、
３……インバータ出力端子、４……入力端子、５
……VSS電源端子、６……Ｎ型半導体基板、７…
…第１のＰウエル、７′……第２のＰウエル、８
……ＰチヤンネルMOSのソース領域、９……Ｐ
チヤンネルMOSのドレイン領域、１０……Ｎチ
ヤンネルMOSのドレイン領域、１１……Ｎチヤ
ンネルMOSのソース領域、１２……基板側入力
保護ダイオード、１３……Ｐウエル側入力保護ダ
イオード、１４……導電性薄膜、１５……酸化
膜、１６……アルミニウム膜。
Figure 1 is a cross-sectional view of an example of a conventional CMOS-IC.
FIG. 2 is an equivalent circuit diagram of a portion related to the latch-up phenomenon of the CMOS-IC shown in FIG. 1, and FIG. 3 is a sectional view of an embodiment of the present invention. 1...V DD power supply terminal, 2, 2'...gate electrode,
3...Inverter output terminal, 4...Input terminal, 5
...V SS power supply terminal, 6...N type semiconductor substrate, 7...
...First P well, 7'...Second P well, 8
...P channel MOS source region, 9...P
Drain region of channel MOS, 10... Drain region of N-channel MOS, 11... Source region of N-channel MOS, 12... Substrate side input protection diode, 13... P well side input protection diode, 14... Conductive Thin film, 15... oxide film, 16... aluminum film.
Claims (1)
と逆導電型の第１及び第２のウエルと、前記第１
のウエルに設けられた一導電型MOSトランジス
タと、前記第１及び第２のウエル以外の前記半導
体基板に設けられた反対導電型MOSトランジス
タと、前記第１及び第２のウエル以外の前記半導
体基板に設けられた逆導電型領域と前記半導体基
板とで形成される基板側入力保護ダイオードと、
前記第２のウエル内に設けられた一導電型領域と
前記第２のウエルとで形成されるウエル側入力保
護ダイオードと、前記半導体基板上に選択的に設
けられた絶縁膜と、該絶縁膜により前記半導体基
板から絶縁分離されかつ前記基板側及びウエル側
入力保護ダイオードの逆導電型領域と一導電型領
域とを接続する導電性薄膜と、該導電性薄膜に接
続される入力端子とを含むことを特徴とする相補
型MOS集積回路装置。1 first and second wells provided in a semiconductor substrate of one conductivity type and having a conductivity type opposite to that of the semiconductor substrate;
a MOS transistor of one conductivity type provided in a well of the semiconductor substrate; a MOS transistor of an opposite conductivity type provided in the semiconductor substrate other than the first and second wells; and a MOS transistor of the opposite conductivity type provided in the semiconductor substrate other than the first and second wells. a substrate side input protection diode formed by a reverse conductivity type region provided in the semiconductor substrate and the semiconductor substrate;
a well-side input protection diode formed by a region of one conductivity type provided in the second well and the second well; an insulating film selectively provided on the semiconductor substrate; and the insulating film. a conductive thin film that is insulated and separated from the semiconductor substrate and connects opposite conductivity type regions and one conductivity type region of the substrate side and well side input protection diodes, and an input terminal connected to the conductive thin film. A complementary MOS integrated circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57043150A JPS58159369A (en) | 1982-03-18 | 1982-03-18 | Complementary mos integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57043150A JPS58159369A (en) | 1982-03-18 | 1982-03-18 | Complementary mos integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58159369A JPS58159369A (en) | 1983-09-21 |
| JPS6361784B2 true JPS6361784B2 (en) | 1988-11-30 |
Family
ID=12655807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57043150A Granted JPS58159369A (en) | 1982-03-18 | 1982-03-18 | Complementary mos integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58159369A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51146188A (en) * | 1975-06-11 | 1976-12-15 | Fujitsu Ltd | Diode device |
| JPS5376679A (en) * | 1976-12-17 | 1978-07-07 | Nec Corp | Semiconductor device |
-
1982
- 1982-03-18 JP JP57043150A patent/JPS58159369A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51146188A (en) * | 1975-06-11 | 1976-12-15 | Fujitsu Ltd | Diode device |
| JPS5376679A (en) * | 1976-12-17 | 1978-07-07 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58159369A (en) | 1983-09-21 |
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