JPS58158727A - Priority controlling system of common bus usage - Google Patents

Abstract

PURPOSE:To attain the bus usage control of many processors with a few number of bus usage request lines, by comparing the state of the bus usage request lines on a common bus with a bus usage request outputted from each processor, and recognizing the propriety of the bus usage. CONSTITUTION:In a processor 2, logical elements such as a comparator 23, FFs, AND gates, OR gates and inverters are connected in addition to a controller 21 and a set switch 22. The priority is set for the bus usage request lines with switches S1-S4 of the switch 22, in an example of four lines, BRQ1-BRQ4. In this case, the bus usage request is transmitted even to all the bus usage request lines having lower priority than the set priority, and each processor recognizes the propriety of the bus usage for the state of the bus usage request line on the common bus by comparing 23 the request with the bus usage request outputted from the processor.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a priority control system for use of a common path in a plurality of grosses, that is, a plurality of grosses connected in parallel to a common path, and an fy stem.

! In general, when it comes to bus usage time, the processing time required is long due to the long distance between buses. ,
is used. What is desired for such a multi-pro system, Nuxtem, is that the order of use of common paths by a large number of programs can be properly controlled, that the system is easy to add and change processors, and that bus configuration is easy. For example, it is compact (the number of bus signals III is small).

Generally, in a multi-processor system that uses a common bus, some kind of control is performed on the path usage rights of each group, f, in order to resolve the problem of bus usage conflict between each group and group. . Conventionally, this type of path usage right control method generally gives priority to each 7° loss and tK path, and processes path usage requests from each gross and tK path according to that order. There were two types of methods for implementing this method: a series type and a parallel type.

FIG. 1 shows a schematic diagram of the configuration of a conventional serial path usage control system. Here, l to l are professional and su, respectively, with 1 having the highest priority and l being the lowest.

FIG. 2 is a circuit diagram showing a path usage right control circuit in each of the first and seventh rows (for example, 1) of the 1M.

FIG. 3A is a Thai construction garden showing the timing of an access request to a path when the paths are in a meeting state.

FIG. 3B is a tie construction diagram showing ties when two professionals, t, issue pass use requests at the same time. In these figures, BPRN is a signal that becomes active when there is no bus use request from the upper level, BPRi is a signal indicating that there is no bus use request from the upper level for the lower level, BRQ7 is a signal indicating that the path is currently in use, and BCLK
is a pass clock, REQ is a path use request signal from a CPU (not shown), and END is a bus use end signal from the CPU.

ACK is the same<pass permission signal to CPU,
As is clear from No. 211 and No. 311A, the bus use request (REQ) from professional expert t is sent to a high-ranking station when the path is not in use (q off).

When there is no bus use request from the path (BPRN on), it is accepted, sets 7v and 77 day lag F, and issues a busy signal (B18y on) to the path.

In addition, if two professionals (for example, L and 2) issue a request to use the bus at the same time, as can be seen from the tying diagram in Figure 3B, the 14th order with the highest priority, Su The request to use the bus is accepted, and the request from Pro 7, t2, is made to wait until t, when the use of the bus by Pro 7, S1 ends.

This straight path usage control method has the following problems: (1) The number of devices that can be connected to the path is limited by signal propagation time and system bus speed;
・(2) Due to the Tastem configuration, it is difficult to use the motherboard, and if used, it would require wiring and cutting for each V Stella, making it impossible to standardize and generalize, (3)
No additions, changes, etc. of professional staff or sills shall be made.

There are drawbacks to the city.

Figure 4 shows the configuration of the conventional parallel path usage control method.
, as shown in the diagram. Here, 11 is the bus controller, 1 to 1 are each 11+I-, and the path busy signal (BB
For SF)K, each of the 11 buses is connected to the path controller 11k via a common cable, and the bus use request signal (
BRQl~1) and path use permission signal (PMTl~1)k
Therefore, each professional player is connected to the bus control unit U via a separate line.

FIG. S is a circuit diagram showing the circuit configuration of the pass pull 911 in FIG. will be understood to increase.

FIG. 6 is a circuit diagram showing the path usage control circuit in each processor yt (for example, i)K in FIG. 4, and FIG. FIG. 7 is a timing diagram showing the timing of a pass access request;
Figure B is a timing chart showing the timing when two professional players, Su (Otori and J), issue requests to use the bus at the same time.

#! The operation will be explained with reference to FIG. 5, FIG. 6, and FIG. 7A. Professional, bus use request (REQl)k in t14C
More Tsuri, Tsu 70. FFs are set and a bus use request signal (BRQ i ) is issued. In path controller draw 911, the path is in an empty state (BBSy off 5) at this time.
Therefore, a bus use request (REQ i ) is accepted and a bus use permission signal (PMTi) is sent to the processor.

Send 1m. When P*RyuYSU receives this path use permission signal (PMTl), it
When 7FF1 is set, the path in use signal (Bu
sy) to start using the pass. When the bus use is finished, the use end signal (IND I) is activated.
On the 7th day, 1FFz was reset and the path in use signal (B
B8F).

As can be seen from FIG. 7B, if two professionals S (l and j) issue requests to use the bus at the same time.

Professionals with high priority (11 bus use permission signal (P
MT i ) is given, and #Putase turns on the bus busy signal (BB8F) and starts using the KL-C path.

The bus is used by the low-priority PSE (J).

High process? (It will wait until the use by 17 is finished.

Such a conventional parallel bus control method requires a large number of signal lines (2×11+1) for tK, due to limitations in the number of signal lines.

The normal number of units is 3 to 4 units per system, and 1 unit per system, and it is difficult to expand. In addition, there are other drawbacks such as the need for a bus right control circuit (bus controller).

The present invention has been made to eliminate the drawbacks of the prior art as described above, and therefore, an object of the present invention is to eliminate the problem of a large number of processes sharing a common bus in a multi-processor system. It is an object of the present invention to provide a priority control system for the use of a common bus in which the addition or change of a process is a nuisance and the bus configuration is also a problem.

The gist of this invention is that in a multiple processor system consisting of a plurality of processors connected in parallel to a common bus, n bus use request lines for the common bus are provided, and By assigning each bus request line to each line and giving a weight to each bus request, we assign a priority to each process, and each processor assigns a bus request line to which a path use request has been assigned. At the same time, it also sends a path use request to a path use request lower than the assigned priority, and each process reports the status of the bus use request line on the common bus to the path use request it outputs. The point is that the configuration is such that it is possible to know whether the path is being used or not by comparing it with the request.

Next, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 8 is a circuit diagram showing one example of this invention,
In the figure, a controller 21 is included in the process 2.
', setting switch n, logic elements such as comparator, clear, grill, gate, AND gate, OR gate, I/Putter, etc. are connected as shown. This is a case of 11m4 of bus use request lines B RQ 1 to IRQ4,
1■C, t for the S type can be used, and the priority is set by switches 81 to 84 in the setting switch n.

In addition, each sui.

S1 to S4 are defined as unset 10'' in the open state and valid setting ``1'' in the closed state.Table 1 below shows the priorities and output states to the bus use request line according to the settings of switches 81 to 84. In the example of FIG. 8, the priority is @3''.

Table 1 If the settings of the setting switches S1 to S4 are set according to the path use request line output (set to L-1) in Table 10, the path use request output zero shown in the dashed line in FIG. This is simplified as shown in Figure 9. Figures 1A and 1B are basic time charts of the **th circuit operation.

FIG. 10A shows the situation when a bus usage request is generated when the bus is empty, and FIG.

This shows a case where path use requests are generated simultaneously from the two.

The basic operation will be explained with reference to FIG. 8 and FIG. 10A.

(1) Path use request REQ from controller 21
From K, 170, 1FF1 is set, and a bus use request signal 1-2゛1-i is output.

(2) At this time, if no path use request is output from another process, the self-setting (
A) and the path use request #(B) on the bus match, so the AND gate A1 opens and the PSG signal is output, causing y7a and 1FF to respond.

(3) The bus in-use signal B8Y is outputted to the bus by the 7th part of the FFm, and the path in-use signal ACK is output to the controller 21. N, at this point 7, PffW, 1FFs are reset, n6. (4) The controller 21 starts using the bus and issues an end signal END when its use is finished.

(5) By the end signal END, flip-to-tube F
Fm is OFF L, bus busy signal BaY is OFF L
, opening up bus use.

Next, referring to FIG. 10B, an explanation will be given of the operation when a request to use the bus is issued from two processors at the same time. The priority order of the two Pro 7, f is set to ``3'' for Pro 7, A4t, and ``2'' for Pro 7, Su B.

(1) Pro 7, Su A, and Pro 7 11 are all k at the same time.

Generates the RIQ signal, and from this K, both sets and FF1
is set, and the bus usage fee reimbursement number is output. At this time, the signal lines to which the bus use request signal is output are PRO(, AmBRQm, IIRQ4, ytB-
BRQI and BRQs become 100, and the state number of the bus use request line on the bus is 11Q, 1 page 1j", and BRQ4 is output.

(2) At this time, considering the phantom input of the controller i (actuator) in both processes, the internal setting signal lines 11RQI and IRQ4. Therefore, no coincidence signal is output from the inverter. , On the other hand, in the process B, the internal S setting signal - stone s, mnc1m, [14, a match signal is output from the comparator and the FFI is set.

Use the bus by outputting the BsY signal.

(3) Pukanse, ? During this time, A confirms that the inverters match with Samurai, and only when S1 has finished using the path does the PIG signal become active and uses the bus properly (by setting Firs to -).

If it is set to 5, it will be possible to use n lines without providing a separate bus control circuit (bus controller).
With 11 lines, it is possible to control bus usage rights for (m+1) units and t.

No. US is a circuit diagram showing an applied example of this invention,
The difference from No. ** is that the expansion bus request line (E
BRQs, EBIIQg) is established, and priority at the expansion level is established from the expansion bus use request level switch, timing, coincidence check...circuit 25, k, and then open AND GO (As) is established to use the bus. The request was made to issue a request (BRQI~4).

As a result, it is possible to connect up to (m+1) x (m+1) five printers, up to t, by combining one expansion path use request line and one bus use line.

In the example of Figure 11, m-L n so 4 has 15 professional sevens,
You can connect with ST.

Note that the feature of the example in FIG. 11 is that the AND gate (AI) k
The main point is that the level of the bus use request is determined after determining the priority of the expansion level.

If this function is removed, bus use request signals (BRQn) of different expansion levels will coexist, making it impossible to determine the priority level based on coincidence detection.

5. According to the present invention, in a plurality of 1vx units connected in parallel to a common path, a single bus request line for the common bus is provided, and By allocating one bus to each bus and giving weight to each bus usage request line, each bus
Grant first rank.

At the same time, each pro 7 sends a pass use request to the assigned bus use request line, and at the same time, the pass use request donation "CK" which is lower than the allocated rank also sends a bus use request,
By comparing the state of the bus use request line on the common bus with the bus use request output by itself, each programmer can know whether the path is being used properly or not. It is possible to control the path usage rights of a large number of programs with a small number of bus usage request lines without providing a separate controller.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional serial bus control system, and FIG. 2 is a diagram showing each program in FIG. ? Circuit diagram showing the bus right control circuit in 3rd WJ
A is a diagram showing a request for access to the bus when the bus is in the 9-store state as shown in Figure 2.B is a diagram showing a request for access to the bus when two processors simultaneously issue a request to use the path. 4F is a similar timing diagram for the case, #5 is a circuit diagram showing the configuration of the conventional parallel bus usage control system, and #5 is a circuit diagram showing the circuit aS of the bus controller in FIG. 4. 6rIA is a circuit diagram showing the bus use control circuit in 10th section of FIG. 4, and FIG. Thai ζ blowfish diagram showing the number 7
FIG. B is a similar timing diagram when two 10 cells and t issue path use requests at the same time. FIG. 8 shows an embodiment of the present invention, and FIG. 9 shows an embodiment of the present invention. FIG. 1A is a simplified circuit diagram of the bus use request output section 811, and FIG. Frose, t
FIG. 11 is a circuit diagram illustrating another embodiment of the present invention; FIG. 1.2...1:Process...11! Bus controller, 21 f controller, 22, 241 setting switch,
T-mu. 25=-laying and unloading circuit. Saij Utai No. 37A Wood 3rd grain β Fig. 4 Fig. 5 Fig. 6 off mA BCL. Off torture B? 9 years old to figure 4 years old 10th B

Claims (1)

[Scope of Claims] 1) In a plurality of buses and buses formed by connecting a plurality of buses to a common bus line, n bus use request lines for the common bus are provided. By assigning it to each bus, one by one, and giving weight to each bus request line, each bus is given priority, and each process, t, is assigned a path usage request. Bus usage request IsK
At the same time, a path use request is also sent for each bus use request request lower than the assigned priority level. However, if the state of the bus use request line on the common path is compared with the path use request output by itself, the priority control method for using the common path is based on the fact that it is possible to know from K whether the bus is being used successfully or not.