JPS58158565A - Inspection of logic circuit - Google Patents

Abstract

PURPOSE:To obtain an inexpensive apparatus also capable of detecting troubles in a complicated logic circuit by positioning a probe in contact with each node in an internal circuit according to inspection information. CONSTITUTION:The positions of probes P1 and P2 are controlled sequentially corresponding to the sequence of an inspection pattern with a probe position indicating control block 5. The probe P1 is connected to an inspection pattern application block 2 and operates to render the internal circuit 4b of a logic circuit 4 to be tested direct under a specified condition. The probe P2 is connected to a comparison block 3 to function as probe for direct testing without introducing the output of the internal circuit 4b of the logic circuit 4. Thus, this invention enables simultaneous accessing of the internal circuit in cooperation with an inspection from an input/output terminal thereby realizing a high trouble detection capacity with an inexpensive equipment in an inspection of a complicated logic circuit being tested.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention generally relates to a testing method for testing the quality of logic circuits.

Conventional technology Conventional logic circuit testing involves checking the input/output terminals or...

The quality of the circuit under test was tested by applying a test pattern from a Kenzan probe made to suit the circuit under test, but the former method requires a large number of circuit stages and is not practical for testing when the logic becomes complex. It is difficult to create the pattern, the failure detection ability of the test distortion pattern is reduced, and the number of man-hours required to create the test pattern is significantly increased. - In the latter case, the Kenzan probe jig is unique to the circuit under test, so the cost of the jig increases as the number of target products expands, resulting in extremely expensive testing equipment. 1. Purpose of the Invention An object of the present invention is to provide an inexpensive transverse distortion method with high R detection capability for various types of complex logic circuits.

To achieve the above object, the testing method of the present invention includes at least one bin of movable probes for applying signals to internal circuit nodes of a logic circuit under test or observing multiple signals from internal circuit nodes. In the conventional inspection method, for faults that are difficult to detect with the inspection method from one input/output terminal, accessible internal circuit nodes and inspection patterns are created in advance to observe the application of signals, and this inspection information is used. Accordingly, the glove is positioned and brought into contact with each internal circuit node, and a corresponding test pattern is supplied to the logic circuit under test, thereby making it possible to detect failures that were previously undetected.

Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram for testing a logic circuit. 1 is a block that stores inspection information. 2 is a block that applies a test pattern to the logic circuit under test; 3 is a block 1 that stores the output from the logic circuit under test and test information;
A block 4 is a logic circuit under test, which is compared with the expected value of the output from the circuit to determine pass/fail. 5 is a block that controls the glove position instruction of the movable probe p+f2.

FIG. 2 shows the contents stored in block 1 that stores inspection information, where It-In corresponds to the input terminal of the logic circuit under test, 0r-On corresponds to the output terminal, p+α corresponds to the globe P1, pxh respectively correspond to probe P2,
Logical values for each test pattern are stored. Also pl
h and p2b correspond to probes pr and p2, respectively,
Probe position instruction information for each inspection pattern is stored.

In testing a logic circuit, input test patterns 11 to In are generally applied to the logic circuit under test 4 from a block 2 for applying inputs. As a result, the internal circuit blocks 4a, Ah, and 4c of the logic circuit under test operate in sequence, and the operation results are obtained at the output terminals. On the other hand, inspection information storage block 1
The expected output 01-om of the logic circuit under test 4 is stored in . These two signals 1 and 1 are led to a comparison block 5 to determine whether they are good or bad.

However, as the scale and complexity of logic circuits under test increase, the method described above is increasingly unable to guide faults in internal circuit blocks 4α and Ah to the output terminals via internal circuit block 4c. This results in a decline in fault detection ability.

In the present invention, in order to detect a failure that would go undetected due to the above-mentioned reason, the probe p1. The above-mentioned problems have been solved by bringing the pz into contact between accessible internal circuit blocks as necessary to provide optimal conditions for detecting the undetected faults.

Figure 1 shows an example of a 2-pin probe, probe p1. The probe position IN of p2 is sequentially controlled by the probe 1□' position instruction control block 5 in accordance with the test pattern sequence. The probe P1 is connected to the test pattern application block diagram and operates to directly bring the internal circuit 4h of the logic circuit under test 4 into a predetermined state. The globe P2 is connected to the comparison block 3 and does not lead the output of the internal circuit 4h of the logic circuit under test 4 to the output terminal.
Acts as a direct testing probe.

In this way, the present invention achieves high fault detection capability in testing complex logic circuits under test using inexpensive equipment by simultaneously accessing internal circuits in conjunction with testing from input/output terminals. Can be done.

Effects of the Invention By using the method described above, the failure detection ability can be reduced by about 30% compared to the conventional method, and the jig cost can be reduced to 115 or less than that of the Kenzan bulk probe.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.
The figure is an explanatory diagram of the present invention. 1...Test information storage unit. 2...Test pattern application section, 3...Output pattern comparison section, 4...Logic circuit under test, 5...Probe position instruction control section. Representative Patent Attorney Susuki 1) Li1□#-1゜L(

Claims (1)

[Claims] 1. When testing a logic circuit that has multiple input/output terminals and multiple accessible internal circuit nodes, at least one of the internal circuit nodes mentioned above is selected and contacted at the same time to provide a temporary testing input. The probe which can apply and observe the -C test pattern as an output terminal is sequentially switched in accordance with a series of test patterns prepared in advance.
(□) A logic circuit testing method characterized in that each time this switching is performed, the previously prepared test pattern is applied to the logic circuit under test to test whether the logic circuit under test is good or not.