JPH0280987A - Inspection apparatus of logical circuit - Google Patents

Abstract

PURPOSE:To perform inspection at a high speed by a method wherein the output values between a plurality of inspection circuits are compared and, when non- coincidence is generated, a circuit to be inspected having a minority output value is confirmed to be inferior to judge a logical circuit. CONSTITUTION:In judging the quality of each of circuits 20-22 to be inspected, the output expected value calculated by a trouble simulation control part 13 and the output value of the circuit to be inspected having the minority output value shown by a test number 1 are compared by an output value comparator 12 and, when non-coincidence is generated, the circuit to be inspected having a majority output value is judged to be an inferior circuit and data of a non- coincidence logical circuit ratio and a non-coincidence logical circuit number are altered to the data of the circuit to be inspected having the majority output value. Since a logical circuit number has '1' different from other output value in a test number 2, a logical circuit number (n) is judged to be inferior because said number has '0' in a test number (n). Further, it is checked whether a non-coincidence dictionary 14 is formed and, when there is no non-coincidence, all of the circuits 20-22 to be inspected are regarded as a good product.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an inspection method for integrated circuits and printed circuit boards,
In particular, the present invention relates to a logic circuit testing device capable of pointing out faulty parts at high speed and with high quality, regardless of input test patterns.

[Conventional technology]

As described in Japanese Unexamined Patent Publication No. 61-117471, a conventional inspection device inputs the same signal to a circuit to be inspected and a non-defective logic circuit, and compares the output signals to determine pass/fail. For this reason, it is necessary to prepare a non-defective circuit whose logical operation is guaranteed before testing, and no consideration has been given to determining pass/fail based only on the output logic value of the circuit under test and pointing out faulty parts.

[Problem to be solved by the invention]

The above conventional technology does not take into consideration the comparison of output values between circuits under test, and requires a good logic circuit with guaranteed logic operation to be prepared before performing a logic test. There were also problems in that it was not possible to pinpoint the faulty part.

An object of the present invention is to use a testing device that simultaneously tests multiple circuits under test to verify the output value of each circuit under test, thereby making it possible to determine whether the circuits under test are good or not, and to point out a faulty part. The purpose of this invention is to provide an inspection device that is suitable for use.

[Means to solve the problem]

In order to achieve the above objective, the output values of multiple test circuits are compared, and if a mismatch occurs, the test circuit with the minority output value is recognized as defective. It is possible to judge whether the product is good or bad.

Furthermore, in order to guarantee pass/fail judgment, if a discrepancy occurs in the output values of the tested circuit, the test pattern number, discrepancy tested circuit number, and percentage of discrepant circuits among all tested circuits are registered. Based on the dictionary, we perform a fault simulation for only the test pattern in which a mismatch was found, compare the expected output value with the output value of the circuit under test, and recognize whether there is a match. This guarantees the quality of the test circuit and increases its reliability.

[Effect]

In the inspection results of logic circuits, the ratio of non-defective products to defective products is much higher. This is due to improvements in process technology. Therefore, when the output values of a plurality of circuits to be tested are compared and a mismatch occurs, the circuit to be tested having the minority output value can be regarded as a defective logic circuit.

However, the circuit under test having this minority output value is not necessarily a defective logic circuit. Therefore.

If the same test pattern is input to multiple circuits under test at the same time and there is a discrepancy in the output values obtained,
The test pattern number in which a mismatch has occurred, the number of the circuit under test having a minority output value, and the ratio of the circuit under test having a minority output value among all circuits under test are registered in the mismatch dictionary. After performing these procedures for all test patterns.

A pass/fail judgment is made using a mismatch dictionary. First, using the test pattern when the mismatch occurred, find the output value of a good sample circuit or a normal circuit using a fault simulator, and compare it with the output value of the circuit under test that has the minority output value in the mismatch dictionary. If they do not match, it is determined to be a defective product, and if they match, the circuit under test having the majority output value is determined to be a defective product. In addition, in all the test patterns, when the output values are slightly softened, the judgment of pass/fail can be guaranteed by comparing the randomly extracted circuits to be inspected with the output values of the failure simulation.

In addition, by adding the fault parts that can be detected by each test pattern in the fault simulator to the mismatch dictionary,
It becomes possible to point out a faulty part of a circuit to be inspected that is determined to be defective using multiple test patterns.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1, 2, 3, and 4.

In FIG. 1, a plurality of circuits 20 to 22 to be tested do not have good sample circuits whose logical operation is guaranteed.
It is composed of only the circuits to be tested 20 to 22.

Inspection test patterns are simultaneously input to the circuits under test 20 to 22 from the test pattern generation section II.

As a result, the output values of the circuits to be tested 20 to 22 are simultaneously taken into the compressors 15 to 17, the plurality of signals are coded and converted into one signal, and then the output values are taken into the output value comparator 12.

This captured output value is subjected to a ratio V calculation in the output value comparator 12, and if a mismatch occurs, the test pattern number at the time of the mismatch is stored in the mismatch dictionary 14 in the format shown in FIG. The number of the circuit to be tested having a minority output value and the ratio of the circuit to be tested having the minority output value to all the circuits to be tested 20 to 22 are registered. Here, the unmatched logic circuit ratio is the ratio of circuits that have internal matching output values among all circuits to be tested, and the faulty part is the faulty part pointed out by fault simulation. These procedures are repeated until all test patterns are exhausted. When this repetition is completed, control is passed to the failure simulation control unit 13 shown in FIG.

In the failure simulation control unit 13, the mismatch dictionary 14
Based on the information on the test pattern series when the mismatch occurs, the expected output value of a normal circuit and the faulty part that can be detected by the test pattern series are additionally registered in the mismatch word #14 in the format shown in FIG.

The pass/fail judgment of the circuits under test 20 to 22 is made by using the expected output value obtained by the failure simulation control unit 13 and the output value of the circuit under test having a minority output value as shown in test number 1 in FIG. A comparison is made by the comparator 12, and if a mismatch occurs, it is determined that the circuit is defective.

On the other hand, if the output values match, the circuit to be inspected having the majority output value is determined to be a defective circuit, and the information on the mismatch logic circuit ratio and mismatch logic circuit number in the mismatch dictionary 14 is transferred to the circuit having the majority output value. Update to the information of the circuit under test. Figure 4 shows
The circuit under test 20 is determined from the output logic values of the circuits under test 20 to 22.
This is the result of determining the pass/fail of 22. Logic circuit number (1
, n are judged to be defective. Logic circuit number α
has a different output value of '1' from other output values in test number 1, so logic circuit number n has an I value in test number n.
It was determined to be defective because it had O+. On the other hand, it is checked whether the mismatch dictionary 14 has been created, and if there is no mismatch, all the circuits to be tested 20 to 22 are considered to be good products.

In order to guarantee this pass/fail judgment, we randomly extract one circuit under test, perform a fault simulation using a part of the test pattern, and compare the output value of the circuit under test with the output value of the fault simulation. compare. If there is a match in this comparison, it can be guaranteed that all of the nine same paths 20 to 22 to be tested are non-defective. On the other hand, if they do not match, it is re-determined that all of them are defective. Failure analysis is performed using this discrepancy dictionary 14.
It is done based on. For example, as shown in FIG. 2, the circuit under test 20 has test number 1. and No. 100, and the failure location is a common value. Therefore, it can be pointed out that the failure exists at the force point (■) shown in FIG.

Therefore, according to this embodiment, the circuit under test can be tested at high speed.
This has the effect of achieving high quality.

〔Effect of the invention〕

According to the present invention, before testing, a plurality of circuits to be tested are simultaneously tested without preparing a non-defective test circuit whose logic operation is guaranteed, and a minority logic value is determined from the comparison result of each output logic value. Since the logic circuit can be determined to be a defective logic circuit, it is possible to perform parallel testing of the circuits to be tested when testing the logic circuit, thereby enabling high-speed testing.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram of a multi-test circuit testing device according to an embodiment of the present invention, and FIG. 2 shows an output to a mismatch dictionary when the output logical values between the test circuits in FIG. 1 become inconsistent. FIG. 3 is a diagram for explaining information, and FIG. 3 is a logical configuration diagram of a circuit under test, and FIG. 4 is a diagram showing output logic values and test results. DESCRIPTION OF SYMBOLS 1... Inspection device, 11... Test pattern generation part, 12... Output value comparator, 13... Failure simulation control part, 14... Mismatch dictionary, 15-17... Compressor. 20-22...Circuit to be inspected, 30-32...Drive terminal for inspection, 33-38...Observation terminal for inspection,

Claims (1)

[Claims] (1) In an apparatus that uses an integrated circuit or a printed circuit board as a circuit to be tested and tests the quality of the circuit to be tested based on the output results obtained from the circuit to be tested, a plurality of circuits to be tested are handled at one time, The output values obtained by the test patterns input simultaneously to these multiple circuits under test are compared between each circuit under test, and if there is a mismatch, the circuit under test with the minority output value is regarded as a defective circuit, and A logic circuit inspection device is characterized in that it performs a failure simulation on a defective circuit, guarantees the determination of a defective logic circuit, and points out a failure location.