JPH05341005A - Failure detection system - Google Patents

Abstract

PURPOSE:To shorten the focusing time and reduce the amount of memory usage in the focusing process by focusing a multifold trouble only through assumption of a single trouble using a trouble throttling system for a failed circuit. CONSTITUTION:On the basis of tester error observation point information 5, fan-in trace is conducted by a by-point circuit grouping means 1 from each error observation point to make grouping of failed circuits classified by the error observation points. An error probability calculating means 3 assumes the failure to perform trouble simulation and calculates the error probability from the number of times, at which the error observation point of the circuit group where this assumed failure exists is judged as error by tester, and the frequency of failure sensing according to the failure simulation of the error observation point, and the determined error cause 12 is emitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI failure detection system, and more particularly to a failure detection system that narrows down failure locations of an LSI.

[0002]

2. Description of the Related Art Narrowing down of failure points of an LSI is performed by comparing the state value of an observation point by an IC tester with the state value of an observation point by a failure simulation assuming a multiple failure or a single failure.

In such a conventional LSI failure location narrowing method, a large amount of time and memory capacity are required when multiple failures are assumed, and multiple failures are required when a single failure is assumed. Has the drawback that it cannot be narrowed down sufficiently.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide a fault detection system capable of reducing the narrowing time and the memory capacity by narrowing down multiple faults only on the assumption of a single fault. is there.

[0005]

A failure detection system according to the present invention comprises, for each error observation point, circuit information of a logic circuit to be detected and error observation point information in which an error observation point at which an error should be observed by a tester is predetermined. A means for detecting a single circuit group that affects only that observation point and a duplicate circuit group that affects not only that observation point but also another error observation point, and performing circuit grouping corresponding to the error observation point. And means for performing a fault simulation while inputting a predetermined test pattern to each predetermined fault definition point in each circuit group corresponding to this error observation point, and a circuit having a fault point assumed in this fault simulation The state value of the error observation point corresponding to the group and the normal state of the error observation point when the test pattern is input And further, means for calculating the error occurrence probability of the error observation point using the state value of the error observation point previously obtained by the tester using the test pattern. .

[0006]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic system block diagram of an embodiment of the present invention. First, each of the information 4 to 9 used in the embodiment of the present invention will be described. LSI logic circuit information 4
Is information on a logic circuit to be detected as a failure, for example, the circuit shown in FIG. 2 is previously filed as information.

The tester error observation point information 5 is information indicating the position of an observation point in a predetermined logic circuit where an error should be observed by the tester, and is, for example, position information of each point A to C shown in FIG. is there.

The fault definition information 6 defines in advance the position of a node in which a fault is likely to occur in the logic circuit, and is, for example, information indicating the node position of the X mark and the star mark shown in FIG.

The test pattern 7 is input pattern information used when a failure simulation of a logic circuit is performed.
In this embodiment, 10 sets of input patterns shown in FIG. 5 are used. The failure simulation is performed by the test pattern of FIG. 5, but in addition to this, the input pattern 7 is also used for the observation by the tester (not shown) of the logic circuit, and the tester observation is performed in advance by the ten input patterns 7. It is assumed that the state value of each error observation point, which is the test result, is stored as a tester observation value 9 in a file.

The normal value information 8 is a file in which a normal value (expected value) at each error observation point when the logic circuit is operated by the test pattern 7 is stored in advance.

The error observation point circuit grouping means 1 is
If the LSI logic circuit information 4 and the tester error observation point information 5 are input, fan-in tracing is performed from the error observation point, and if there is only a single circuit group that affects only that observation point and that observation point The redundant circuit groups that also affect other error observation points are detected, and the error observation points are grouped and the circuit group division information 10 is output.

The target fault grouping means 2 receives the LSI logic circuit information 4, the circuit grouping information 10 and the fault definition information 6 as input, divides the faults subject to error into groups, and deviates from the group. The failure is reduced from the target failure and the error target failure information 11 is output.

The error probability calculating means 3 has a test pattern 7
And error target failure information 11 and tester error observation point information 5
Input and, and perform a failure simulation for each failure with the test pattern 7, compare the error observation point value of the failure group with the error observation point value of the tester, and obtain the error cause 12. Output.

FIG. 2 is an example of a circuit model of a faulty circuit targeted by the embodiment of the present invention. Based on the tester error observation point information 5, the error cause 12
To pursue. In the fault circuit LSI 20, it is assumed that the fault point a is a stuck-at-1 fault and the fault point b is a stuck-at-0 fault.

FIG. 3 shows an example in which the error observation points are divided into groups. When fan-in tracing is performed from each of the error observation points A, B, and C, the observation point A has no overlapping portion with other observation points, and the portion fan-in traced from the observation point A is set as a group A1. Since the observation point B has an overlapping portion with the observation point C, the overlapping portion is a group BC1 and the other portions are a group B1. The observation point C is a group C1 except the portion overlapping the observation point B.

FIG. 4 shows an embodiment in which target faults are divided into groups. When the fault definition information 6 is divided into groups according to the grouping shown in FIG. 3, the fault groups A1, BC1, B
It can be divided into four groups, C1 and C1. Faults out of this group, faults to be excluded c, d, e, f, g
Are excluded from the target failure.

FIG. 5 shows an example of the test pattern 7. It is assumed that this test pattern is a test pattern in which a tester has found a failure in the circuit of FIG.

FIG. 6 shows the output pin value in the tester and the output pin value (normal value) of the logic simulation when the test pattern of FIG. 5 is applied. In the figure, E indicates that the determination result is an error.

FIG. 7 shows an example when a failure simulation is carried out assuming failure points a and b. This result is the result of the failure simulation assuming the failure points a and b as a single failure.

FIG. 8 shows an embodiment in which the error probability of the target failure is obtained by the conventional method. The error probability is calculated using Equation 1.
In Equation 1, (the number of error outputs of each Σ error pattern) is
The output value of the tester in the test pattern 7 and the output value in the logic simulation are different numbers, and “1
In Expression 1, (the number of times of failure detection) is defined as the output value (FIG. 7) when the failure is defined at a certain position (a in this example) and the test pattern 7 is given, and E of FIG. Is the number of times the output value of the tester where
A comparison between FIG. 6 and FIG. 7 yields “6”. Therefore, the error probability from Equation 1 is 55%. When the failure point b is assumed (the number of times of failure detection), it is "5", and the error probability is 45% from Equation 1 as well.

The failure point a appears only at the error observation point A, and the failure point b appears only at the error observation points B and C, so that the error probability is as described above. Therefore, in the conventional method, the failure points a and b may be the cause of the error, but it is not certain. In this case, failure a,
In the case where b actually exists, the fault a propagates only to the output pin A and the fault B propagates only to the output pins B and C, respectively, and therefore the formula 1 does not reach 100%. Since the influence range of the failure is not taken into consideration in Expression 1, the probability is low.

FIG. 9 is an example in which the error probability of the target failure is obtained by the method of the present invention, and the error probability is obtained by the equation 2 which is the result of considering the affected range. In this equation 2, since the fault a propagates to the output pin A, the output pin A
The number of errors in the output pin A is set as the denominator, and the number at which the value of the output pin A matches the value at the output pin A when simulation is performed by defining the failure a and the value of the output pin A (number of error occurrences) are used as the numerator. .

The number of errors in the tester at the error observing point A is "6" from FIG. 6, and the number of errors in the tester at the error observing point BC (BorC, hereinafter the same) is "5".
Is. The number of failure detections assuming the failure point a is
Comparing FIG. 6 and FIG. 7, since the failure point a exists in the failure group A, the failure detection frequency at the error observation point A is “6”. Therefore, the error probability of the error observation point A for the failure point a is 100%.

When the failure point b is assumed, the number of failure detections is "5" when comparing FIG. 6 and FIG. 7, since it is present at the error observation point BC for the failure point b. Becomes Therefore, the error probability of the error observation point BC for the failure point b is 100%. This failure point b naturally exists also in failure groups B and C. Therefore, the error probabilities of the error observation points B and C for the failure point b are 100%.

From this result, it can be said that multiple faults at fault points a and b have occurred. Therefore, failure points a and b
Error cause 10 can be output. In this case, the cause of the error can be pursued without obtaining the error probabilities of the error observation points B and C, but it is necessary to obtain it in the case of FIG.

FIG. 10 is an example showing a failure location. Here, it is assumed that the actual failure is the stuck-at-1 failure at both the failure points x and y, and the failure point b is not the actual failure. FIG. 11 shows output values and normal values on the tester. 12
Is the result of the failure simulation assuming the failure points b, x, and y.

FIG. 13 is an example of obtaining the error probability.
As for the error probability of the error observation point BC when the failure point b is assumed, comparing FIG. 11 and FIG. 12, the error count of the error observation point BC is “5” and the failure detection count is “0”, which is 0%. Is. The number of times of failure detection at the error observation point BC when the failure point x is assumed is “2”, which is 40%. The number of times of failure detection at the error observation point BC when the failure point y is assumed is "3", which is 60%. In this case, it cannot be said that the failure points x and y are the causes.

However, when the error probabilities of the error observation points B and C are calculated, the failure point x is included in the failure group B. Therefore, when the error probability of the error observation point B is calculated, the number of errors is " Since the failure detection frequency is "2" and the failure detection frequency is "2", it is 100%, and the failure point y is included in the failure group C. Therefore, when the error probability of the error observation point C is calculated,
Since the number of times is "3" and the number of times of failure detection is "3", it is 100%. Therefore, the error cause 10 of the failure points x and y can be output.

In the above example, the failure points a, b and x, y have been described as an example. However, since the above-mentioned processes are sequentially applied to all the failure points other than the exclusion target failure points shown in FIG. is there.

[0031]

As described above, according to the present invention, the error probabilities can be increased by grouping the target faults by the error observation points and assuming the error observation points to be observed. Even in the case of multiple failures, it becomes possible to easily investigate the cause of the error by performing failure simulation based on the assumption of a single failure. Therefore, it is possible to significantly reduce the error cause pursuit time in the case of multiple failures, and it is also possible to reduce the amount of memory used.

[Brief description of drawings]

FIG. 1 is a schematic system configuration diagram showing an embodiment of the present invention.

FIG. 2 is a circuit model diagram targeted by an embodiment of the present invention.

FIG. 3 is a diagram showing an example of grouping for each error observation point of the circuit model of FIG.

FIG. 4 is a diagram showing an example of grouping of target faults based on the grouping of FIG.

FIG. 5 is a diagram showing an example of a test pattern.

FIG. 6 is a diagram showing an example of output values and normal values in a tester.

FIG. 7 is a diagram showing an example of output values in a failure simulation.

FIG. 8 is a diagram showing an example in the case of calculating a conventional error probability.

FIG. 9 is a diagram showing an example of calculating an error probability according to the present invention.

FIG. 10 is a diagram showing another example of a failure location.

FIG. 11 is a diagram showing another example of output values and normal values on the tester.

FIG. 12 is a diagram showing another example of output values in a failure simulation.

FIG. 13 is a diagram showing another example of the case of calculating the error probability of the present invention.

[Explanation of symbols]

 1 Circuit grouping means by error observation point 2 Target failure grouping means 3 Error probability calculating means 4 LSI logic circuit information 5 Tester error observation point information 6 Failure definition information 7 Test pattern 8 Normal value 9 Tester observation value 10 Circuit grouping information 11 Failure information for error 12 Cause of error

Claims (2)

[Claims] 1. From the circuit information of a logic circuit to be detected as a fault and the error observation point information in which an error observation point at which an error should be observed by a tester is predetermined, each error observation point affects only that observation point. A means for detecting a single circuit group and a duplicate circuit group that affects not only its observation point but also other error observation points and dividing the circuit groups into corresponding error observation points. Means for performing a fault simulation while inputting a predetermined test pattern to each predetermined fault definition point in each circuit group, and the error observation point corresponding to the circuit group in which the fault point assumed in this fault simulation exists State value, the normal state value of the error observation point when the test pattern is input, and the test pattern is used. And a state value of the error observation point previously obtained by the tester, and means for calculating an error occurrence probability of the error observation point. 2. The means for calculating the error occurrence probability comprises:
The error occurrence probability is calculated based on the number of error occurrences by the tester and the number of failure detections by the failure simulation at the error observation point corresponding to the circuit group in which the assumed failure location exists, and the assumption is made when the probability is 100%. The failure detection system according to claim 1, wherein the failure location is detected as an actual failure location.