JPH04203982A - Semiconductor test device - Google Patents
Semiconductor test deviceInfo
- Publication number
- JPH04203982A JPH04203982A JP33618290A JP33618290A JPH04203982A JP H04203982 A JPH04203982 A JP H04203982A JP 33618290 A JP33618290 A JP 33618290A JP 33618290 A JP33618290 A JP 33618290A JP H04203982 A JPH04203982 A JP H04203982A
- Authority
- JP
- Japan
- Prior art keywords
- state
- relays
- memory element
- cpu
- test device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 230000002093 peripheral effect Effects 0.000 claims abstract description 9
- 238000005259 measurement Methods 0.000 abstract description 4
- 230000002950 deficient Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体の電気的特性を測定する半導体試験装
置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor testing device for measuring the electrical characteristics of a semiconductor.
第２図は従来の半導体試験装置のブロック図で、図にお
いて、（１０）は中央処理装置（以下てはＣＰＵと呼ふ
） 、（２＋）、（２２）は状態保持手段、（＋１）、
（１２）はＣＰＵから状態保持手段（２＋）（２２）を
制御する制御線、（４０）は周辺回路で、被試験装置（
以下ＤＵＴと呼ぶ’） （５０）、電圧線（４３）、電
流計（４４）、リレー（４Ｉ）、（４２）を有している
。また、（３１）（３２）は状態保持手段（２＋）（２
２）から周辺回路（４０）へ状態を伝達する手段である
。FIG. 2 is a block diagram of a conventional semiconductor testing device. In the figure, (10) is a central processing unit (hereinafter referred to as CPU), (2+), (22) are state holding means, (+1),
(12) is a control line that controls the state holding means (2+) (22) from the CPU, (40) is a peripheral circuit, and the device under test (
(hereinafter referred to as DUT) (50), a voltage line (43), an ammeter (44), relays (4I), and (42). In addition, (31) and (32) are state holding means (2+) (2
2) to the peripheral circuit (40).
次に動作について説明する。ＣＰ Ｕ （１０）により
状態保持手段（２１）に第１の状態、例えば“１”の状
態を保持させ、リレー（４１）をｏｎ状態にする。Next, the operation will be explained. The CPU (10) causes the state holding means (21) to hold the first state, for example, the "1" state, and turns the relay (41) on.
次にＣＰ Ｕ （１０）により状態保持手段（２２）に
第１の状態、例えは“１”の状態を保持させ、リレー（
４２）をｏｎ状態にする。次にＤ ｔＪ Ｔ （５０）
の端子（５１）に電圧か印加された状態で、Ｄ Ｕ Ｔ
（５０）の端子（５１）の電流を電流計（４４）で読
み取る。次にＣＰＵ （ｌｏ”ｌにより状態保持手段（
２Ｉ）、（２２）に第２の状態例えば“０”の状態を保
持させ、リレー（４１）、（４２）をｏｆｆ状態にし、
測定か完了する。Next, the CPU (10) causes the state holding means (22) to maintain the first state, for example, the "1" state, and the relay (
42) is turned on. Then D tJ T (50)
With a voltage applied to the terminal (51) of the D U T
The current at the terminal (51) of (50) is read with an ammeter (44). Next, the state holding means (
2I), (22) are held in the second state, for example, "0" state, and the relays (41), (42) are turned off,
Measurement or completion.
測定値に対して、良と不良とに判定する。The measured value is judged as good or bad.
従来の半導体試験装置は以上のように構成されていたの
で、リレーとして機械的な接点を持ったものか使用され
、比較的その故障率か高く、リレーか故障することによ
って、測定値か不良と判定されれば、不良ＤＵＴか後工
程に流出しないが、逆にリレーか故障しても良と判定さ
れると、不良ＤＵＴが後工程に流出する可能性かあり、
品質管理上問題である。Conventional semiconductor test equipment was configured as described above, and used relays with mechanical contacts, which had a relatively high failure rate. If it is determined, the defective DUT will not flow to the subsequent process, but on the other hand, if it is determined that it is OK even if the relay fails, there is a possibility that the defective DUT will flow to the subsequent process.
This is a quality control problem.
この場合、通常のときはリレーか故障した場合、必ずＤ
ＵＴか不良と判定されるように周辺回路を構成するのか
一般的である。しかしながら、リレーか故障した場合、
必ずＤＵＴか不良と判定されるかどうかを確認すること
が、リレーの個数か多い場合困難となる。すなわち、リ
レーの故障はショート故障とオーブン故障かあり、個々
のリレーを強制的にそれぞれの故障状態に設定し、測定
値の良不良をチエツクする必要かあるなとの問題点かあ
った。In this case, under normal circumstances, if the relay fails, it will always be D.
It is common to configure peripheral circuits so that the UT is determined to be defective. However, if the relay fails,
When there are many relays, it becomes difficult to confirm whether the DUT is always determined to be defective. In other words, there are two types of relay failures: short-circuit failures and oven failures, and there was a problem in that it was necessary to forcibly set each relay to its own failure state and check whether the measured values were good or bad.
この発明は上記のような問題点を解消するためになされ
たもので、リレーの故障状態の設定を自動的に行うこと
のできる半導体試験装置を得ることを目的とするもので
ある。The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor testing device that can automatically set the failure state of a relay.
この発明に係る半導体試験装置は、リレーをＯｎ状態と
ｏｆｆ状態を制御する状態保持手段内に、リレーの故障
状態を保持する記憶素子を設け、この記憶素子の故障状
態をＣＰＵて制御し、リレーを制御する状態として、ｏ
ｎ ／ ｏ ｆ ｆ状態と故障状態とを選択する選択
手段を設けて、その選択をＣＰＵて制御するようにした
ものである。In the semiconductor testing device according to the present invention, a memory element for retaining the failure state of the relay is provided in the state holding means for controlling the ON state and the OFF state of the relay, and the failure state of the memory element is controlled by a CPU. As the state that controls o
A selection means for selecting the n/off state and the failure state is provided, and the selection is controlled by the CPU.
この発明における選択手段は、任意のリレーをｏｎ１０
ｆｆ状態と故障状態のいづれかに設定することかでき、
リレーの故障状態を任意のリレーで設定することかでき
る。The selection means in this invention selects any relay from on10.
Can be set to either ff state or fault state,
Relay failure status can be set for any relay.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例である状態保持手段のブロ
ック図を示す。図において、 （２＋１）は０ｎ１０ｆ
ｆ状態か故障状態かを設定する状態を保持する記憶素子
、 （２＋２）はｏｎ状態かｏｆｆ状態かを保持する記
憶素子、（２＋３）はショート状態かオーブン状態かを
保持する記憶素子、 （２］５）はリレーを制御する状
態を保持する記憶素子、 （２１４）は記憶素子（２１
５）に記憶素子（２］２）の状態を転送するが、記憶素
子（２１３）の状態を転送するが、記憶素子（２１１）
の状態で選択するセレクタである。FIG. 1 shows a block diagram of state holding means which is an embodiment of the present invention. In the figure, (2+1) is 0n10f
(2+2) is a memory element that holds a state that sets the f state or a fault state; (2+2) is a memory element that holds a state that is on or off; (2+3) is a memory element that holds a short state or an oven state; (2) ]5) is a memory element that maintains the state that controls the relay, (214) is a memory element (21
5) The state of memory element (2) 2) is transferred to memory element (213), but the state of memory element (211) is transferred to memory element (211).
This is a selector that is selected in the state of .
次に動作について説明を行う。記憶素子（２＋２）には
、通常の測定に必要なＯｎ ／ ｏ ｆ ｆ状態をＣＰ
Ｕて設定する。記憶素子（２１３）にはショート／オー
ブンの故障状態をＣＰＵて設定する。記憶素子（２１１
）にはこの測定で状態保持手段を故障状態にするか否か
の状態をＣＰＵて設定する。この設定により、記憶素子
（２＋５）には。ｎ１０ｆｆ／シヨート／オーブンの４
状態のいづれかの状態が設定される。Next, the operation will be explained. The memory element (2+2) stores the On/Off states necessary for normal measurement.
Set it. A short circuit/oven failure state is set in the memory element (213) by the CPU. Memory element (211
), the CPU sets the state of whether or not the state holding means is to be brought into a failure state by this measurement. With this setting, the memory element (2+5) has: n10ff/shoot/oven 4
One of the states is set.
以上のようにこの発明によれば、任意の時点て、任意の
状態保持手段において、ＣＰＵにより故障状態か設定で
き、周辺回路上のリレーが故障した場合に、測定値か不
良となる確認を比較的容易に行うことかできるという効
果がある。As described above, according to the present invention, a failure state can be set by the CPU in any state holding means at any time, and when a relay on a peripheral circuit fails, the measured value is compared to confirm that it is defective. It has the effect of being easy to perform.
第１図はこの発明の一実施例である状態保持手段のブロ
ック図、第２図は従来の半導体試験装置のブロック図で
ある。
図において、（２＋１）、（２＋２）、（２＋３）、（
２＋５） 記憶素子、（２］４） セレクタ。FIG. 1 is a block diagram of a state holding means according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional semiconductor testing apparatus. In the figure, (2+1), (2+2), (2+3), (
2+5) storage element, (2]4) selector.
Claims (1)
れる複数個の状態保持手段と、被試験装置の状態を設定
及び読み取る周辺回路と、上記状態保持手段に保持され
た状態を上記周辺回路に伝達する手段を備えた半導体試
験装置において、上記状態保持手段が、第１の状態状を
保持する第１の記憶素子と、第２の状態を保持する第２
の記憶素子と、上記第１の状態と第２の状態のいづれか
を選択して上記周辺回路に伝達する選択手段と、上記第
１の状態を選択するか上記第２の状態を選択するかの状
態を保持する記憶素子を備えたことを特徴とする半導体
試験装置。A central processing unit, a plurality of state holding means whose states are controlled by the central processing unit, a peripheral circuit that sets and reads the state of the device under test, and a state held by the state holding means to the peripheral circuit. In the semiconductor testing apparatus, the state holding means includes a first storage element that holds a first state, and a second memory element that holds a second state.
a memory element, a selection means for selecting either the first state or the second state and transmitting the selected state to the peripheral circuit, and a selection means for selecting the first state or the second state. A semiconductor testing device characterized by comprising a memory element that retains a state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33618290A JPH04203982A (en) | 1990-11-29 | 1990-11-29 | Semiconductor test device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33618290A JPH04203982A (en) | 1990-11-29 | 1990-11-29 | Semiconductor test device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04203982A true JPH04203982A (en) | 1992-07-24 |
Family
ID=18296505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33618290A Pending JPH04203982A (en) | 1990-11-29 | 1990-11-29 | Semiconductor test device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04203982A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010047275A3 (en) * | 2008-10-24 | 2010-07-08 | 日本電子材料株式会社 | Semiconductor test system and relay driving test method therefor |
-
1990
- 1990-11-29 JP JP33618290A patent/JPH04203982A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010047275A3 (en) * | 2008-10-24 | 2010-07-08 | 日本電子材料株式会社 | Semiconductor test system and relay driving test method therefor |
| US8456171B2 (en) | 2008-10-24 | 2013-06-04 | Japan Electronic Materials Corp. | Semiconductor test system and relay driving test method therefor |
| JP5598764B2 (en) * | 2008-10-24 | 2014-10-01 | 日本電子材料株式会社 | Probe card inspection system and probe card relay drive inspection method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4531394B2 (en) | Test vias and contacts in integrated circuit manufacturing | |
| US6943576B2 (en) | Systems for testing a plurality of circuit devices | |
| JPH04203982A (en) | Semiconductor test device | |
| JP3490661B2 (en) | Circuit device for burn-in test of semiconductor module | |
| JP3241777B2 (en) | Open test equipment for in-circuit tester | |
| KR20000011002A (en) | Bus system and method for diagnosing subscribers interconnected via the bus system | |
| JP2002139552A (en) | Constitution for testing integrated circuit | |
| JPS61170677A (en) | Logical circuit tester | |
| JPH04352445A (en) | Test head for ic tester | |
| KR20100024678A (en) | Probe card for testing semiconductor devices, tester and chip inspection method using the same | |
| JPH11231022A (en) | Inspection method of semiconductor device and device thereof | |
| JP2659043B2 (en) | Channel control device for electrical component testing machine | |
| KR100470989B1 (en) | Verification Probe Card | |
| JPH0365674A (en) | Test of semiconductor | |
| JP2002131372A (en) | Method and device for inspecting semiconductor device | |
| JPH0329752Y2 (en) | ||
| JPS58158565A (en) | Inspection of logic circuit | |
| JPH03239977A (en) | Screening device for integrated circuit | |
| JPS6239708B2 (en) | ||
| JPS596553A (en) | Logic circuit | |
| JPH0510784B2 (en) | ||
| JPS61170676A (en) | Logical circuit tester | |
| JPH02186278A (en) | Part measuring apparatus | |
| KR20010045147A (en) | Relay checking method of semiconductor tester in the test head | |
| JPS61178674A (en) | Self-diagnostic circuit of semiconductor inspection apparatus |