JPS58156283U - Semiconductor device testing equipment - Google Patents
Semiconductor device testing equipmentInfo
- Publication number
- JPS58156283U JPS58156283U JP5327582U JP5327582U JPS58156283U JP S58156283 U JPS58156283 U JP S58156283U JP 5327582 U JP5327582 U JP 5327582U JP 5327582 U JP5327582 U JP 5327582U JP S58156283 U JPS58156283 U JP S58156283U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- testing equipment
- device testing
- gate
- shows
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のMOS FET断続電力印加試験装置
回路、第2図は従来装置のゲート・ソース間電圧、ドレ
イン電流波形例、第3図は本考案の試験装置のゲート回
路周辺部の実施例、第4図は本考案の試験装置の各部の
電流電圧波形、である。
なお図において、1・・・・・・供試素子MO3FET
。
1a・・・・・・ドレイン、1b・・・・・・ソース、
IC・・・・・・ゲート、2・・・・・・主回路電源、
3・・・・・・負荷抵抗、4.4′・・・・・・ゲート
回路、5・・・・・・ゲート電源、6・・・・・・スイ
ッチ、7・・・・・・ゲート負荷抵抗、10・・・・・
・スイッチ用トランジスタ、11・・・・・・ベース信
号ユニット、12・・・・・・抵抗、8・・・・・・ゲ
ート信号(オン期間)、9・・・・・・ゲート信号の立
上り、立下り時のサージ電圧、である。Fig. 1 shows the circuit of a conventional MOS FET intermittent power application test device, Fig. 2 shows an example of the gate-source voltage and drain current waveform of the conventional device, and Fig. 3 shows an example of the peripheral part of the gate circuit of the test device of the present invention. , FIG. 4 shows the current and voltage waveforms of each part of the test device of the present invention. In the figure, 1... test element MO3FET
. 1a...Drain, 1b...Source,
IC...Gate, 2...Main circuit power supply,
3...Load resistance, 4.4'...Gate circuit, 5...Gate power supply, 6...Switch, 7...Gate Load resistance, 10...
・Switch transistor, 11...Base signal unit, 12...Resistor, 8...Gate signal (on period), 9...Rise of gate signal , the surge voltage at the time of falling.
Claims (1)
験装置において、前記半導体素子の印加する信号の立上
り、立下りを緩くする手段を有することを特徴とする半
導体素子試験装置。What is claimed is: 1. A semiconductor device testing device for performing an intermittent power application test on a semiconductor device, comprising means for slowing the rise and fall of a signal applied to the semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5327582U JPS58156283U (en) | 1982-04-13 | 1982-04-13 | Semiconductor device testing equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5327582U JPS58156283U (en) | 1982-04-13 | 1982-04-13 | Semiconductor device testing equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58156283U true JPS58156283U (en) | 1983-10-19 |
Family
ID=30063952
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5327582U Pending JPS58156283U (en) | 1982-04-13 | 1982-04-13 | Semiconductor device testing equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58156283U (en) |
-
1982
- 1982-04-13 JP JP5327582U patent/JPS58156283U/en active Pending
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