JPS58153419A - Logical integrated circuit - Google Patents

Abstract

PURPOSE:To detect the logical degenerated faults and single short-circuit faults of signal lines, by generating an observation signal for test which can be previously determined independently of normal logic by using an optional productterm line out of an AND array. CONSTITUTION:By adding a simple observation signal (g) for test which can be previously determined independently of a normal logical function to be executed by a circuit, all the single short-circuit faults between decoding lines (116-119) to function as an wired AND or OR in a programmable logical array, between product term lines (21-27), between output lines (31-33), and between signal lines generating no feedback loop of each decoder (11-13) and all the single logical degenerated faults of respective signal lines can be detected by the syndrome test of normal output signals (f1-f3) and the observation signal (g) for test.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an easily calibrated logic integrated circuit, and more particularly to a programmable logic play which is easy to test for logic stuck-at faults and short-circuit faults in signal lines.

As logic integrated circuits become larger and more complex due to advances in LSI technology, fault testing is becoming increasingly difficult and expensive. The main inspection costs are the test pattern generation cost and the 7714 line cost, but in general, theory 3! LS I/V
Generating LSI test patterns requires the use of a large computer for a long time, and testing requires a high-grade tester that can apply a large number of test patterns at high speed and determine pass/fail in a short time. Since it is necessary to use this method, the inspection cost becomes very high, which poses a problem. For this reason, various methods of configuring logic circuits that are easy to test have been proposed for the purpose of reducing testing costs.

IEEE Trams, Compute, C-2
9, PP, 442-451゜June 1980. r J, 5avir, “Syndrome −
TeatableD@sign of Combina
tonal C1rcuits" is an inexpensive method that determines the quality of the circuit by adding all 21 inputs tlf to an n-input combinational logic circuit and counting the number of times the output becomes 1 (hereinafter referred to as syndrome). A means of fault testing (syndrome testing) is proposed, and a method of configuring a circuit so that all single-logic stuck-at faults can be detected is shown. However, this easy-to-test configuration of the combinational logic circuit does not guarantee detection of short-circuit failures in signal lines.

Short-circuit faults in signal lines are not necessarily easier to handle than logic stuck-at faults, so they have not been sufficiently studied as a subject for inspection. However, as the density of circuits has increased in recent years, the frequency of short-circuit faults in signal lines has increased, so it has become necessary to consider short-circuit faults in addition to conventional logic stuck-at faults as a subject of fault inspection. Ta.

In view of this situation, it is an object of the present invention to develop a programmable logic array, which is considered to be a useful component for realizing VLSI.
y) According to the above syndrome test, there is a logic stuck-at fault in the signal line and a wired AN between adjacent signal lines.
An object of the present invention is to provide a logic integrated circuit that can also detect a single short circuit fault that functions as a D or an OR.

According to the present invention, a programmable AND array that generates an arbitrary AND of a decoder group that decodes an external input signal, an arbitrary AND of the output signals of the decoder group, and an arbitrary OR of the output signals of the AND array. In a programmable logic array consisting of a programmable OR array and a programmable OR array, a test observation signal that can be determined in advance regardless of normal logic is generated using any one product term line of the AND array. Then, a logic integrated circuit in which the syndrome test is easily performed by observing the signal (glI) can be obtained.

Hereinafter, embodiments of the present invention will be described with reference to drawing t. As for integration, it is easily realized by ordinary technology, so a description thereof will be omitted.

FIG. 1 is a circuit diagram showing a specific embodiment of the testable logic integrated circuit of the present invention. In the same figure, 11 to 1
3 is a 2-bit decoder, 2 is a programmable AND play, 3 is a programmable OR array, 116-1
19 is a decode line, 21 to 27 are product term lines, 31 to 33 are output lines, 211FiAN-I) device with function, 3
11# A device with a 10R function, xlwx is an external input signal, f1 to fsF1 are normal output signals, and y is an observation signal for inspection.

FIG. 2 is a circuit diagram showing a specific embodiment of the decoder 11 shown in FIG.
12 to 115 with a NAND gate. In the same figure,
For NAND gates 112 to 115, each station +
xl ten fs e Xs ten and X! The operation + is executed and the result is output to decode lines 116-119K. However, + represents a logical sum, and - represents a logical negation. The same applies to decoders 12 and 13.

Referring again to FIG. 1, in the logical product array 2, each product term line 2
Logic stallion C*sx of the signal of the decode line where the AND device (corresponding to the e mark of 211) exists in 1 to 27
a+x mountain) 4mu, jc=kihaya et al.(tame jCa+jC mountain) x
sZ*, x1x4xi, Es for, (sei+:
fs2) Q'f;a and Cs2 effect 4 effect are generated respectively, and in the logical OR array 3, a product term in which an OR deno(chair (corresponding to the x mark in 311) exists) is generated in each output line 31 to 33. The logical sum of the line signals is respectively generated.Therefore, the normal output signals f, ~f3 and the inspection observation signal can be expressed by the following equation.

fx = 2 C2Cs2 + Cs2 ) & 4 +
ZxXs (1) fs ” jct&24
＋xs! 2 (2) fs
= (ForjCa+xsL)x42 + CZsEa+
xs”a )’%”s (3)j’ =Zs2Km2
For 2 (4) Equation (1) ~
From (4), when all 26 inputs are applied once to the circuit shown in the figure, the syndromes of the outputs f-, fx, h, and 2 are 18.12.16 and 1, respectively.

The decoder I in Fig. 1 is configured #s as shown in Fig. 2.
At I, the input line of external input signal z and inverter 1
When a short-circuit fault occurs that functions as a connection KAND of the 11 output lines, the normal outputs fx and f remain unchanged, but f
It changes as shown in the following equation.

f; = 2x4 + A%! a However, since the syndrome of h is the same as the syndrome of 9, the above-mentioned short circuit failure cannot be detected by the syndrome test of normal outputs f1 to 9. On the other hand, the test IN measurement signal 2 changes as follows.

v' = (Bird + 4)97^ The syndrome of 2' is 1, whereas the 7' syndrome of 2' is 3, so the above short-circuit fault can be detected by the syndrome test of the observation signal for inspection. It becomes possible. In addition, the input line of the external input signal 4 in the decoder 13 and
Inverter that outputs st (corresponds to 110 in Figure 2)
The same can be said of the AND type short circuit fault between the output line and the output line.

Next, consider a case where a logic 0 stuck-at fault occurs in the human power line of external input signal 4. At this time, the normal output 9 remains unchanged, but fl and 9 change as shown in the following equations.

To f1' - Xs 94 + 4 fs = ZaXs cannot detect a logic O stuck-at fault. On the other hand, the inspection observation signal changes as follows.

7' = Shouma x 4 Appetizers 4 The syndrome of 2 is 1, while the syndrome of 2' is 2, so the syndrome of the observation signal for inspection.
The test makes it possible to detect the logic 0lti regression fault described above. I of input line of external human input signal 4! The same can be said for the salt-1 stuck-at fault.

As mentioned above, by adding the inspection observation signal No expressed by equation (4), a short circuit fault that functions as a wired AND, which could not be detected by the syndrome test of normal outputs f1 to f9, can be detected. and logical stuck-at faults can be detected. As a result, in the logic array configured as shown in Figure 1, a single short circuit between decode lines that function as a wired AND, between product term lines, between output lines, a feed line in each decoder, and a single short circuit between signal lines that does not cause a croup. All faults and single-logic stuck-at faults on each signal line are f1-9 and 7.
It can be detected by the syndrome test. Q. As observation signal 2 for inspection, other than equation (4) K: A 'JC*
'%XaXsXs or (appetizer+l(x,+4)(rs+x
) can also be used to obtain the same effect.

FIG. 3 is a circuit diagram showing another embodiment of the easily calibrated logic integrated circuit of the present invention. The circuit in the same figure and the circuit in FIG.
They have the same structure except that the location of the device and the location of the OR device in the OR array 3 are different. Therefore, in the product term lines 21 to 27 in the figure, the logical product 4 of the signals of the decode line where the AND device exists is 4. Tamemaru, Tamechi 4. x4chi4pa14゜(appetizer+horse)4 and "l tame%'C4k"s are respectively generated, and at the outputs @31 to 33, the logical sum of the signals of the product term line where the OR device exists is generated, The following normal output signals f1 to f9 and observation signal for inspection are obtained.

5 = 44 yen + 4 chi + A94 (5) 9 - 99 + x 444 (6) 44 chibi + (q + x) q (7) 2 = 4 -
%XaQ'Cm (8) Formula (5
) to (8), the syndromes of output ft −A , 9 and 2 are 20, 16.28 and 1, respectively.

Decoder 11 in FIG. 3 configured as shown in FIG.
In , when a short circuit fault occurs between the input line of the external human-powered signal holder and the input line of the external human-powered signal horse, which functions as a wired OR, the normal outputs 9 and 9 remain unchanged, but f,
changes as shown below.

f:= ("s + Q) "sr'Cm + "5
rs-%”a +”1”l”6-%However, f8
Since the syndrome of ``uft'' is the same as the syndrome of uft, the above-mentioned short-circuit failure cannot be detected by the syndrome test of 9 to normal output. On the other hand, the inspection observation signal y changes as follows.

9' = (4 + 4) ``I becomes 5rIO.

Next, logic 1 is applied to the input line of the external human input signal! Consider the case where a regression failure occurs. At this time, the normal output fl and 9 remain unchanged, but 9 changes as shown in the following equation.

ni=4Y.

□ However, since the syndrome 9' is the same as the syndrome 9, the normal output f, ~9 syndrome test cannot detect all of the above logic 1 stuck-at faults. On the other hand, the inspection observation signal i changes as follows.

i'=early i- Since the syndrome of 2 is expressed by 1, the syndrome of 2' is expressed by 2, so the syndrome of the observation signal for inspection is
The test makes it possible to detect the above-mentioned stuck-at-at-logic-1 fault. The same thing can be said about the logic 0/stuck-at fault in the input line of the external input signal x4.

As mentioned above, by adding the inspection observation signal expressed by equation (8), the wired O
Short-circuit faults and logic stuck-at faults that function as R can be detected. As a result, in the logic array configured as shown in FIG. 3, between the decode lines functioning as wired OR,
Single short-circuit faults between product term lines, between output lines, and between signal lines that do not cause a feedback loop in each decoder, and single-logic stuck-at faults on each signal line can all be detected by the f1-9 and 2 syndrome tests. becomes.

A circuit diagram showing another embodiment of 410,411 U
Inverters 412-415 are OR gates. Second
When the decoder shown in the figure is used for the decoder shown in the figure,
By using 499994 as the inspection observation signal V, all single short circuit faults that function as wired AND between the signal lines and single logic stuck-at faults in the signal lines can be detected by the syndrome test. . Also, deaf sleep to -44 4 Q
x4 nine, (appetizer +4) (x, + $4) (enter +4
) as the observation signal for calibration, both a single short circuit fault that functions as a wired OR between the signal lines and a single logic stuck-at fault in the signal lines can be detected by the syndrome test.

The present invention has been explained using an example in which 6 human power is used, 4 to 4, 3 outputs f, to 9, and the product term is 6, but in general, 2α input, β
Of course, it cannot be applied to the case where the product term is γ at the output; in this case, the calibration result 611J signal 2 is as follows depending on the configuration of the short-circuit fault type sedecoder circuit. However, TVa means the logical product of -1, 2, . . . , α.

As explained above in detail, the logic integrated circuit of the present invention has the following features:
By adding simple test observation signals that can be predetermined independently of the normal logic functions implemented in the circuit, the product term between decode lines can function as a wired AND or OR in a programmable binary logic array. All single short-circuit faults between lines, output lines, and signal lines that do not cause a feedback loop of each decoder, as well as single-logic stuck-at faults in the signal lines, can be detected using inexpensive and simple testing means.□
As a result, the logic LS I,,'V
This has a significant effect on reducing LSI inspection costs.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a specific embodiment of the logic integrated circuit of the present invention, FIG. 2 is a circuit diagram showing a specific embodiment of the decoder 11 of FIG. 1, and FIG. FIG. 4 is a circuit diagram showing another embodiment of the logic integrated circuit of the invention. FIG. 4 is a circuit diagram showing another embodiment of the decoder 11 shown in FIGS. In the figure, 11-13...decoder, 116-119...decode line. 2... Logical product array, 21-27... Product term line, 21
1... Device with AND function, 3... Logical sum array. 31-33...Output line, 311...OR function too?
device. 110.11...Inverter, 112-115...
・NAND game), 410, 411・-inverter,
412 to 415: OR gate, 4 to 4: external input signal e, f+ to f3: normal output signal, and no: inspection observation signal, respectively. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] A group of decoders that decode external input signals, a programmable AND array that generates an arbitrary AND of the output signals of the decoder group, and a programmable OR that generates an arbitrary logical interest of the output signals of the AND array. In a programmable logic array consisting of an array of A logic integrated circuit characterized in that syndrome testing is facilitated by observation.