JPS58207719A - Logical circuit easy of inspection - Google Patents

Abstract

PURPOSE:To attain ease of failure check with a simple test input, by producing an exclusive logical sum between all of output signal group of exclusive logical sum of plural input signals and control input signals, and an input signal for check. CONSTITUTION:In the exclusive logical sum gate group 11 of a combined logical block 1, an exclusive logical sum output group XC between each input signal xi(i=1-n) of an input signal group X=(x1-x2) and a control input signal C is outputted. In an AND gate group 12, the AND between the signal groups X and Xc is outputted and inputted to an exclusive logical sum gate group 13. In the gate group 13, the exclusive logical sum between the output signal group of the gate group 12 and some logical constants y1 and X and Xc is taken, an output signal Z1 is produced. The check of a failure in logical degeneration of the signal line is done easily by taking an output of the gate group 13 as an observing signal. Further, a signal short-circuit failure between lines is detected by taking the exclusive logical sum between the signal group Xc and an input signal y2 for check at a logical block 2 and outputting an observing signal Z2 for check.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an easily testable logic circuit that can be tested for failures using simple test inputs that can be created regardless of the logic function of the circuit.

In recent years, as the density of logic circuits has increased due to advances in integrated circuit technology, the frequency of short-circuit failures between signal lines connecting logic elements has rapidly increased. It has become necessary to include failures as a subject of inspection. The circuit is complicated.

When the scale becomes large, it becomes extremely difficult to create efficient test inputs for testing these faults, so it is strongly desired to adopt a circuit configuration that facilitates fault testing. Conventionally, various means have been devised to facilitate the calibration of logic stuck-at faults in signal lines, but little consideration has been given to means for facilitating short-circuit faults between signal lines.

In view of this situation, an object of the present invention is to provide a combinational logic circuit that can detect both single-logic stuck-at faults in signal lines and single short-circuit faults between lines with simple test inputs that can be created independently of the logic function of the circuit. It's about doing.

According to the present invention, a first exclusive OR gate group that generates an exclusive OR of each input signal z, (i=1 to bamboo) $ and a control input signal C; the output signals of the group and the input signals 2. A combination consisting of an AND gate group that generates an AND of ~2 and a second exclusive OR gate group that generates an exclusive OR of the output signal group of the AND GUT group and a logic constant y. In the logic circuit, all of the outputs of the first group of exclusive OR gates -
By adding a third exclusive OR gate that generates the exclusive OR of the input signal 1 and the test input signal 1!2, and using the output signal as an observation signal, a logic circuit that facilitates fault testing can be obtained.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an easily testable logic circuit according to the present invention, and %1 is an exclusive OR gate group 11.1.
3 and a group of AND gates 12, and 2 is a logic block that generates an exclusive OR added to facilitate fault testing.

In the same figure, in the exclusive OR gate group 1, each input signal X of the input signal group
・The exclusive logic of (i = 1-%) and 'ff1lJ ld1 input signal C is logically summed ΦC, and in the AND gate group 12, the signal groups X and Xc
= (ZlΦc, z2cL:, ・=, 23ΦC
), and in the exclusive OR gate group 13, the exclusive logical OR of some of the output signals #,

is generated. The logic block 2 calculates the exclusive OR of the signal group Xc and the input signal for inspection, and outputs the observation signal for inspection Z2.

FIG. 2 is a circuit diagram showing a specific example of FIG. 1. In the combinational logic block 1 of the same figure, the following four human variables X=
There is something that realizes the combinatorial logic of (Zl, $2.~3.~4).

The above combinational logic can be expressed by the following expansion formula.

Z, =Oe &+ @z4e ~2 + $40z3
・z4ezl・~3 (1) However, 0...logical constant,...logical product, -...logical centipede, ■...exclusive OR.

If the value of the control input signal C during normal operation is 1, the output signals of 111 to 114 are each 1
1 to i4, so the logical product is good.) In 121 to 124, the product term i, . . . 4, 4 .'4 v ''R. . . .
・2. are generated respectively. Therefore, the logical constant human power &
If the value of + is 0, exclusive OR gates 131 to 13
4 connections realize the above equation (1). Incidentally, when only the term ˜4 or Xi appears in the above expansion equation, this is also regarded as one product term.

Paper by D. K. Pradhan, ” Univ.
ersal Te5tSets for Multi
ple Fault Detection 1nAN
D-EXORArrays, 〃IBEHTTrans,
, C-27゜pp-181-187, Feb, 1978
As shown in FIG.
Logical product of output signal group (zlec) ・(ztΦC)
- By using (jE3Φe)"(Z4■C) as the observation signal, it is possible to easily test for logical stuck-at faults in signal lines, but short-circuit faults between signal lines cannot necessarily be tested efficiently. It is not possible.

Logic block 2Fi was added to improve efficiency in testing not only logic stuck-at faults but also short-circuit faults.
The exclusive logic between the output signals of the exclusive OR gates 111 to 114 and the test input signal V is Zz = (Z+ΦG
)Φ(jezΦ6)@($3ΦC)■(~4 ec)
(2) Consists of a group of exclusive OR gates 21 to 24 that generate v2.

FIG. 3 is a diagram showing the Wanbei test input set T4 for a single pathological stuck-at fault and a single short-circuit fault between the legs in a four-man variable combinational logic circuit having the configuration illustrated in FIG. 2. . However, it is assumed that the line-to-line short circuit fault functions as a wired AND or HUB, and T', T2. T',
T' andhi T' g TiC Tweet HT, '4
4 4 4 4
4→T2-+ T"-) T'→T'
-+ T" -+ T'Nol1lj Introduction 4
4 4 4 4
It shall be added to the 4th road.

FIG. 4 shows a circuit diagram using the circuit of FIG. 2 as an example of a specific example of a short-circuit fault that can be detected under test input set T4 by taking the above-mentioned measures. The failure point in the figure is an example of a short circuit between the output lines of the exclusive OR gates 113 and 114. The short circuit fault is wired A
When functioning as an ND, a failure is detected by applying the test force 'r10 of FIG. 3 and observing the output Z2, as shown in the figure.

In the faulty circuit shown in Fig. 4, whether the outputs of the AND gates 121 to 124 all have normal values regardless of which test input from the test input set T4 is applied, or whether an even number of logic Error 11 in the output of the product gate
0 (indicating that the normal value is a logic 1 but has become a logic 0 due to a failure). Output Z.

As is clear from the equation (tl) above, the value of depends on the evenness of the number of inputs with logic 1 among the inputs to the exclusive logic logic group 13, so observation of the output Zt is difficult to detect a fault. was not possible. Logic block 2 is added to enable the detection of a failure that cannot be detected by observing the output ZI for the reason described in F.

The short-circuit fault in the figure could not be detected using the test input set T in the conventional current stage, which uses the AND of the output signals of the exclusive OR gates 111 to 114 as the observation signal. . Further, by adopting the means for facilitating inspection of the present invention, it is possible to detect each O stuck-at fault in the input line to which the signal zl t ZB is externally applied, which was the objective of the conventional means. In general, there is a universal test input set T? for a circuit with nine input variables. S is TA~'rei corresponding to T1 to T7 in FIG. 3, and C=corresponding to 'r:~T'41.
When i/l = V2 = 0, input J*xtv..., only one of the 2 units is O and all others are 1? 11 Test input T notification, T shame, ..., TtL+" construction.

As explained above in detail, the easily testable logic circuit of the present invention is capable of dealing with single-logic stuck-at faults and single shorts between signal lines that occur in the circuit by simple test inputs that can be created regardless of the logic function of the circuit. Failures can also be detected. As a result, high-quality failure horizontal placement can be carried out at low cost, which has great effects.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an easily testable logic circuit according to the present invention, FIG. 2 is a circuit diagram showing a specific example of FIG. 1, and FIG. FIG. 4 is a diagram showing an example of a universal test input set for a manual combinational logic circuit. FIG. FIG. In fig. 1... Combinational logic block, 11... Exclusive OR gate group, 111-114... Exclusive OR gate,
12... AND gate group, 121-124... AND gate, 13... Exclusive logic today gate group, 131
~134...Exclusive logic first gate, 2...Additional logic circuit for inspection, 21-24...Exclusive OR gate, X
・-・Input 1g @% ``I-'' 4...Input signal, C
...Controller input signal, Xc...Exclusive OR gate #
11 output signal group s 'Ih-...Logic constant input s
V2...input for pronunciation, ZI. Z, -...Output signal %D...Failure point, respectively. Figure 2

Claims (1)

[Claims] a first exclusive OR gate group that generates an exclusive OR of each input signal z (C4 = 1 to %) and a control large sword signal C;
Exclusion of the output signal group of the exclusive OR gate group and the AND gate group that generates the AND of the input signal zl~2%, and the output signal group of the AND gate group and the logical constant input y1 In a combinational logic circuit consisting of a second exclusive OR gate group that generates an exclusive OR gate, all of the output signals of the first exclusive OR gate group and the test signal ν are exclusive A logic circuit characterized in that a third group of exclusive OR gates for generating a logical sum is added, and the output signal thereof is used as an observation signal to facilitate failure testing.