JP2684058B2 - CMOS type PLA circuit with failure diagnosis function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a programmable logic allen (hereinafter PL
A circuit), especially domino type CMOS with fault diagnosis function
Type PLA circuit improvement.

[Conventional technology]

The PLA circuit can easily obtain an arbitrary multi-output logic function, and in particular, its structure is regular and can be designed or changed in a short period of time. Widely used for control circuits such as instruction duder in the LSI chip and other applications.

An example of such a PLA circuit is shown in FIG. The PLA circuit is an AND matrix circuit 1 for calculating and outputting a predetermined logical product term signal based on a plurality of logical input signals X ₁ , X ₂ , ..., X _n.
When, an OR matrix circuit 2 for calculating a predetermined logic Kazuko signal based on said logical Risekiko signal, the input signal is input X _1, X _2, ......, the desired product sum format X _n Logical operation,
The logic output signals F ₁ , F ₂ , ..., F _l are output.

By the way, the PLA circuit is provided with transistors at the lattice points of the matrix circuits 1 and 2. The transistors provided at the respective matrix lattice points are connected or not connected so that the AND and OR functions can be realized at desired matrix lattice points.

As described above, in the PLA circuit, each matrix circuit 1 and 2 has a regular configuration, and the user can arbitrarily specify the connection / opening of the transistors provided at the matrix lattice points. It is possible to easily configure a logic circuit that performs a product-sum type logical operation.

By the way, the PLA circuit is manufactured in the same manner as an ordinary IC or LSI, but in the final stage of manufacturing, the AND matrix circuit 1 and the OR matrix circuit 2 are each specially planted with a logical operation function. The structure process is different from that of a normal IC or LSI in that it is formed as a circuit element.

In this way, each PLA circuit has its own logical operation function, and in extreme cases, it is designed and manufactured to have completely different functions. Therefore, the function inspection is performed for different contents. There is a need.

Especially in recent years, with the progress of semiconductor manufacturing technology, IC, LSI
Since the integration density of the
A major problem is how to test the functions of A circuits, especially large-scale PLA circuits.

In other words, in order to perform a complete functional test on a PLA circuit with n input signal lines, it is necessary to test 2 ⁿ input combinations, which requires a great deal of labor and time for the functional test. There is a problem you need.

In particular, if the number n of the input signal lines increases, it becomes practically impossible to perform a function test. For example, if the number of input signal lines is n = 40 and the inspection time for one input is 1 μsec, the functional inspection of the PLA circuit will take about 13 days, so that the functional inspection can be performed easily and reliably. The development and practical application of technology was strongly desired.

Therefore, various PLA circuits with a failure diagnosis function have been developed and put to practical use.

As a function inspection technique for such a PLA circuit, one output signal line for parity check is provided in each of the AND matrix circuit 1 and the OR matrix circuit 2, and the state of the input signal lines of both matrix circuits 1 and 2 is externally determined. It is known to have a configuration that can be controlled from. By using this technique, the logic operation can be simplified, and the function test can be performed by inputting a constant test series signal that does not depend on the logic function from the outside during the test.

This function inspection technique is extremely effective for PLA circuits, and therefore some proposals of PLA circuits adopting such an inspection technique are known. (For example, "Implementi
ng a built−in self−test PLA designs ", IE ³ Design
& Test of Computer PP.37-48, April 1985 nMOS PL
It is about the A circuit. However, the failure that occurs in the PLA circuit is peculiar to the manufacturing technology and circuit configuration of the circuit. Especially, the PLA circuit of the CMOS structure causes a different failure from the PLA circuit of the nMOS structure. However, there is a problem that it is not always possible to perform a highly reliable function test.

For example, in a CMOS circuit, a certain gate input signal causes a so-called stack open failure in which the output of the transistor is in a high impedance state. Two or more inspection patterns are required to reliably detect this failure.

For this reason, the conventional inspection technology remains the same as domino type CMOS.
If this stack open fault is to be inspected with a constant inspection series signal that does not depend on the logic function when applied to a type PLA circuit, it is necessary to perform extremely inefficient inspection, and the inspection series length becomes long. The problem arises.

[Problems to be solved by the invention]

The present invention has been made in view of such a conventional problem, and an object thereof is a CMOS type PLA with a fault diagnosis function capable of easily performing a function check by a constant check series signal that does not depend on a logic function. To provide a circuit.

[Description of the Invention]

(Structure) In order to achieve the above object, the present invention uses a plurality of signal input lines to which a logic signal is input, a clock input line to which an AND array control clock φ ₁ is input, and the AND array control clock φ ₁ . Each of the transistors for precharging and discharging the product term line, a plurality of bit lines and the product term line are matrix-connected via the transistor at the lattice point, and the logical sum of a plurality of logical input signals is calculated. An AND matrix circuit including an AND matrix section that outputs a logical product term signal, a clock input line to which an OR array control clock φ ₂ is input, and precharging and discharging of a product term line using the OR array control clock φ ₂ Each transistor to do, multiple product term lines and sum term lines, through the transistor at that lattice point It is Trix connection, the AND
In a CMOS type PLA circuit having an OR matrix circuit for calculating the NOR of the logical product term signals output from the matrix section and outputting as a logical sum signal, a positive input bit line or a logic input signal independent of the logical input signal A diagnostic input control circuit for setting the complementary input bit line to a predetermined level, a diagnostic input product term line control circuit for setting a predetermined product term line to a predetermined level, and all bit lines and their lattice points via transistors. And a second additional product term line provided in the AND matrix section so that the number of grid points not connected to the product term line via the transistor is odd on each bit line. An additional product term line, and on each of the product term lines, an additional sum term line provided in the OR matrix circuit so that the number of grid points connected via the product term line and the transistor is odd, And a parity generation circuit for calculating and outputting a parity signal of a sum line for which the force signal has a predetermined level, and using the bit line input control circuit to set either or both bit lines to a predetermined level to a predetermined level, Apply test sequence independent of logic function to input line and product term line control line,
At this time, a fault diagnosis circuit for diagnosing a fault by monitoring the parity signal output from the parity generation circuit is provided.

(Operation) When the failure diagnosis of the PLA circuit of the present invention is performed, the bit line input control circuit is used to set either of the complementary bit lines to the "0" level independently of the logic input signal. Here, in order to simplify the explanation, it is assumed that the auxiliary input bit line is set to "0" level regardless of the input signal.

In this state, for example, if all the plurality of input logic input signals are set to the "1" level, all the signals input to each bit line of the AND matrix section become the "0" level.

In the present invention, the first additional product term line is connected to all the bit lines of this AND matrix section at their lattice points via transistors. Therefore, by monitoring this first additional product term, when at least one of the bit lines becomes the "1" level, this can be detected reliably.

Further, in the present invention, this second additional product term line is used so that the number of unconnected grid points on each bit line of the AND matrix section is set to be an odd number. Therefore, when only one bit line of the AND matrix section shows the "1" level due to a failure or the like, the odd number of product term lines always show the "1" level.

Further, in the present invention, an additional sum product is provided in the OR matrix circuit, and the number of grid points connected to the sum line on each product line is set to be an odd number. Therefore, 1
When only the product term lines of the books indicate the "1" level, the odd-numbered sum term products always indicate the "0" level.

In particular, in the present invention, since the bit line and the product term line can be controlled independently, if the parity signal of the sum term product whose output signal is at "0" level is calculated, the AND matrix circuit based on this parity signal, The failure diagnosis of the OR matrix circuit can be performed efficiently.

That is, a constant check sequence that does not depend on a logical function is input to each signal input line and product term line control line of the AND matrix circuit, and at this time, the parity signal output from the parity generation circuit provided in the OR matrix circuit is observed. Only by doing so, it is possible to efficiently diagnose the failure that occurs in each part of the circuit.

In particular, the inspection sequence required for this inspection can be a regular sequence that does not depend on the logic function of the PLA circuit.
The test sequence generator that supplies the test sequence to each signal input line and each product term control line of the AND matrix circuit, and the response output determination device that is provided at the output stage of the OR matrix circuit for fault diagnosis have a relatively simple circuit configuration. You can
It is possible to diagnose the PLA circuit failure with a simple circuit.

(Effects of the Invention) As described above, according to the present invention, a regular check sequence that does not depend on a logic function is used to control each signal input line of the diagnostic input control circuit and each product term control of the diagnostic input product term line control circuit. Input to the line, and at this time, by performing a parity check on the number of sum-term lines that output a signal of a predetermined level from the OR matrix circuit, each part of the circuit, especially the AND matrix circuit, O
Diagnosis of failures that occur in the R matrix circuit can be performed efficiently with a simple circuit.

Particularly, according to the present invention, a second additional product term line and an additional sum term product are provided, and in the AND matrix circuit, the grid points having no connection on each bit line are set to be odd, and OR
In the matrix circuit, the number of lattice points having product term line connections is set to be an odd number. Therefore, the fault diagnosis occurring in the PLA circuit can be quickly and reliably performed only by observing the parity signal output by the parity generation circuit.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings. In addition,
The parts corresponding to those of the circuit shown in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted.

FIG. 1 shows a CMOS PLA with a failure diagnosis function according to this embodiment.
A preferred example of the circuit is described. In order to facilitate the understanding of the present embodiment, FIG. 2 shows a circuit configuration in which the circuit portion used for the failure diagnosis is removed from the circuit shown in FIG. Show.

The PLA circuit of the embodiment according to the present invention includes an AND matrix circuit 1 that outputs a plurality of predetermined logical product term signals based on a plurality of theoretical input signals X ₁ , X ₂ , and X ₃ , and an operated logical product term. The AND matrix circuit 1 and the OR matrix circuit 2 have a NOR gate configuration, including an OR matrix circuit 2 that calculates a logical sum signal based on the signal and outputs the logical sum signal as a logical output signal.

(A) AND Matrix Circuit The AND matrix circuit 1 is formed centering on an AND matrix section 3 described later, receives a control clock φ ₁ via a control clock input line 4, and has a plurality of signal input lines 5 Logic inputs X ₁ , X via (5a, 5b, 5c)
₂ , X ₃ is supplied.

Then, the logic input signals X ₁ , X ₂ , X ₃ supplied via these respective signal input lines 5 are input to the AND matrix section 3 via the corresponding inverter 6 and further via the inverter 6a. .

The AND matrix section 3 connects a plurality of bit lines 8 to which each input signal is input and a plurality of product term lines 9 in a matrix connection, and connects a plurality of transistors 10 on the matrix to the product term line 9. The matrix lattice points and the matrix lattice points which do not connect the transistor 10 to the product term line 9 are arranged.

The transistor 10 connected to the same product term line 9
Is configured to act as a NOR gate.

Then, the transistor 10 connected to the product term line 9
The other end of is connected to the ground side through the gate 11.
Further, each product term line 9 has its upper end connected to the power supply line via the gate 12 and the other end input to the OR matrix circuit 2. Since the transistor 10 functions as a NOR gate, "1" is applied to any one of the bit lines 8 connected to the product term line 9 through the transistor 10.
When a level logic signal is input, a "0" level signal is generated on the product term line 9.

Therefore, a desired logical operation function can be obtained by arranging the transistor 10 in the AND matrix section 3.

(B) OR matrix circuit The OR matrix circuit 2 is an OR matrix unit.
Control clock input line 14
The control clock φ ₂ is input via the AND circuit, and the logical product term signal generated by the AND matrix circuit 1 is directly supplied as an input signal.

The logical operation output of the OR matrix unit 13 is an inverter
It is output as logic outputs F _{1 to} F ₃ via 15.

In the embodiment, the OR matrix section 13 has a plurality of OR array product term lines 17 having one end connected to the AND array product term line 9 and the other end connected to the product term line control circuit 25 side described later.
And a plurality of sum line 19 connected to the gate 18 at one end and to the corresponding inverter 15 at the other end, and these product term lines 17 and sum term lines 19 are arranged in a matrix. . The PLA circuit of the embodiment is normally used in a state where a signal of "0" level is applied to the gate input of the product term line control gate 25a in the diagnostic input product term line control circuit 25.

A plurality of transistors 20 are also provided at the lattice points of these matrices, and the product term line 17 and the sum term line 19 are connected to each other. The other end of the transistor 20 is connected to the ground side via the gate 16. The transistor 20 connected to the same sum line 19 is formed so as to function as a NOR gate similarly to the transistor 10 provided in the AND matrix section 3.

Therefore, by arranging the transistor 20 at each matrix lattice point of the OR matrix section 13, the OR matrix section 13 can be formed to perform a predetermined logical operation.

Therefore, in manufacturing this PLA circuit, the transistors 10 and 20 are formed in all the matrix lattice points of the AND matrix portion 3 and the OR matrix portion 13, and at the final stage of the production, the transistors 10 of these respective lattice points are formed.
The PLA circuit can be formed as a circuit for performing a predetermined logical operation by assembling the logical function depending on whether 20 is connected or not.

By the way, when the PLA circuit of this embodiment is used as an ordinary logical operation circuit, as shown in FIG.
A "0" level signal is input to both inputs of the gates 7a and 7b to operate as an inverter, and a product term line control gate of a diagnostic input product term line control circuit 25 of the OR matrix section 13 described later.
A signal of "0" level may be biased to 25a.

In this way, predetermined logical operation processing is performed based on the logical input signals X ₁ , X ₂ , X ₃ input from the signal input line 5, and the logical output signals F ₁ , F ₂ , F ₃ from the output line 21. Can be calculated and output.

(C) Fault Diagnosis Circuit By the way, when such a PLA circuit is supplied to, for example, an IC or an LSI chip, it is necessary to perform a fault diagnosis inspection in order to improve the reliability of the circuit itself.

Therefore, the PLA circuit is integrally formed with a failure diagnosis circuit, and after the PLA circuit is manufactured, the failure diagnosis circuit is used for failure diagnosis to improve the reliability of quality.

A feature of the failure diagnosis circuit according to the present embodiment is that a test series signal that does not depend on a logic function is applied to the PLA circuit, and the failure diagnosis of the PLA circuit is performed quickly and reliably.

Therefore, the failure diagnosis circuit of the present embodiment uses the diagnostic input control circuit 22, the additional product term line circuit 23, the additional sum term line 24, the diagnostic input product term line control circuit 25 and the parity generation circuit 26. It is configured.

Diagnostic Input Control Circuit The diagnostic input control circuit 22 includes a first control signal line.
27, second control signal line 28 and each input signal line
D ₁ , D ₂ , D ₃ , ₁ , ₂ , ₃ are connected. The input control circuit 22 is provided with the first and second control signal lines 2
Based on the first control signal C ₁ and the second control signal C ₂ input via 7, 28, the NOR gate 7 is independent of the theoretical input signal.
Complementary input control NOR gate 7a and positive input control NOR gate 7b
Are formed so that the output of can be independently set to the "0" level.

In the embodiment, this diagnostic input control circuit 22 uses the input NO
It is formed using the R gate 7. The control signal C ₁ These NOR gates 7a, 7b and the first and second input of, C ₂
The logic input signal is controlled based on

Therefore, if, for example, a signal of C ₁ = 1 is input to the first control signal line 27, the output of the complementary input control NOR gate 7a to which the logical input signals ₁ , ₂ , 3 are input can be set to the "0" level. Further, if a control signal of C ₂ = 1 is input from the second control signal line 28, the output of the positive input control NOR gate 7b to which the logic input signals D ₁ , D ₂ and D ₃ are input becomes "0" level. can do.

As a result, the first signal input from the control signal lines 27 and 28
Of the control signal C ₁ , the second control signal C ₂ and the logic input signals X ₁ , X ₂ , X ₃ input from the signal input line 5,
Select a predetermined bit line 8 in the AND matrix section 3,
It is possible to supply a logic signal of "1" level only to the selected bit line and supply a logic signal of "0" level to all the remaining bit lines 8.

For example, (C ₁ , C ₂ ) = (1,0), (X ₁ , X ₂ , X ₃ ) = (1,0,
If the signal of 1) is input, (B ₁ , ₁ , B ₂ , etc.) is input to each bit line 8 of the AND matrix section via the 2-input NOR gates 7a, 7b.
₂ , B ₃ , ₃ ) = (0,0,1,0,0,0) signal is supplied and B ₂
The bit line corresponding to the signal can be selected.

Additional Product Term Line Circuit The additional product term line circuit 23 is formed using a first additional product term line 29 and a second additional product term line 30.

The first additional product term line 29 is connected to each bit line 8 at every lattice point through the transistor 10 in the AND matrix section 3. Therefore, if at least one bit line 8 of the AND matrix section 3 is at "1" level, the logic signal of the first additional product term line 29 becomes "0" level.

Therefore, as described above, the bit line input control circuit 22 is used to select the bit lines 8 of the AND matrix section 3 one by one, and the signal level of the first additional product term line 29 is output from the parity generation circuit. By observing based on the signal Z,
For example, stuck-at faults of the bit line 8 and faults equivalent to these can be inspected.

The second additional product term line 30 is provided as a parity product term line for inspecting an intersection fault of the AND matrix section 3, and is a product term line on each bit line 8 for input. It is formed so that the number of grid points without connection is odd.

That is, B _{1 in the} state without this second additional product term line 30
In the bit line 8 of, two (even) grid points are not connected to the product term line.

Therefore, in order to make the grid point on this bit line 8 an odd number which is not connected to the product term line, the grid point between this bit line 8 and the second additional product term line 30 is opened, that is, A grid point with no connection may be used.

Looking at the B ₂ bit line 8, there are 3 grid points without connections.
Since the number is an odd number, the lattice points of the bit line 8 and the second additional product term line 30 are connected by the transistor 10.

In this way, using the second addition product term line 30, B ₁ ,
The number of grid points not connected to the product term line of each bit line 8 of ₁ , ..., B ₃ , ₃ is set to be an odd number.

Therefore, as described above, the bit line input control circuit 22 is used to select the bit lines 8 one by one, and the number of product term lines 9 at which the signal becomes the "1" level is counted by the output signal Z of the parity generation circuit. By doing so, the intersection fault of each lattice point in the AND matrix unit 3 and the fault equivalent to this can be inspected.

Additional sum term line The additional sum term line 24 is a parity sum term line provided in the OR matrix unit 13, and on each product term line 17, 31, 32, a grid connected to the sum term line. It is formed so that each of the points has an odd number.

For example, looking at the product term line 17 of P ₅ , this product term line 17 is F ₁
Since the summation product 19 is connected to the summation product 19 via the transistor 20 at one of the lattice points (one lattice point is connected), the lattice point with the additional summation line 19 is set to open.

Further, since the product term line 17 of P ₄ is connected to each sum term line 19 of F ₂ and F ₃ via the transistor 20 at its lattice point (two lattice points are connected), the location of the connection point is In order to make it an odd number, it is connected to the lattice point of the additional sum term line 19 through the transistor 20.

In this way, in the OR matrix unit 13, the product term lines 17, 31, and 32 are connected to the odd-numbered additional sum term lines and the lattice points thereof via the transistor 20.

Therefore, if the product term lines 17, 31 and 32 are selected one by one and the number of the sum term lines 19 and 24 at which the signal becomes the “0” level is counted, the product term lines in this OR matrix circuit 2 are counted.
17, it is possible to inspect the sum line 19 for stuck-at faults, intersection faults at each lattice point of the OR matrix section 13 and faults equivalent to these.

Diagnostic Input Product Term Line Control Circuit The diagnostic input product term line control circuit 25, under the control of the diagnostic input control circuit 22, sets the product term lines other than the predetermined product term line obtained from the bit line to be diagnosed to “0”. This is a circuit for controlling the level, and the circuit 25 inputs a drain to each product term line, a source to ground, and a signal from a gate.
It consists of FETS ₁ , S ₂ , S ₃ , S ₄ , S ₅ , and S ₆ .

Then, a predetermined signal is input in synchronization with the bit line of the diagnostic input control circuit 22.

Parity Generating Circuit The parity generating circuit 26 is formed so as to arithmetically output a parity signal Z indicating whether the number of sum line 19 for which the output signal is at “0” level is even or odd, and in the embodiment, The outputs of the signals F _{1 to} F ₄ of all the logic output lines 21 (21a, 21b, 21c, 21d) connected to the inverter 15 side are formed so as to output the exclusive OR circuit (EXOR) to the Z terminal. ing.

As a result, the parity generation circuit 26 outputs a "1" level signal when the number of logic output lines 21 that output a "1" level signal is odd, and outputs a "0" level signal when the number is even. Becomes

In the present embodiment, regarding the positional relationship between each signal line that has been conventionally used and each signal line provided for failure diagnosis, the first additional product term needs to be arranged at the right end of the AND matrix section 3. Although the other positional relationships are not limited to those shown in the figure, the ground line connected to the ground gate 11 and the left side of the AND matrix section 3 have the first additional product term line 29 with the AND matrix. It needs to be placed on the right side of the part 3.

Further, the ground lines connected to the ground gates 16, 16 of the OR matrix section 13 need to be gathered on both upper and lower sides. With this configuration, the earth line open failure, which was conventionally impossible to detect, does not become a failure.

(Operation) Next, an example of the failure diagnosis operation of the CMOS PLA circuit of this embodiment will be described.

When performing fault diagnosis using the circuit of the present embodiment, the following inspection series is applied to each input line 5, 27, 28 of the diagnostic input control circuit 22 and the control line 25b of the diagnostic input product term line control circuit 25. Input the signal.

_{I = (X 1, X 2} , X 3, C 1, C 2, S 1, S 2, S 3, S 4, S 5, S 6) In Example, I ₁ ² as such test sequence = (1,1,1,1,0,0,1,1,1,1,1) is applied to each input line 5,27,28 and product term control line 25b, and the case where the fault diagnosis is performed is assumed. To do.

(A) First, consider the case where there is no failure in the PLA circuit. In this case, the logic input signals (X ₁ , X ₂ , X ₃ ) forming a part of the check sequence I are set to (1, 1, 1) as described above. Therefore, the auxiliary input control NOR gate 7 is supplied from the signal input line 5 via the inverter 6.
The signals ₁ , ₂ , ₃ input to a are (0,0,0), and the signals D ₁ , D ₂ , D ₃ input to the positive input control NOR gate 7b via the inverter 6a are ( It becomes 1,1,1).

Further, the first control signal C ₁ forming a part of the test sequence signal I is set to “1”, and the second control signal C ₂ is set to “0”. Therefore, the complementary input control NOR gate 7a sets all the complementary input bit lines to the "0" level, and the logical signals D ₁ and D
Only the values of ₂ and D ₃ (D ₁ = 1, D ₂ = 1 and D ₃ = 1) are inverted and B ₁ , B ₂ ,
It is output to each bit line 8 of B ₃ , and all the bit lines 8 become “0”.

As described above, when the test sequence I ₁ ² is applied to each input line when there is no failure in the PLA circuit, all the bit lines of the AND matrix section 3 become “0” and are applied to the product term line control gate 25b. Product term line control signal (S ₁ , S ₂ , ..., S ₆ )
= (0,1, ..., 1) sets the product term line except P ₁ to the “0” level.

Therefore, each product term line of the OR matrix circuit 2 is (P ₁ , P
₂ , ......, P ₆ ) ＝ (1,0, ……, 0), so the sum term line of W ₄ connected via the product term line 17 of P ₁ and transistor 20 is added. only Kazukosen 24 becomes a value of "0", other W _1, W _2, W ₃ of the sum term line 19 takes a value of "1". Then, the outputs of the summation lines 19 and 24 of these W _{1 to} W ₄ are the inverter 15
Is supplied to the output line 21 of F _{1 to} F ₄ via (F ₁ , F ₂ ,
Since F ₃ , F ₄ ) = (0,0,0,1), the parity generation circuit 26
Will output a parity signal of Z = 1.

In this way, according to the present embodiment, when the check sequence I ₁ ² is input, if there is no fault in the PLA circuit, the parity generation circuit 26 outputs a parity signal of “1”. Determines that there is no failure in the PLA circuit.

(B) Next, consider a case where some failure occurs in this PLA circuit, for example, the bit line 8 of B ₁ of the AND matrix section 3 is degenerated to "1".

In this case, it is applied to the test sequence I ₁ ² to each input line, each bit line of the AND matrix unit 3 does not become all "0", only the bit line 8 of the B ₁ is "1" Take a signal.

Thus the bit line 8 of the B ₁ is take values B ₁ = 1, the value of the first additional product term lines 29 connected through the bit lines and the transistor 10 is P ₁ = "0" , This results in this
All values of the product term lines 9,29,30 constituting the AND matrix unit 3 _{(P 1, P 2, ......} , P 6) = (0,0, ......, 0) and becomes. Then, the value of each of these product term lines is directly transmitted to each of the product term lines 17, 31, 32 of the OR matrix circuit 2.

When all the OR array product term lines become “0” in this way, all the sum term lines forming this OR matrix section 13,
That is, the summation lines 19 and 24 of W ₁ , W ₂ , W ₃ and W ₄ are all “1”, and this value is output to the output signal line 21 via the inverter 15 (F ₁ , F ₂ , F ₃ , F ₄ ) = (0,0,0,0) signal is output.

Therefore, the parity signal calculated by the parity generation circuit 26 becomes Z = 0, which makes it possible to detect that a failure has occurred.

In this way, the PLA circuit of the present embodiment provides the signal input line 5, the first and second control signal lines 27, 28 and the product term line control line 25b with I ₁ ² = (X ₁ , X ₂ , X ₃ , C ₁ , C ₂ , S ₁ , S ₂ , S ₃ , S ₄ , S ₅ , S ₆ ) = (1,1,1,1,0,0,1,1,1,1,1) inspection A series signal is applied, and at this time, the parity generation circuit 26
The fault diagnosis occurring inside the PLA circuit can be performed only by monitoring the value of the parity signal Z generated from the.

In particular, according to this embodiment, the fault diagnosis can be performed using the inspection series I that does not depend on the logical functions of the AND matrix circuit 1 and the OR matrix circuit 2.
Various kinds of failures that occur inside the circuit can be detected quickly and reliably, and in particular, the reliability of the large-scale PLA circuit can be made extremely high.

FIG. 3 shows a specific example of the inspection series I used for diagnosing the failure of the CMOS PLA circuit of this embodiment. In FIG. 3, the output parity expectation value Z indicates that a failure occurs in the circuit. This is a parity bit obtained when it does not exist. For example, in the check sequences I ⁴ and I ⁵ , the cumulative value of the output parity bits from J = 1 to m is 1.

By adding such a check series to the CMOS type LA circuit, the output parity bits in the check series I ² and I ³ ,
Further, in the inspection series I ⁴ and I ⁵ , by comparing the cumulative output parity with the expected value, a single physical failure (dissolution of note, short circuit between lines) or the like can be detected with certainty.

As described above, according to this embodiment, the PLA circuit is
When it is formed as C or LSI, the diagnostic input control circuit 22, the additional product term line circuit 23, the additional sum term line 24, the diagnostic input product term line control circuit 25, and the parity generation circuit 26 shown in FIG. By incorporating the above into the original circuit of the PLA and forming the circuit, the failure diagnosis of the manufactured PLA circuit can be performed quickly and reliably.

After the diagnosis is completed, the product term line control line 25b
Is applied to (S ₃ , S ₄ , S ₅ , S ₆ ) = (0,0,0,0), and (C ₁ , C ₂ ) = to the first and second control lines 27 and 28. (0,
The control signal of 0) may be applied. In this way, after the failure diagnosis is completed, the PLA circuit is used as a normal circuit as shown in FIG. 2 and its logic input signals X ₁ , X ₂ ,
It is possible to perform a logical operation on X _{3 based} on the set logical function and output logical output signals F ₁ , F ₂ , and F ₃ .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a preferred embodiment of a CMOS type PLA circuit with a failure diagnosis function according to the present invention, and FIG. 2 is a circuit diagram showing FIG.
Equivalent circuit diagram when used as A circuit, Fig. 3 shows the first
FIG. 4 is an explanatory diagram of a signal sequence used when diagnosing a failure of the PLA circuit shown in FIG. 4, and FIG. 4 is a block diagram showing a configuration of a general PLA circuit. 1 …… AND matrix circuit 2 …… OR matrix circuit 3 …… AND matrix section 4 …… Control clock input line φ ₁ 5 …… Signal input line, 6 …… Inverter 7 …… Input NOR gate, 8 …… Bit line 9 …… Product term line, 10 …… Transistor 13 …… OR matrix section 14 …… Control clock input line φ ₂ 15 …… Inverter, 17 …… Product term line 18 …… Gate, 19 …… Japanese term line 20… … Transistor, 21 …… Output line 22 …… Diagnostic input control circuit 23 …… Additional product term line circuit 24 …… Additional sum term line 25 …… Diagnostic input product term line control circuit 26 …… Parity generation circuit 27,28… ... Control line 29 ... first additional product term line 30 ... second additional product term line

Claims (1)

(57) [Claims] 1. Precharge and discharge of a product term line using a plurality of signal input lines to which a logic signal is input, a clock input line to which an AND array control clock φ ₁ is input, and the AND array control clock φ _1. An AND matrix unit that performs each transistor, a plurality of bit lines, and a product term line for performing a matrix connection via a transistor at its lattice point, calculates the NOR of a plurality of logical input signals, and outputs a logical product term signal. And an AND matrix circuit including an OR array control clock φ ₂ , each transistor for precharging and discharging the product term line using the OR array control clock φ ₂ , and a plurality of product terms Lines and sum lines are matrix-connected through transistors at their lattice points, and the AND matrix In a CMOS PLA circuit having an OR matrix circuit for calculating the NOR of the logical product term signals output from the lix section and outputting as a logical sum term signal, a positive input bit line independent of the logical input signal Alternatively, a diagnostic input control circuit for setting a complementary input bit line to a predetermined level, a diagnostic input product term line control circuit for setting a predetermined product term line to a predetermined level, and transistors for all bit lines and their lattice points A first additional product term line connected through the bit line and each of the bit lines such that the number of lattice points not connected to the product term line through the transistor is odd.
The second additional product term line provided in the AND matrix section and the OR matrix circuit provided so that the number of grid points connected to the product term line via the transistors is odd on each of the product term lines. And a parity generation circuit that outputs the parity signal of the summation line whose output signal is at a predetermined level. Using the bitline input control circuit, either positive or complementary, or both The bit line is set to a predetermined level, and a test sequence that does not depend on a logic function is applied to the signal input line and product term line control line,
At this time, the CMOS PLA circuit with a failure diagnosis function is provided with a failure diagnosis circuit that performs a failure diagnosis by monitoring the parity signal output from the parity generation circuit.