JPS5928727A - Programmable logic array - Google Patents

Abstract

PURPOSE:To miniaturize a large-scale integrated circuit, by writing program information sent from an ROM incorporated in a semiconductor chip or an external memory so as to execute the test of a PLA and the switching of redundancy and to reduce external connecting points and the degree of integration at the rise of a system. CONSTITUTION:A rewritable cross point cell 4 is provided to cross points between input lines 1a-1f and product term lines 2a-2e and between the lines 2a-2e and output lines 3a-3c, binary information is written in the cells 4 and the programming of logical function is performed with AND and OR arrays 24 and 25. The arrays 24, 25 are sectioned respectively into a basic block and a redundancy block with respect to the lines 1a-1f, 2a-2e, and 3a-3c, and test information is generated from an input line check circuit 10 in addition to the program of logical function and written in the cells 4. Further, a program term line checking circuit 11, an output line switching circuit 12, a word line/selecting line switching circuit 13, a bit line switching circuit 4, and an input line switching circuit 9 and the like are provided to execute the test of PLA and the switching of redundancy, thereby miniaturizing the large-scale integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to defect tolerant programmable logic arrays.

BACKGROUND OF THE INVENTION Logic devices that perform logical operations in information processing systems and the like are composed of circuits that combine a large number of logic gates having logic functions such as NAND and NOR. Today, with advances in microfabrication techniques for integrated circuits, the number of logic gates that can be integrated on a single semiconductor chip has increased dramatically. It has also become possible to collect them all at once. The reason behind this progress in increasing the scale of integrated circuits is that not only can the manufacturing cost of semiconductor chips per logic gate be reduced, but also the number of interconnections between semiconductor chips can be significantly reduced by batch integration, which makes it easier to implement. The aim is to make the system more economical through simplification and downsizing of the device.

Incidentally, the scale of circuits that can be integrated on one semiconductor chip is determined by the dimensions of the circuit elements and the area of the chip. Among these, the circuit element dimensions depend on the level of microfabrication technology based on improvements in manufacturing methods and manufacturing equipment, and therefore cannot be miniaturized beyond the currently established level.

However, if the chip area is large, there is a high probability that it will contain defects that occur during manufacturing, and the limit for economical manufacturing is a few square inches. Therefore, in large-scale systems/systems, the circuits that make up the logic device must be divided and integrated into multiple semiconductor chips, which not only makes it impossible to significantly reduce the number of interconnections, but also makes it difficult to manufacture multiple types of semiconductor chips. There was a cost problem.

As a conventional technique for eliminating such chip area limitations and enabling large-scale integration, a method for dealing with defects by adding a redundant portion to a memory circuit is known, for example, in Japanese Patent Laid-Open No. 52-31624. In the case of memory circuits, the circuit configuration has repeatability, and the fact that redundant switching can be performed by dividing the cell array into small-scale units facilitates large-scale integration by expanding the chip area. However, in the case of the circuit constituting the logic device 4, especially in the case of a combinational circuit called wired logic, the circuit configuration has poor repeatability, so it is difficult to perform redundant switching efficiently.

In other words, if a circuit is divided into multiple blocks and a redundant configuration such as multiplexing is applied to each block, increasing the circuit size of the block increases the probability that it will contain defects, and conversely, decreasing the circuit size increases the probability that the circuit will contain defects. The scale of redundant switching circuits increases, and the probability that these circuits contain defects increases.

Furthermore, since the circuit functions and configurations differ for each divided block, it is not easy to test whether or not a block contains a defect.

Today, as a way to solve the problems associated with the randomness of the circuits that make up such logic devices, programmable logic plays (hereinafter referred to as PLA), which have repeatable circuit configurations, are being used instead of conventional combinational circuits based on wired logic. The trend toward configuring logical devices with (called) is becoming popular. A basic PLA consists of an ANl array in which a plurality of input lines intersect with a product term line, and an OJ'L array in which these product term lines intersect with a plurality of output lines. By selectively activating the intersections of , it is possible to realize logical functions developed in the sum-of-products form.

In PLA, the operation of selectively activating the intersection points of the array is called programming.
LA is divided into mask writing type and field writing type. The mask writing type is a PLA in which programming is performed during the manufacturing process, for example, by selectively forming through holes. Therefore, book P
In LA, programming methods cannot be changed at the product stage. On the other hand, the field write type is PLA, which allows programming at the product stage, and can be further divided into fixed write type, semi-fixed write type, and rewritable type. Among these, the fixed write type uses a dedicated write device to perform fixed programming by destroying the PN junction of the programmable read-only memory cell provided at the intersection of the array, blowing out the fuse, etc. It is A. Therefore, once programmed, the present P T,,A-'c cannot be changed in the way it is programmed, except by adding to unused portions of the array. In contrast, the semi-fixed type has read-only memory cells located at the intersections of the array that are both programmable and erasable, making it possible to program multiple times.
It is L.A. However, this PLA requires a dedicated writing device in steps 1 to 1 for programming, and programming cannot be performed while it is embedded in a logic device. On the other hand, the rewritable type has a non-rewritable memory cell such as a flip-flop circuit at the intersection of the array, and programming is performed by writing binary information to this memory cell while it is assembled in a logic device. P L
It is A.

Therefore, in this PLA, it is possible to dynamically change the logic function by incorporating programming operations into the logic operation routine of the information processing system including the logic device.

In the PLA described above, as a conventional technique for allowing the existence of defects and performing normal logic functions, there is a known method in which a preliminary product term line is provided in advance in a field writing type PLA. . This method is applied to permanently replace a defective product term line with a spare product term line after the manufacturing process is completed. The reason for providing a reserve for the product term line is that the product term line is involved in both the AND array and the OR array, and can deal with defects at the intersection of both arrays, and the programming state is such that the product term line is replaced as a unit. Even if it is, it does not affect the logical function of the sum-of-products form. However, conventional methods cannot deal with cases where defects at intersections extend to input and output lines, or defects in the input and output lines themselves, and even cannot deal with defects that occur after the start of operation. . Another conventional technique that has been used in rewritable PLA is a method in which spares are provided for the product term line and the output line, and defects are detected and replaced with the spares after the start of operation, as disclosed in Japanese Patent Application Laid-Open No. 56-1999. 16943]. However, even with this method, it is not possible to deal with cases where a defect at an intersection extends to the input line or a defect in the input line itself.

In other words, the method according to the above-mentioned conventional technology is intended to deal with small-scale defects in limited locations of PT and A after the manufacturing process is completed or after the start of operation, and is limited to one semiconductor chip per semiconductor chip. This is based on the assumption that semiconductor chips that include multiple PLAs and have defects that cannot be treated will not be used as defective products. Therefore, P.L.
A large number of P.L.A.
A new invention was required to integrate these on the same semiconductor chip.

Purpose of the Invention The present invention provides a PLA that has a high defect remediation ability and enables automatic defect detection and repair during operation, and enables high-yield production of large-scale semiconductor chips in which logic device circuits are collectively integrated. The aim is to make the 7-system economical by simplifying the implementation and downsizing.

To achieve the above object, the present invention provides a rewritable form P
Divide L A into basic blocks and redundant blocks regarding input lines, product term lines, and output lines, and use the fact that it is rewritable to easily detect defects and switch to redundancy.
It is characterized by allowing the existence of defects over almost the entire surface of the LA.

DESCRIPTION OF EMBODIMENTS FIG. 1 shows a rewritable PL which is an embodiment of the present invention.
FIG. 2 is a block configuration diagram of A. In FIG. 1, lα to 11 are input lines, 2a to 2e are product term lines, and 3a to 3C are output lines. A block 4 provided corresponding to the intersection of each input line and the product term line and the product term line and the output line is an intersection cell consisting of a rewritable memory cell and a logic gate. Logic provided on the input side of the input line and the output side of the output line (numerical block 5 is an inverter. Block 6 connected to the product term line and output line is a pull-up circuit. Of the wirings, 7a to 7t are word lines, 8
8e from σ is a pit line.

Among the other blocks, 9 is an input line switching circuit, 10 is an input line inspection circuit, 11 is a product term line inspection circuit, 2 output line switching circuits, 13 is a word line selection and segmentation circuit, and 14 is a focus line switching circuit. It is. Among the wirings connecting these blocks, 15a to 1, 50 are input line switching information lines,
16a to 1.6d are bit line switching information lines, 17a to 171 are word line switching information lines, 18 is a product term line inspection information line, and 19 is an output line inspection information line. Also, 20d from 20σ is an input terminal, 21a and 21b are output terminals, and 22a
22d from programming terminal, 23 is source selection potential VD
This is the power supply terminal of D.

In the configuration of FIG. 1 described above, the portion 24 related to the intersection of the input line and the product term line is an AND array, and the portion 25 related to the intersection of the product term line and the output line is an OR array.

Next, the redundant configuration of this PLA will be explained. FIG. 2 is a conceptual diagram showing how to classify input lines and output lines in the PLA of this embodiment. In FIG. 2, only the basic parts of the configuration shown in FIG. 1 are shown, and the others are omitted. Note that the intersection points and intersection cells are conceptually indicated by circles. PL A of this example has 6 input lines indicated by 1a to 1f, 5 product term lines indicated by 2Q to 2e, and 8
There are three output lines from α to 3c. Therefore, the number of intersections of the ANr) array denoted by 24 is 30, 2
There are 15 intersections of the OR array shown by 5. A N ]
) array 24 has 2(i(Z 26
．． ? It is divided into eight blocks shown by . Each block includes two input lines, an inverter 5 belonging thereto, and an intersection cell. 26a and 2f35 are basic blocks related to input lines, and 26c is a redundant block related to input lines. On the other hand, the OR array 25 is divided into three blocks 27a to 270 with respect to the output lines. Each block includes one output line, a pull-up circuit 6 imitating it, an intersection cell, and an inverter 5. 27.2 and 27h are basic blocks related to output lines, and 27c is a redundant block related to output lines.

FIG. 8 is a conceptual diagram showing how to divide product term lines in the PLA of this embodiment. Note that this figure supplements the method of classification regarding the product term line, which is not shown in FIG. As shown in the figure, an AND array 24 and an OR array 25
is divided into five blocks indicated by 28α to 28e with respect to the product term line. Each block includes one product term line, a pull-up circuit 6 belonging thereto, and an intersection cell. 28f2 to 28d are four basic blocks related to the product term line, and 28e is a redundant block related to the product term 1 line.

Next, the function and configuration of each block in the PLA of this embodiment shown in FIG. 1 will be explained.

FIG. 4 is a diagram in which a portion of the AND array and the OR array are extracted, and shows the logical function of the PLA in this embodiment. In this example, PT, A is n channel E
/D Consists of MO8 circuits.

Therefore, in this figure, some parts are shown using transistors. Portions 4 and 6 surrounded by broken lines in the figure are an intersection cell and a pull-up circuit, respectively. 29 in the intersection cell 4 is a rewritable memory cell, 30a and J: Hiao, s
is an enhancement type MO8) transistor. 81 in the pull-up circuit 6 is a depletion type MOS transistor. In this PLA, AND array 24 and OR,
The array 25 is constructed such that the intersection cells and the pull amplifier circuit 6 form a NOR circuit. Therefore, AND array 24. Then input 11111j of input line l
The inverter 5 is provided on the output side of the output line 3 to perform an AND function, and the inverter 5 is provided on the output side of the output line 3 to perform an OR function in the twisted OR array 25.

In each intersection cell of the AND array 24 and the 0 array 25, the transistor 3ob can be made conductive by writing the information "■" into the rewritable memory cell 29, and the transistor 3ob can be made conductive by writing the information "o゛". Since the transistors 3ob and 30a are connected in series, this intersection cell 4 can be activated by writing "1" into the rewritable memory cell 29.
It can be made inactive by writing □++. The information in the rewritable memory cell 29 is “1” or “0”
Writing is performed using word line 7 and bit line 8. That is, when the word line 7 is set to the "11" state, which is the same as the power supply potential VDD, the rewritable memory cell 29 connected thereto is selected, and when it is set to the rLJ state, which is the same as the ground potential, it becomes unselected. In the selected rewritable memory cell 29, the bit line 8 connected to it is set to "I".
In the case of the ('' state, information 1'' is written, and in the case of the "r," state, the information 0'' is written.

In the non-selected state, information that has already been written is retained.

5 to 10 are logical configuration diagrams of blocks 9 to 14 in FIG. 1. FIG. 5 shows the input line switching circuit 9,
6 shows the input line inspection circuit 10, FIG. 7 shows the product term line inspection circuit 11, FIG. 8 shows the output/line switching circuit 12, FIG. 9 shows the word line selection switching circuit 13, and FIG. 1O shows the bit@switching circuit. circuit 14
It is. Of the functional elements and logic symbols used in these figures, 32 are bidirectional gate circuits, 83 are bidirectional gate circuits, and 83 are bidirectional gate circuits.
84 is an OR circuit, 84 is a NANDAND circuit, 36 is an AND circuit, and 37 is a flag register.

In gate circuit 32, the wiring indicated by the arrow is rHJ.
state, the penetrating wiring is in a conductive state II),
In the rLj state, it becomes a cutoff state. The 35 /flag registers are connected so that the information of "1" can be shifted sequentially with the information of one register (stage) being "1" and the information of the remaining registers being "0". has been done.3
In the reset state, the flag register 7 holds the information “0°”.
° is written as 1, and the wire indicated by the arrow as input 1 is "
When it enters the IT J state, information “1°” is written 1 and “
Even if the circuit returns to the "," state, the information 1" is retained. Hereinafter, the functions of each of the circuits 101m from FIG. 5 will be explained.

The input line switching circuit in FIG.
A to 11 are simultaneously set to the rLJ state or the [II J state, independently of the input signals applied to the input terminals 20α to 20d, and the shift register 3
5, one of the input lines la to lf is sequentially selected to put it in the II J state and the remaining ones are put in the r L J state, and the input line switching information line 1512 is operated by the input line inspection circuit lO shown in FIG. It is provided with means for switching the connections between the input terminals 20a to 20d and the input lines la to 11 in units of input line blocks in accordance with input line switching information provided via the input line switching information 150. The operation of sequentially selecting and setting to the "11" state is not performed on blocks in which a defect has already been detected according to the input line switching information provided via the input line switching information line 15a]-50.

The input line inspection circuit in FIG. 6 is the input line switching circuit 9 in FIG.
When manually setting IJJla to 1b to be in the "L" state or "HJ state," detect an input line whose potential is fixed at the "I-I J state" or "T," state. , when input lines are sequentially selected in the input line switching circuit 9 and set to the "1-■" state, the "II" state (( Means for generating switching information corresponding to a block related to an input line from the potential of a certain input line and inspection information provided by the product term line inspection circuit 11 shown in FIG. 7 via the product term line inspection information line 18; Means for summing the two pieces of switching information and holding it as input line switching information in the flag register 37, and generating word line switching information corresponding to the block related to the input line from the input line switching information held in each flag register. It also includes means for applying the information from the word line switching information line 17+2 to the word line selection switching circuit 13 via the 1 and 7C.

The product term line inspection circuit shown in FIG.
When setting the means to set the HJ state and the rest to the rLJ state, and the information of the input line potential and the memory cell that can change the view of the intersection cell so that all of the product term lines 2α to 2e are in the sun/moon state, , a means for detecting a product term line whose potential is fixed in the F L J state and generating switching information corresponding to a block related to the product term line;
When set to be in the LJ state, there is a means for detecting the product term line whose potential is fixed in the "I" state and generating switching information, and a means for sequentially selecting the product term line to enter the [I-I J state]. When setting, the block related to the product term line is determined from the potential of the product term line in the f-IJ state and the inspection information provided via the output line inspection information line 19 by the output line switching circuit 12 shown in FIG. means for generating corresponding switching information; means for summing up the above-mentioned switching information and holding it as product term line switching information in a flag register 87;
Generates product term line inspection information indicating whether the block is in the J state and whether the product term line other than the block in which defects have been detected is in the "■【" state, and reports the product term line inspection. The bit line switching information @ 16a to 16d is applied to the bit line switching circuit of FIG. 14.

The output line switching circuit shown in FIG. 8 is configured such that when the potential of the product term line and the information of the rewritable memory cell of the intersection cell are set so that all of the output lines 3a to 3c are in the I-I J state, , a means for detecting an output line whose potential is fixed in the rLJ state and generating switching information corresponding to a block related to the product term line; and, conversely, when all the product term lines are set to be in the rLl state. In addition, there is a means for detecting an output line whose potential is fixed to the rHJ state and generating switching information, a means for summing the two pieces of switching information and holding it as output line switching information in a flag register 87, and a means for all of the output lines. "L"
means for generating and applying output line inspection information to the output line inspection information line 19 indicating whether the block is in the "H" state and whether output lines other than the block in which a defect has already been detected are in the "H"state; Means for generating word line switching information according to the output line switching information held in the flag register 37, applying it to the word line switching information lines L7d to 17f, and switching the connection between the output lines 3α to 30 and the output terminals 21α and 21b. Equipped with:

The word line selection circuit in FIG. 9 sequentially selects one of the word lines 7a to 7L by the shift register 85 to
'' state and the rest to rLJ state, and when the word line switching information given by the word line switching information lines 17α to 17.7' is rHJ, the block related to the input line to which this information belongs and the block related to the output line Of the remaining word lines except for the word lines, means is provided for sequentially selecting one line to put it in the rHJ state and putting the rest in the "L" state in the same way as described above.

The bit line switching circuit shown in FIG.
8e to the rHJ state, means to set the bit line switching information lines 16a to 1 to the rLJ state in order to write the test information II and OII, and the bit line switching information lines 16a to 1
According to the bit line switching information provided by 6d, bit lines 8a to 8e and programming terminals 22a to 22
It is equipped with means for switching the connection with d.

The purchase of one embodiment of the present invention has been described above, but in order to operate the PLA of this embodiment, PLA testing, redundancy switching,
Perform the programming procedure. These procedures are executed during the period defined by control signals TEO to TE11 shown in FIG. Among these control signals, TE
O to TE9 are test procedures, TE10 is redundant switching procedure, T
E11 corresponds to the programming procedure. FIG. 12 is a timing chart of control signals TEO to TE11, clock CL, and control signal TE.

These steps will be explained below with reference to FIG.

Test procedure: First, in the test procedure, during the TEO period, the contents of the shift register and flag register are reset to 0'' information.In the reset state, the outputs of these registers are in the rLJ state. In Figure 1O, wiring for the control signal TBO is omitted.

In the next TE1 period, information 0° is written as test information into the rewritable memory cells of all the intersection cells.

At this time, in the bit line switching circuit 14 of FIG. 1O, all the bit lines are set to the rLJ state by the control signal TEL, and in the word line selection switching circuit 18 of FIG. The information "1" is set to , and one piece of information "1" is sequentially shifted by the clock CL. Information “1” is set/The word line connected to the foot register is rH
Since the state is J, information 0'° is sequentially written into all rewritable memory cells.

In the next TB2 period, the input line switching circuit 9 shown in FIG. 5 sets all the input lines after the inverter to be in the rLJ state. At this time, the input line inspection circuit IO of FIG. 6 detects an input line in the rHJ state due to a defect in an inverter or the like, generates input line switching information, and fixes the input line in the rHJ state to the rLJ state. Further, the product term line inspection circuit 11 shown in FIG. 7 detects a product term line that is in an "L" state due to a disconnection or a short circuit with an input line, and generates product term line switching information.

In the next TE3 period, the input line switching circuit 9 shown in FIG. 5 sets all input lines after the inverter to be in the rLJ state. At this time, in the input line inspection circuit 10 of FIG.
By fixing to the rLJ state according to the test results of the period, “L
” and generates input line switching information. Further, in the product term line inspection circuit 11 of FIG. 7, all product term lines are set to the "L" state. At this time, in the output line switching circuit 12 of FIG. 8, if the output is in the "L" state due to a disconnection or short circuit with the product term line, or if the output is in the rLJ state due to failure or a defect in the inverter, an equivalent output line is detected. death,
Generates output line switching information.

Between the next TE4E, the input line switching circuit 9 in FIG.
Select the books one by one and set them to the "g" state one by one, and set the rest to the rLJ state. At this time, in the product term line inspection circuit 11 of FIG. 7, among the product term lines other than the blocks in which defects have already been detected, the rewritable memory cells of the AND array are fixed to the information "■", etc. A product term line in the r L J state due to the defect is detected, and product term line inspection information is generated.

The input line inspection circuit 10 of FIG. 6 generates input line switching information from this product term line inspection information and the potential of the input line in the HJ state.

Between the next TE5E, the product term line inspection circuit 11 shown in FIG. 7 selects the product term lines one by one and sets them to the "11" state one by one, and sets the remaining ones to the "7" state.

[Output line switching circuit in Figure 8] 2, there is a defect such as a rewritable memory cell of the OR array fixing the information to "1" among the output lines other than the block in which the defect has already been detected. 1, detect the output line in the L J state,
Generates output line inspection information. The product term checking circuit 11 in Figure 7 generates product term line switching information from this output line inspection information and the potential of the product term line in the [I(J) state.

During the next TE6E, information "1" is written as a test report into all rewritable memory cells using the same procedure as during TE1E.

In the next 'r' E7 period, in the same way as the TE time and effort described in M, the input line switching circuit 9 in FIG. '' state, and the rest are set to rLJ state 1 (set. At this time, in the product term line inspection circuit 11 of FIG. A product term line in the 1'-1-(J state is detected due to a defect such as the line being fixed in the "II" state, and product term line inspection information is generated. A signal T indicating that one wire is in the [1-T J state
In synchronization with E 7', the product term line in the [1-I J state is detected, and switching information corresponding to the block related to the product term line is generated.

In the input line inspection circuit 10 of FIG. 6, the product term line inspection information and the
Input line switching information is generated from the potential of the input line in the "II" state.

Between the next TE8E, the product term line inspection circuit 11 of FIG. Set to . At this time, in the output line switching circuit 12 of FIG. 8, the rewritable memory cell of the OR array is
An output line that is in the rHJ state due to a defect such as the output line being fixed at °° or the output line being fixed in the "■1" state is detected, and output line inspection information is generated. A signal T' indicating that at least one of the product term lines is in the rHJ state.
In synchronization with E8', the output line in the I-I J state is detected and switching information corresponding to the block related to the output line is generated.In the product term line inspection circuit 1 of FIG. and [tl Product term line switching information is generated from the potential of the product term line in the J state.

During the next TE9E, information "[]"° is written into all the rewritable memory cells in the same way as during the TE1E described above. This completes the test procedure.

Redundancy switching procedure: Redundancy switching is performed in 'I''E ], O periods. As explained in FIGS. 2 and 3, in the PLA of this embodiment, blocks related to input lines and blocks related to product term lines One redundant block is provided for each of the blocks related to the output line and the output line.Therefore, the existence of defects can be tolerated for 2261 basic blocks.

Between TEIOEs, blocks related to input terminals and input lines, and blocks related to output terminals and output lines are switched according to switching information held in flag registers provided corresponding to blocks of input lines, product term lines, and output lines. Switch connections between blocks related to word lines and input lines, blocks related to output lines, and blocks related to programming terminals and product term lines. With such redundant switching,
This PLA is placed in a state equivalent to when it is composed of only basic blocks.

Programming procedure: Programming of logic functions is performed during the TEII period. During programming, the word line selection switching circuit 18 shown in FIG. 10 sequentially selects the word lines of the block related to the input line and the block related to the output line that are to be used as a result of redundancy switching, and puts them in the rHJ state. This is done by providing programming information, which is binary information, from the programming terminal 22 in synchronization with . Through the above programming procedure, programming information is written to the rewritable memory cells of the intersection cells belonging to the block to be used, and information "0" is written to the blocks that are not to be used. This allows the PLA to execute logical operations according to programming information.

In the embodiments of the present invention described above, volatile static RAM cells are used as rewritable memory cells and flag registers, but any memory cell with an easily rewritable structure and that can be integrated can be used. , can be applied regardless of whether it is volatile or non-volatile. Further, in this embodiment, all circuits are realized using E/T) MO8 circuit technology, but even if other integrated circuit technologies are applied, the PL related to the present invention will not be affected.
A can be constructed. In addition, many modifications to the PLA circuit configuration (redundant configuration and test procedure) other than those described in the embodiments are easily possible.

Description of Effects As explained above, in the rewritable PLA of the present invention, the input lines constituting the AND array and the OR array,
A redundant configuration is applied to each of the product term line, the output line, and the circuits associated with these, which has a high defect relief effect with a small degree of redundancy. P indicates the existence of defects on a scale that cannot be handled by technology.
It is possible to allow the entire surface of T and A to perform logical functions normally. Further, defect detection for redundancy switching can be automatically performed using a built-in circuit using a simple test procedure that focuses on the circuit function of the PLA, independent of the logic function set by programming.

Therefore, the manufacturing yield of PLA can be significantly improved, and the cost of testing after manufacturing can also be significantly reduced. Furthermore, when creating programming information that is binary information for programming, it can be treated as if it were always composed of basic blocks without considering redundancy switching.

As an application field of the present invention, when constructing a large-scale logic integrated circuit in which a large number of PLAs are integrated on the same semiconductor chip, it is possible to reduce the number of external connection points and improve the degree of integration. 7 can be achieved by simplifying the implementation of the applied system and making it more economical by downsizing. In such a system, the button that operates the PLA performs PLA testing and redundancy switching at system startup, and
This is done by writing programming information from a read-only memory built into the same semiconductor chip as A or from an external memory. In such a system, during system development, by writing programming information for testing, it is possible to easily separate malfunctions due to defects from malfunctions due to logic bugs, and it is also possible to easily conduct tests that focus on connections between multiple PLAs and on specific PLAs. . Furthermore, in terms of maintenance, defects that occur during operation can be repaired by repeating the testing, redundancy switching, and programming procedures at system start-up. Furthermore, by performing testing and redundancy switching in advance when rewriting the programming information of the PLA according to the purpose of arithmetic processing during operation, it is possible to reduce the probability that a processing error will occur during operation. However, in conjunction with the function that detects errors in other processing results, when a processing error occurs, testing, redundancy switching, and programming procedures are executed to prevent system downtime due to processing errors. It is possible to do so.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a PLA according to an embodiment of the present invention, FIGS. 2 and 8 are conceptual diagrams showing how the PLA shown in FIG. 1 is divided in a redundant configuration, and FIG. Figure 1 is a partial configuration diagram of the AND array and OR array of PLA. Figure 5 is a logical configuration diagram of the input line switching circuit in Figure 1.
Figure 7 is a logical configuration diagram of the same line testing circuit, Figure 7 is a logical configuration diagram of the same line testing circuit, Figure 8 is a logical configuration diagram of the output line switching circuit, and Figure 9 is the word line selection switching circuit. The logical configuration diagram of the bit line switching circuit, Figure 1O is the logical configuration diagram of the same bit line switching circuit,
1 is a diagram showing the operating procedure of the PLA shown in FIG. 1, and FIG. 12 is a timing chart of control signals of the PLA shown in FIG. 1. ■...Input line, 2...Product term line, 3...Output line, 4
... Intersection cell, 5... Inverter, 6... Pull-up circuit, 7... Word line, 8... Bit line, 9...
...Input line switching circuit, 10...Input line inspection circuit, ll
...Product term line inspection circuit, 12...Output line switching circuit, 1
3... Word line selection switching circuit, ■4... Bit line switching circuit, 15... Input line switching information line, 16... Bit line switching information line, 17... Word line switching information line, 18
...Product term line switching information line 2.19...Output line inspection information line, 20...Input terminal, 21...Output terminal, 22...
...Programming terminal, 28...Power supply terminal, 24.
...AND array, 25...OR array, 26...
Blocks related to input lines, 27...Blocks related to output lines, 28...Blocks related to product term lines, 29...
・Rewritable memory cells. Fig. 1] Fang 2 Fig. 28a 28b 28c 28d 28e)・
Figure 4], Figure 5, Figure 3'6

Claims (1)

[Claims] (1) Equipped with a rewritable memory cell at the intersection of the input line and the product term line and the product term line and the output line,
In a logic array consisting of an AND array and an OR array in which logic functions are programmed by writing value information, the AND array and the OR array are divided into basic blocks and redundant blocks with respect to the input line, product term line, and output line, respectively. and means for generating test information and writing it into the memory cell independently of programming of logic functions; means for setting the potentials of the input line and the product term line independently of the input signal; means for detecting the potentials of a line, a product term line, and an output line to generate and hold switching information indicating whether or not at least the basic block includes a defect; A programmable logic array comprising means for replacing redundant blocks.