JP2005063529A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device whose defect analyzing time is shortened. <P>SOLUTION: This device is provided with a plurality of word lines and a plurality of bit line pairs, and a memory cell array arranged at the intersection point between the word and bit lines, and a means for simulatively or actually causing a specific memory cell arrays to go out of order. A mask is prepared which is capable of prefixing a memory cell state to a High or Low failure state, by fixing one of the bit lines connected to the specific memory cell to Low and the other to High. Alternatively, a fuse circuit containing a logical gate is prepared for two bit lines connected to the specific memory cell, the bit lines are controlled by cutting the fuse, and the memory cell is fixed in a High or Low failure state, when the word lines connected to the memory cell are asserted. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device, and more particularly to an inspection technique thereof.

  With the progress of higher integration and miniaturization of semiconductor integrated devices, development of multifunctional one-chip system LSIs that combine single-function large-scale integrated circuits (LSIs) has become active. Along with this, LSI inspection and analysis of defective judgment products by the inspection have become more complicated and more man-hours are required, and higher efficiency is desired.

  One of the inspection items with a high defect rate among LSI inspection items is inspection of a semiconductor memory device (SRAM). In order to improve the yield of LSI inspection, the following process is usually taken. A defective part is identified for an inspection defective LSI, the cause of the defect is investigated, and the result is fed back to the manufacturing process and circuit design.

As a method often used as a method for identifying a defective portion in a semiconductor memory device, there is an FBM (Fail Bitmap) method. The FBM expresses as a physical arrangement where a defective portion of a semiconductor memory device exists in which column and in which row on the semiconductor memory device. Usually, the result of inspection of the semiconductor memory device and the semiconductor It is created by a correspondence table between storage device addresses and their physical locations. A defective part is identified from the created FBM, the cause of the defect is investigated, and the result is fed back.
Japanese Patent Laid-Open No. 7-12900

  Although the defective part is specified by the FBM method, the created FBM itself may be wrong, and if it is wrong, a huge amount of man-hours is required. The reason why an incorrect FMB is created is as follows. One is a case where there is a problem in the inspection result of the semiconductor memory device. This is due to an incorrect inspection pattern, an incorrect inspection specification, a defect in the inspection apparatus, and the like. The other is an error in the correspondence table between the address of the semiconductor memory device and its physical arrangement. This is due to incomplete specifications of the semiconductor memory device. As described above, there is a high possibility that an error is mixed in the created FBM itself. Nevertheless, the conventional semiconductor memory device does not have a mechanism for clearly associating an address with its physical layout. Therefore, the FBM's correct / incorrect determination is made by physically analyzing the location pointed to by the FBM, It is the present situation that can not be done without opening and observing. When it is determined that the FBM is incorrect, the inspection pattern, the address of the semiconductor memory device, and the correspondence table between the physical arrangement and the like are reconfirmed, the defect is removed, the FBM is recreated, and the physical analysis is performed again. Take the process of If the FBM is still wrong, the above process is repeated endlessly, and enormous man-hours are required.

  The present invention has been made in view of the above-described problems. By associating an address with a physical arrangement of a specific failure location, a semiconductor capable of effectively confirming an FBM and reducing the number of inspection steps. An object is to provide a storage device.

  In order to solve the above problems, a semiconductor memory device according to claim 1 of the present invention includes a plurality of word lines, a plurality of bit line pairs, and a memory arranged at an intersection of the word lines and the bit lines. The memory cell array includes a cell array and fixing means for fixing a storage state of a specific memory cell to a faulty state in a pseudo or actual manner.

  The semiconductor memory device according to claim 2 of the present invention is the semiconductor memory device according to claim 1, wherein the fixing means prepares in advance a failure state of the specific memory cell with a mask. It is what.

  The semiconductor memory device according to a third aspect of the present invention is the semiconductor memory device according to the first aspect, wherein the fixing unit is configured to operate the specific memory cell in a word line direction connected to the specific memory cell. Each of the bit line pairs controlling the storage state of the memory device is provided with a respective fuse circuit, and the fuse circuit disposed in the word line direction is cut to change the storage state of the specific memory cell to High or Low. It is characterized by being fixed to a state.

  A semiconductor memory device according to a fourth aspect of the present invention is the semiconductor memory device according to the first aspect, wherein the fixing means stores the memory cell in the direction of the word line connected to the specific memory cell. When the bit line pair that controls the state is provided with each logic gate and is set to a specific inspection state, the bit line pair is set to High or Low by a control signal input from the outside of the semiconductor memory device. By controlling, the storage state of the specific memory cell is fixed to a high or low failure state.

  According to the semiconductor memory device of the first aspect of the present invention, a plurality of word lines, a plurality of bit line pairs, a memory cell array disposed at an intersection of the word lines and the bit lines, and the memory cell array Among them, there is provided fixing means for fixing the storage state of a specific memory cell in a pseudo or actual failure state. Therefore, when specifying a defective portion of the semiconductor memory device, the failure state is determined by the address and the fixing means. It becomes possible to associate the physical arrangement of a specific memory cell that has been set, FBM can be confirmed effectively, and it is possible to contribute to shortening the inspection man-hour compared with the conventional method.

  According to a semiconductor memory device of a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the fixing unit is configured to previously prepare a failure state of the specific memory cell using a mask. The state of any specified memory cell in the semiconductor memory element can be fixed to a low or high failure state, which is effective for confirming the created FBM and contributes to a reduction in man-hours compared with the conventional method. can do.

  According to a semiconductor memory device of a third aspect of the present invention, in the semiconductor memory device according to the first aspect, the fixing means is configured to connect the specific memory in a direction of a word line connected to the specific memory cell. Each bit line pair that controls the memory state of the cell is provided with a respective fuse circuit, and the fuse circuit arranged in the word line direction is cut, whereby the memory state of the specific memory cell is set to High or Low. Since it is fixed in the failure state, the specific memory cell can be fixed in the failure state of Low or High by cutting the fuse without providing a mask separately, which is effective in confirming the created FBM. It can contribute to cost reduction.

  Furthermore, according to a semiconductor memory device of a fourth aspect of the present invention, in the semiconductor memory device according to the first aspect, the fixing means is configured to connect the memory in a direction of a word line connected to the specific memory cell. Each bit line pair that controls the memory state of the cell is provided with a respective logic gate, and when the bit line pair is set to a specific inspection state, the bit line pair is set to High by a control signal input from the outside of the semiconductor memory device. Alternatively, the memory state of the specific memory cell is fixed to a high or low failure state by controlling to Low, so that the semiconductor memory device is specified without being destroyed by signal control from the outside of the semiconductor memory device. The memory cell can be fixed to a high or low failure state, and the semiconductor memory device can be used not only for inspection but also as a normal device. Because to withstand the use of Te, it can contribute to cost reduction.

(Embodiment 1)
The semiconductor memory device according to the first embodiment of the present invention relates to a semiconductor memory device in which a specific memory cell failure is previously produced using a mask.

  First, FIG. 4 shows a basic configuration example of a conventional semiconductor memory device. In FIG. 4, a row decoder 102 for selecting word lines 100 and 101 in the row direction, bit lines 109 to 112, memory cell portions 103 to 106, and 107 which is a part of a write data input port to the semiconductor memory device. , 108. The memory cell portion has a latch circuit in which two inverters are connected in series, and two stable states can be ensured by controlling a pair of left and right bit lines, thereby discriminating between High and Low. doing. The specific memory cell is selected by selecting a specific bit line and word line by the row decoder.

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to Embodiment 1 of the present invention.
In FIG. 1, the memory cell unit 103 which is a specific memory cell has two unique bit lines, and the bit line connected to the transistor A is connected to a constant voltage and the bit line connected to the transistor B is connected to the ground. Thus, one end of the transistor A and one end of the transistor B can be fixed to High or Low, respectively. When the word line connected to the memory cell unit 103 is asserted by the selection of the row decoder 102, the latch circuit latches data from the bit line.

  As described above, in the semiconductor memory device according to the first embodiment of the present invention, apart from the mask for causing the semiconductor memory device to perform normal operation, one of the bit lines connected to a specific memory cell is set to Low and the other is set to the other. Since the mask for fixing the state of the specific memory cell to High or Low in advance is prepared by fixing to High, the state of any specified memory cell in the semiconductor memory element is prepared. Can be fixed to a low or high failure state, and it is possible to effectively confirm the created FBM by easily associating the address and the physical arrangement of the memory cell in a specific failure state. This can contribute to shortening the inspection man-hours.

(Embodiment 2)
FIG. 2 is a circuit diagram showing a configuration of the semiconductor memory device according to the second embodiment.
In FIG. 2, logic gates 201 and 211, selectors S1 to S4, and fuse circuits 113 and 114 including fuses are provided for a pair of bit lines 109 and 110 that control the storage state of the memory cell 103. . Further, since the other configuration of the semiconductor memory device is the same as that of the first embodiment, description thereof is omitted.

  When two fuses are connected, the selectors S1 to S4 always select the input 107 according to the High control signal, so that the operation of the memory cell 103 is the same as when the fuse circuit is not provided. Operate. That is, when the fuse is connected, the circuit of FIG. 2 is equivalent to the circuit of FIG.

  Next, setting of a failure state by cutting a fuse in the semiconductor memory device according to the second embodiment will be described.

  In a specific inspection state, the memory cell can be fixed to High or Low by cutting the fuse connected to 113 or 114.

  For example, when only the fuse connected to 113 is cut, the control signal to the selectors S1 to S4 is grounded and thus becomes Low. On the bit line 109 side, the selector S1 selects the output of the OR logic gate 201 by the Low control signal and outputs it to the bit line 109 connected to the transistor A. In addition, since the fuse connected to 114 is not cut, the output of the OR logic gate 201 is kept high, so that one end of the transistor A is always fixed to high regardless of the state change of the input 107. .

  On the bit line 110 side, the selector S3 selects the output of the NOR logic gate 211 by the Low control signal and outputs it to the bit line 110 connected to the transistor B. Further, since the fuse connected to 114 is not cut, the output of the NOR logic gate 211 is kept low, so that one end of the transistor B is always fixed to low regardless of the state change of the input 107. The

  Therefore, when the word line connected to the memory cell 103 is asserted, the storage state of the memory cell can be fixed to High or Low.

  Note that the selectors S2 and S4 select the input 107 again according to the Low control signal and output it to the bit lines 109 and 110, respectively. Accordingly, one end of the transistors A and B is fixed to High and Low, respectively, and does not affect other memory cells.

  Further, when both the fuses connected to 113 and 114 are cut, the control signal to the selectors S1 to S4 is grounded, so it becomes Low. On the bit line 109 side, the selector S1 selects the output of the OR logic gate 201 by the Low control signal and outputs it to the bit line 109 connected to the transistor A. Since both fuses are cut, the output of the OR logic gate 201 is kept low, so that one end of the transistor A is always fixed to low regardless of the state change of the input 107.

  On the bit line 110 side, the selector S3 selects the output of the NOR logic gate 211 by the Low control signal and outputs it to the bit line 110 connected to the transistor B. Since both fuses are blown, the output of the NOR logic gate 211 remains High, so that one end of the transistor B is always fixed to High regardless of the state change of the input 107.

  Therefore, even when all the fuses connected to 113 and 114 are cut, the memory cell can be fixed to High or Low by asserting the word line connected to the memory cell.

  Note that the selectors S2 and S4 select the input 107 again according to the Low control signal and output it to the bit lines 109 and 110, respectively. Therefore, one end of the transistors A and B is fixed to Low and High, respectively, but does not affect other memory cells.

  Thus, in the semiconductor memory device according to the second embodiment, a fuse circuit 113 including a selector, a logic gate, and a fuse for a pair of bit lines 109 and 110 that control the storage state of a specific memory cell 103, 114 is provided, so that the fuse connected to 113 or 114 is cut to control the bit line for setting the memory cell to a high or low state, and the word line connected to the memory cell is controlled. When asserted, the memory cell can be fixed to a high or low fault state. Therefore, in the semiconductor memory device according to the second embodiment, a specific memory cell can be fixed to a high or low failure state by cutting a fuse without providing a mask separately, which is effective in confirming the created FBM. It can contribute to cost reduction.

  Further, the above bit line control has no effect on memory cells other than fixed memory cells.

(Embodiment 3)
FIG. 3 is a circuit diagram showing a configuration of the semiconductor memory device according to the third embodiment.
In FIG. 3, logic gates 301 and 311 and selectors S1 to S4 are provided for a pair of bit lines 109 and 110 that control the storage state of the memory cell 103. The logic gates 301 and 311 receive a control signal from the outside of the semiconductor memory device, an FMB mode, and a High / Low control signal. Further, since the other configuration of the semiconductor memory device is the same as that of the first embodiment, description thereof is omitted.

  When the FMB mode is Low, that is, in normal operation, the selectors S1 to S4 always select the input 107 according to the Low control signal, so that the operation of the memory cell 103 is performed by the logic gates 301 and 311 and the selectors S1 to S1. It operates in the same way as when S4 is not provided. That is, the circuit of FIG. 2 at this time is equivalent to the circuit of FIG.

  Next, the setting of the failure state in the semiconductor memory device according to the third embodiment will be described.

  In a specific inspection state, the storage state of the memory cell can be fixed to High or Low by setting the FMB mode to High and setting the High / Low control signal to any one state.

  For example, when the FMB mode is High and the High / Low control signal is High, on the bit line 109 side, the selector S1 selects the output of the AND logic gate 301 according to the High control signal and is connected to the transistor A. Output to the bit line 109. The AND logic gate 301 outputs a Low signal to which the High FMB mode signal and the inverted signal of the High High / Low control signal are input. Therefore, one end of the transistor A is in the state of the input 107. Regardless of the change, it is fixed to Low.

  On the bit line 110 side, the selector S3 selects the output of the AND logic gate 311 according to the High control signal and outputs it to the bit line 110 connected to the transistor B. The AND logic gate 311 outputs a High signal to which a High FMB mode signal and a High H / High / Low control signal are input. Therefore, one end of the transistor B changes the state of the input 107. Regardless, it is fixed to High.

  Therefore, when the word line connected to the memory cell 103 is asserted, the storage state of the memory cell can be fixed to High or Low.

  Note that the selectors S2 and S4 select the input 107 again according to the High control signal and output it to the bit lines 109 and 110, respectively. Therefore, one end of the transistors A and B is fixed to Low and High, respectively, but does not affect other memory cells.

  When the FMB mode is High and the High / Low control signal is Low, on the bit line 109 side, the selector S1 selects the output of the AND logic gate 301 and is connected to the transistor A by the High control signal. Output to the bit line 109. The AND logic gate 301 outputs a High signal to which a High FMB mode signal and an inverted signal of a Low High / Low control signal are input. Therefore, one end of the transistor A is in the state of the input 107. Regardless of the change, it is fixed to High.

  On the bit line 110 side, the selector S3 selects the output of the AND logic gate 311 by the High control signal and outputs it to the bit line 110 connected to the transistor B. The AND logic gate 311 outputs a Low signal to which the High FMB mode signal and the Low H / high / Low control signal are input, so that one end of the transistor B changes the state of the input 107. Regardless, it is fixed to Low.

  Therefore, when the word line connected to the memory cell 103 is asserted, the storage state of the memory cell can be fixed to High or Low.

  Note that the selectors S2 and S4 select the input 107 again according to the High control signal and output it to the bit lines 109 and 110, respectively. Therefore, one end of the transistors A and B is fixed to High and Low, respectively, but does not affect other memory cells.

  As described above, in the semiconductor memory device according to the third embodiment, the bit line pair 109, 110 that controls the storage state of the specific memory cell 103 is provided with a selector, a logic gate, and the like to be in a specific inspection state. When setting, the state of the specific memory cell 103 can be fixed to High or Low by controlling the bit line by two control signals outside the semiconductor memory device. Therefore, the semiconductor memory device according to the third embodiment is created because a specific memory cell can be fixed in a high or low failure state without destroying the semiconductor memory device by signal control from the outside of the semiconductor memory device. This is effective for FBM confirmation. For example, when the function according to the present invention is not used after the start of a new semiconductor process, it can withstand use as a normal device, which contributes to cost reduction. it can.

  The control of the bit line has no effect on memory cells other than fixed memory cells.

  The semiconductor memory device according to the present invention has an effect of effectively checking the FBM for specifying the defective part by associating the address with the physical arrangement of the specific faulty part and reducing the inspection man-hours. Therefore, it is useful as a semiconductor memory device that shortens the failure analysis time of the semiconductor memory device.

1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the semiconductor memory device by Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the semiconductor memory device by Embodiment 3 of this invention. It is a circuit diagram which shows the structure of the conventional semiconductor memory device.

Explanation of symbols

100, 101 Word line 102 Row decoder 103-106 Memory cell unit 107, 108 Data input port 109-112 Bit line pair 113, 114 Fuse circuit 201 OR logic gate 211 NOR logic gate 301, 311 AND logic gate S1-S4 selector

Claims (4)

A plurality of word lines and a plurality of bit line pairs;
A memory cell array disposed at an intersection of the word line and the bit line;
Fixing means for fixing a memory state of a specific memory cell in the memory cell array in a pseudo or actually faulty state,
A semiconductor memory device. The semiconductor memory device according to claim 1,
The fixing means includes
Producing a failure state of the specific memory cell in advance with a mask,
A semiconductor memory device. The semiconductor memory device according to claim 1,
The fixing means includes
With respect to the direction of the word line connected to the specific memory cell, each bit line pair that controls the storage state of the specific memory cell includes a respective fuse circuit,
By cutting the fuse circuit arranged in the word line direction, the storage state of the specific memory cell is fixed to a high or low failure state.
A semiconductor memory device. The semiconductor memory device according to claim 1,
The fixing means includes
With respect to the direction of the word line connected to the specific memory cell, each bit line pair that controls the storage state of the memory cell includes a respective logic gate,
When setting to a specific inspection state, the bit line pair is controlled to be High or Low by a control signal input from the outside of the semiconductor memory device, and the storage state of the specific memory cell is set to High or Low. To fix the failure state of
A semiconductor memory device.

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