JPS58153290A - System for invalidating buffer memory - Google Patents

Abstract

PURPOSE:To control the invalidating operation of a buffer memory and increase the speed of the invalidating operation, by installing a bit which indicates at least one registering unit of the buffer memory is cut off, and detecting the existence of cut off from the condition of the bit. CONSTITUTION:One registering unit 4 of an address converting buffer memory 3 is fetched into a read-out data register 5 by an address register 1. A cut-off bit 6 is installed in the read-out data register 5 and the cut-off 6 is inputted into a invalidating control circuit 7. When a cut off of the registering unit exists in a memory 3, its cut-off bit D is turned on and a degradation register 8 which indicates that the cut off is generated is also turned on and the wirting of invalidated data in the memory 3 is inhibited. When no cut off is generated, the writing is performed irrespective of the cut-off bit. Therefore, the existence of a cut off is known before starting the invalidating operation, and thus, the invalidating processing speed is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a buffer memory invalidation method, and particularly to a buffer memory invalidation method such as a high-speed buffer memory and an address conversion (rough memory) memory.

Conventional technology Conventionally, when there is a failure in a memory element in a high-speed buffer memory or address conversion (address conversion) area memory that enables the separation of registration units, the registration unit is separated (the separation bit is turned ON) and in subsequent operations. The system prohibited the use of the registered unit, retained the contents as they were at the time of separation, and prohibited any rewriting operations on the separated registration unit for use in error analysis. If the memory is invalidated in such a way that the registered contents cannot be used in subsequent operations, the rewriting operation due to invalidation is also prohibited for the separated registration unit.

Here, invalidation is an operation to make the already registered contents unusable in subsequent processing.If you re-register the contents, the registration unit becomes usable. If the registration unit becomes unusable due to a failure of the memory element or the like, it cannot be newly registered in subsequent processing.

The buffer memory invalidation operation that enables the separation of registration units is a process that detects whether the registration unit has been separated for each registration unit, invalidates it if it has not been separated, and leaves it as is if it has. 1 to detect whether it is done and is generally detached.
It took two machine cycles, one machine cycle, for each registration unit to invalidate the data if it had not been done. Since there is a detachment bit for each registration unit, the above processing is performed by multiplying the number of columns of the buffer memory (2 x 2 = 512 in the case of a buffer memory addressed in 8bHs) regardless of whether detachment occurs or not.
) was necessary.

In recent years, the status of high-speed buffer memory and address conversion pan-7 memory has been increasing, and the number of registered units has also increased, so the time required for invalidation has also increased, making it difficult for processing devices that require high-speed performance. , which is a cause of performance deterioration that cannot be ignored.

OBJECTS OF THE INVENTION It is an object of the present invention to achieve the effect of speeding up memory invalidation by eliminating the operation of detecting whether a registration unit has been separated when a buffer memory is not separated. An object of the present invention is to provide a method for invalidating a buffer memory that has a buffer memory.

General Introduction to the Invention The present invention is characterized by providing a bit indicating that at least one registration unit of the buffer memory is disconnected, and controlling the invalidation operation of the buffer memory based on the state of this bit. It is something.

Embodiment of the Invention and Its Effects FIG. 1 shows a buffer memory invalidation method as an embodiment of the invention, and an address translation buffer memory is considered as the buffer memory.

One registration unit 4 of the address translation buffer memory 3 is taken into the successive data register 5 by the address register 1. The disconnection bit 6 in the read data register 5 is input to the invalidation control circuit 7. The invalidation data 2 is written into the registration area designated by the address register 1 under the control of the invalidation control circuit 7.

At least one entry is made in the address translation buffer memory 3.
The output of the degradation register 8 indicating that a recording unit has been disconnected is input to the invalidation control circuit 7.

When at least one registration unit is disconnected in the address translation buffer memory 3, the disconnection bit in that registration unit (indicated by XD' in the registration unit 4) is turned ON.
, and the degradation register 8 also turns ON.

The degradation register 8 is turned from OFF to ON when a failure is detected for the first time in a memory element constituting the address conversion rougher memory 5.

First of all, Degrade! The invalidation of the address translation buffer memory 3 when the input register B is ON will be described.

At this time, the registered data 4 specified by the address register 1 is transferred to the read data register 5. The detachment bit 6 in the successive data register 5 is input to the invalidation control circuit 7, and when it is ON, an AND is established with the contents of the degradation register 8, and the address conversion buffer memory of the invalidation data is established. 3
Writing to is suppressed. However, when the separation bit 6 in the read data register 5 is OFF, the AND with the contents of the degradation register 8 is not established, and the invalidation data is written to the address translation buffer memory 3. That is, when the degradation register 8 is ON, the contents of the address translation buffer memory 3 are read out as in the conventional example, and writing of invalidation data is controlled depending on the state of the disconnection bit.

Next, when the degradation register 8 is OFF, that is, when no disconnection has occurred in the address translation buffer memory 3, the disconnection bit in the successive data register 5 is ignored, and the invalidation control circuit 7
The invalidation data 2 is written to the registration area designated by the address register 1. In other words, when the degradation register 8 is OFF, there is no need to read the contents of the address translation buffer memory B and determine the state of the disconnection bit, so the invalidation data can only be written by that amount. It can be done quickly.

Generally, it takes one machine cycle to read the contents of the address translation buffer memory 3 and determine the data, and it takes one machine cycle to write invalidation data to the address translation buffer memory 3. - When register 8 is OFF, the buffer memory can be invalidated in half the number of machine cycles compared to the conventional method.

In recent years, the reliability of memory devices has improved, and the probability of a deletion occurrence has become extremely small. Therefore, with this method, the buffer memory can be invalidated in about half the number of cycles compared to conventional methods. It will be done.

Effects of the Invention According to the present invention, it is possible to determine whether at least one detachment has occurred in the buffer memory before starting the invalidation operation, so that when no detachment has occurred,
Buffer memory can be disabled without searching for the state of the detach bit. Therefore, the processing time required for invalidation can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a buffer memory invalidation method showing one embodiment of the invention. DESCRIPTION OF SYMBOLS 1... Address register, 5... Read data register, 7... Invalidation control circuit, 8... Degradation register. 1 1 Figure

Claims (1)

[Claims] In a buffer memory invalidation method that has a detachment bit in the buffer memory for each registration unit and enables the separation and deletion of the registration unit, at least one of the detachment bits is in a state indicating detachment. a means for searching the state of the cutoff bit and controlling the invalidation of registered contents based on the result; and a means for invalidating the registered contents without searching for the state of the cutoff bit. and when at least one of the detachment bits in the buffer memory indicates a state indicating detachment in the first means, the state of the detachment bit of the registration unit groove is searched, and the registered contents are invalidated based on the result. control, and when the first means indicates a state in which no separation of registration units has occurred, the registration contents are invalidated without searching the state of the separation bit. Features and invalidation method of suru buffer memory.