JPH0348335A - Fault processing system - Google Patents

Abstract

PURPOSE:To effectively utilize another entry at the time of generating a fault in a certain entry by setting up an error bit(Ebit) only in the entry generating the fault. CONSTITUTION:When an error is detected by a parity checker(PC) 6 for checking the error of an output generated from a branch history table (BHT) 1, the error information is informed to a control circuit 8 and fault processing is started. The contents of an address register(AD) 2 are the address of the entry generating the fault, the address is retreated to an address register buffer(ARB) 3 and then the output of the ARB 3 is selected by a selector 4 based upon an instruction generated from the control circuit 8. At the selection timing, the control circuit 8 resets the valid bit of the entry generating the fault in the BHT 1 and sets up the error bit(Ebit) of the entry through a control line 101. Thus, another entry effectively is utilized at the time of generating a fault in a certain entry.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a failure handling method for an information processing device, and particularly to failure handling in a branch history table.

[Conventional technology]

Conventionally, a branch history table that stores the address of a branch instruction and a branch destination address as a pair is composed of a memory element, and when handling a fault in the branch history table,
When an error is detected in the output of a memory element, the entire branch history table is disconnected and the information processing device continues to operate.

[Problem to be solved by the invention]

In the conventional fault handling method described above, it is necessary to disconnect the entire branch history table even if the error occurs in one word of a memory element, which poses the problem that other words cannot be used effectively. .

An object of the present invention is to provide a fault handling method that can effectively utilize other words (other entries).

[Means for solving the problem] In the present invention, when processing a fault in a branch history table that stores a branch instruction address and a branch destination address as a pair, the fault in the branch history table is recorded as an entry. When the failure is detected, The present invention is characterized in that the failure occurrence entry address of the branch history table is held, and the entry specified by the held factory address is invalidated and rendered unusable.

〔Example〕

Next, the present invention will be explained with reference to examples.

Referring to Figure 1, 1 is the branch history table (BI
T), 2 is an address register (AR), 3 is an address register puffer (ARB), 4 is a selector, 5 is a comparator, 6 is a gelity checker (PC)
, 7 is an AND dart, 8 is a control circuit, and 9 is a read register (RDR).

Due to normal operation, when an instruction is prefetched, the instruction address is set in AR2, selected by selector 4, and
Address HT1. As shown in Figure 2, each entry in BHT 1 includes a part of the instruction address, a branch destination address, a valid bit (V), and a fault bit. detected,
When ■=:l and E=0 of the corresponding entry are detected by the AND gate 7, this detection information is reported to the control circuit 8. The branch destination address read from the stored BIT 1 is set in RDR 9. And RDR 9
Preemption 9 of the branch destination instruction is started using the output of .

Next, the failure handling operation will be explained.

When an error is detected by the PC 6 which checks the output of the BIT 1 for errors, the error information is reported to the control 1 output circuit 8 and trouble handling is started. The contents of A R 2 are:
This is the address of the enotli where the failure occurred, and it is the AR
It will be evacuated to B3.

Next, after the control circuit 80 commands, the selector 4 selects the ARB.
3 output is selected. Press the button at this selection timing,
The control circuit 8 uses the control line 102 to reset the Vbit of the entry in which the BHTI fault has occurred, and also resets the control line 1.
01 sets the E (Error) bit of the entry.

〔Effect of the invention〕

As explained above, in the present invention, since the error bit (Eb + t) ft is set only in the entry where a failure has occurred, it is possible to separate instruction addresses, etc. according to the entry, and the effect is that other entries can be effectively used when a failure occurs. There is.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing the structure of a branch history table. l...Branch history table (BIT). 2
... Address register (AR), 3... Address renoster buffer (ARB), 4... Selector, 5... Comparator, 6... Nosority check force - (P
C). 7...AND dart, 8...control circuit, 9.
...Read register (RDR).

Claims (1)

[Claims] 1. In an information processing apparatus that includes a branch history table that stores a branch instruction address and a branch destination address in pairs and performs instruction prefetch processing, a detection means that detects a fault entry in the branch history table; a holding means for holding a failure entry address in the branch history table when a failure in the history table is detected; 1. A failure handling method characterized by having a nullification means for disabling the state.