JPS5815243A - Mounting structure for semiconductor integrated circuit - Google Patents
Mounting structure for semiconductor integrated circuitInfo
- Publication number
- JPS5815243A JPS5815243A JP56113828A JP11382881A JPS5815243A JP S5815243 A JPS5815243 A JP S5815243A JP 56113828 A JP56113828 A JP 56113828A JP 11382881 A JP11382881 A JP 11382881A JP S5815243 A JPS5815243 A JP S5815243A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- mounting structure
- chip
- anisotropic conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4827—Materials
- H01L23/4828—Conductive organic material or pastes, e.g. conductive adhesives, inks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
Abstract
Description
【発明の詳細な説明】
本発明は半導体集積回路（以下の説明においては工０チ
ップと略して書く、）の実装構造に関する。さらに本発
明は工０チップの高密度実装に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mounting structure of a semiconductor integrated circuit (abbreviated as "chip" in the following description). Furthermore, the present invention relates to high-density packaging of zero-chip chips.
今日、ＩＯはエレクトロニクス産業の米としてあらゆる
製品に用いられている。今後も工０の生産量は増々大き
くなるものと考えられる。Today, IO is used in all kinds of products in the electronics industry. It is thought that the production volume of 0-manufacturing will continue to increase in the future.
ｘＯは量産効果の非常に大きい部品であるためＩＯチッ
プ巳ストは年毎に低くなって来ている。Since xO is a component that has a very large mass production effect, the cost of IO chips is decreasing year by year.
しかし工０の実装コストは、工０チップコスト程に低か
らず、大きな課題となって来ている。However, the cost of zero-process implementation is not as low as the cost of zero-process chips, and has become a major issue.
ＩＯ−チツプ実装方式は、一般的なワイヤボンディング
法、テープキャリア法、７リツプチツプ法等があり、そ
れぞれのメリットを活かした形で広く用いられている０
本発明はこれら従来の実装方式以上に簡単でしかも低コ
ストの工０チップ実装を実現するところにある。IO-chip mounting methods include the general wire bonding method, tape carrier method, and 7-lip chip method, which are widely used by taking advantage of the merits of each.
The purpose of the present invention is to realize chip mounting that is simpler and less costly than these conventional mounting methods.
以下本発明について具体的な実施例をもとにして説明す
る。The present invention will be described below based on specific examples.
第１図は本発明に用いる異方性導電ゴムシートの説明図
である。第１図（＠）に示す如く薄いシート状をしてお
り、母材がゴムであるため７レキシプルである。シート
の厚さはα０５〜５ｍまで任意のものがある。このシー
トは、第１図（＆）に示す如く、細長い導電体がシート
の厚み方向に無数に配列されており、その導電体はシー
ト表面より数μ慣程度突出している。第１図中の１はゴ
ムシート、２は母材のゴム、３は細長い導電体である。FIG. 1 is an explanatory diagram of an anisotropic conductive rubber sheet used in the present invention. As shown in Figure 1 (@), it is in the form of a thin sheet, and the base material is rubber, so it has a 7 lexiple. The thickness of the sheet may be arbitrary from α05 to 5 m. In this sheet, as shown in FIG. 1 (&), a countless number of elongated conductors are arranged in the thickness direction of the sheet, and the conductors protrude from the surface of the sheet by several micrometers. In FIG. 1, 1 is a rubber sheet, 2 is a base material of rubber, and 3 is an elongated conductor.
第１図（ａ）は、上方から見た場合の導電体の配列を示
す説明図である。すなわち、シート間に対して垂直な方
向では導電体であり、平行な方向では絶縁体の異方性導
電ゴムである。導電体は、カーボンのファイバーでも良
いし、ステンレスの細線、金の細線、あるいは金メッキ
した金属細線でも良い・、基板との接触抵抗を低げるに
は、金メッキした金属細線が適当である。FIG. 1(a) is an explanatory diagram showing the arrangement of conductors when viewed from above. In other words, the anisotropic conductive rubber is a conductor in the direction perpendicular to the space between the sheets and an insulator in the parallel direction. The conductor may be a carbon fiber, a stainless steel wire, a gold wire, or a gold-plated metal wire.To reduce the contact resistance with the substrate, a gold-plated metal wire is suitable.
次にこの異方性導電ゴムシートを用いた本発明の具体的
実施例を第２図に示す。第２図において４は、リード線
５が形成された回路基板である。Next, a specific example of the present invention using this anisotropic conductive rubber sheet is shown in FIG. In FIG. 2, 4 is a circuit board on which lead wires 5 are formed.
この回路基板は、ガラスエポキシの様なプラスチック基
板でも良いし、またガラスあるいは石英の様な透明基板
でもよい。リードＩＩ！５は、金メッキされた鋼あるい
はニッケルクロムのリード線でもよいし、また５ｎＯ１
＊工ｎ、０．あるいは工ＴＯ等の透明導電膜からなるリ
ード線でもよい０図中の６は、本発明のポイントとなる
枠である。この枠の目的は、回路基板上′のリード線と
、ＩＯチップ上のポンディングパッドとの位置合せを容
易にするためと、この枠により、工ｄチップ上から常に
圧力を加え、ＩＣチップ下の異方性導電ゴムシートを常
に加圧の状態にして接触の信頼性を高めるところにある
。この枠は金属製でもよいし、また型成形したプラスチ
ックでもよい、またこの位置合せ用の枠は、位置合せを
した状態であらかじめ回路基板へ固定しておく。７は異
方性導電ゴムシート、８は工０チップである。９は工０
チップ上のポンディングパッドであり、通常はアルミニ
ウムが用いられている。しかし前述した様に、異方性導
電ゴムとの接触抵抗を下げるには、表面を金の層にする
か、あるいはその他の安定な金属層かあるいは８ｎ０１
．ニー、０１等の膜にすることが必要である。This circuit board may be a plastic substrate such as glass epoxy, or a transparent substrate such as glass or quartz. Lead II! 5 may be a gold-plated steel or nickel chromium lead wire, or may be a 5nO1 lead wire.
*Eng.n, 0. Alternatively, a lead wire made of a transparent conductive film such as TO may be used. 6 in Figure 0 is a frame that is the key point of the present invention. The purpose of this frame is to facilitate the alignment between the lead wires on the circuit board and the bonding pads on the IO chip, and to constantly apply pressure from above the IC chip to the bottom of the IC chip. The purpose of this is to keep the anisotropic conductive rubber sheet under pressure at all times to increase contact reliability. This frame may be made of metal or molded plastic, and this alignment frame is previously fixed to the circuit board in an aligned state. 7 is an anisotropic conductive rubber sheet, and 8 is a zero chip. 9 is engineering 0
A bonding pad on a chip, usually made of aluminum. However, as mentioned above, in order to lower the contact resistance with the anisotropic conductive rubber, the surface should be covered with a gold layer, or some other stable metal layer, or 8n01
．． It is necessary to use a film of Knee, 01, etc.
第２図（＆）は、第２図（ａ）を上方から見た枠の外観
図である。枠の中へ、異方性導電ゴムシートを挿入後、
工０チップを７エイスダウンで入れる。FIG. 2(&) is an external view of the frame seen from above in FIG. 2(a). After inserting the anisotropic conductive rubber sheet into the frame,
Insert 0 chips with 7 aces down.
第３図はＩＯ−チツプで挿入した説明図である。FIG. 3 is an explanatory diagram inserted with an IO-chip.
工０チップの上から加圧すると、異方性導電ゴムを介し
て、回路基板上−のリード線と工０チップ上のポンディ
ングパッドが導通状態となる。この加圧は、接触の信頼
性を得るには必ず必要である。When pressure is applied from above the chip, the lead wires on the circuit board and the bonding pads on the chip become electrically connected via the anisotropic conductive rubber. This pressurization is absolutely necessary to obtain reliable contact.
第４図は、常に一定の圧力にて加圧する方法を示す実施
例である。すなわち、非加圧の状態で、１０チツプの高
さが、枠の高さよりもΔｙ１ｍｌ突き出す様に設計すれ
ばよい。このΔνは、枠６上から図中の１０で示す様な
ふたを用いて押えることにより、異方性導電ゴムの変形
となり、接触の信頼性が大きく向上する。FIG. 4 is an embodiment showing a method of pressurizing at a constant pressure. That is, the design may be such that the height of the 10 chips protrudes Δy1ml beyond the height of the frame in the non-pressurized state. By suppressing this Δν from above the frame 6 using a lid as shown by 10 in the figure, the anisotropic conductive rubber is deformed and the reliability of contact is greatly improved.
回路基板上の位置合せ用の枠は、回路基板へ固定する時
にあらかじめ位置合せして固定しなければならない。す
なわち、ＩＣチップを枠内へ挿入した時、工０チップ上
のポンディングパッドとリード線が導電する様に位置合
せが必要である。一般の工０チップのポンディングパッ
ドは、−辺が約１００μ輌、間隔が約１００μ情である
ため、位置合せ精度は±１０μ愼から±２０μ慣程度が
必要である０回路基板へ枠を固定するための位置合せは
任意の方法にて簡単に行なうことが出来る。The alignment frame on the circuit board must be aligned and fixed in advance when it is fixed to the circuit board. That is, when the IC chip is inserted into the frame, it must be aligned so that the bonding pads on the chip and the lead wires are electrically conductive. The bonding pad of a general 0-chip has a negative side of about 100μ and a spacing of about 100μ, so alignment accuracy requires ±10μ to ±20μ. Fixing the frame to the circuit board The alignment for this purpose can be easily performed using any method.
一番むづかしい所は、工０チップと枠の位置合せ・１．
１
である。本発明におけるこの問題の解決策を第５図に示
す。すなわち、工０チップは、ダイシングソーを用いて
工０チップの厚さの約２／３〜３／４まで溝をつけてク
ラッキングする。この溝の位置精度は前記した±１０μ
愼から±２０μ愼の精度内には十分大る。また枠は、プ
ラスチックの型成形で製造すれば、±１０μ輌以内には
簡単に入るので、第５図中のΔ２は１０μ惜から２０μ
領の範囲に押え込むことは非常に容易である。したがっ
て、この方法を用いることにより、工０チップ上に、多
数のポンディングパッドがある場合においても、全端子
の接触が信頼性よく得られる。The most difficult part is aligning the 0 chip and the frame.1.
It is 1. A solution to this problem in the present invention is shown in FIG. That is, the No. 0 chip is cracked using a dicing saw by making a groove to about 2/3 to 3/4 of the thickness of the No. 0 chip. The positional accuracy of this groove is ±10μ as mentioned above.
The accuracy is sufficiently large to within ±20 μm from the desired value. Also, if the frame is manufactured by plastic molding, it will easily fit within ±10μ, so Δ2 in Figure 5 is 10μ or less to 20μ.
It is very easy to keep it within the territory. Therefore, by using this method, even if there are a large number of bonding pads on a chip, reliable contact between all terminals can be obtained.
第５図中において、１１は段付きの枠であり、１２はダ
イシングツにて切断されたＩＣチップである。In FIG. 5, 11 is a stepped frame, and 12 is an IC chip cut with a dicing tool.
第６図は本発明による他の実施例を示す。第６図におい
ては図中の１３にて示す如く、異方性導電ゴムシートの
中央部を穴あけした物を用いる。FIG. 6 shows another embodiment according to the invention. In FIG. 6, as shown at 13 in the figure, an anisotropic conductive rubber sheet with a hole punched in the center is used.
この実施例の目的は、工０チップの能動領域（トランジ
スタ等が形成された領域）に異方性導電ゴ□
ムシート中の導電体が接触して電気的に回路を破壊する
のを防止するところにある。The purpose of this embodiment is to prevent the conductor in the anisotropic conductive rubber sheet from coming into contact with the active area (area where transistors, etc. are formed) of the chip and electrically destroying the circuit. It is in.
第７図は本発明による他の実施例を示す。この実施例に
おいては、ＩＣチップ上のボンディングパット部にバン
プ１４が形成されている。このバンプは、高さが２〜５
０μ渭程度あればよい。このバンプの部分に接触した異
方性導電ゴムシートのみが加圧されるため、ＩＣチップ
へのダメージも少なく、接触の信頼性も高い。FIG. 7 shows another embodiment according to the invention. In this embodiment, bumps 14 are formed on bonding pads on the IC chip. This bump has a height of 2 to 5
It is sufficient if it is about 0μ. Since only the anisotropic conductive rubber sheet in contact with the bump is pressurized, there is little damage to the IC chip and the reliability of the contact is high.
第８図は、本発明によるＩＣチップの実装構造を液晶表
示パネル駆動用のドライバエ０の実装へ適用した場合の
説明図である。図中の１５は下側基板、１６は透明な上
側基板である。１７及び１８が本発明による実装構造を
有するドライバ１０チツプである。１９はシール剤であ
る。この実施例においては回路基板として透明基板を用
いるため、位置合せが容易に出来ること。また液晶表示
パネルの液晶駆動電極として用いた透明導電膜あるいは
金−ニクロム膜等がそのまま工Ｃチップ接続用のリード
線として利用出来るところに大きな特徴がある。FIG. 8 is an explanatory diagram when the IC chip mounting structure according to the present invention is applied to mounting a driver area 0 for driving a liquid crystal display panel. In the figure, 15 is a lower substrate, and 16 is a transparent upper substrate. 17 and 18 are driver 10 chips having a mounting structure according to the present invention. 19 is a sealant. In this embodiment, since a transparent substrate is used as the circuit board, alignment can be easily performed. Another great feature is that the transparent conductive film or gold-nichrome film used as the liquid crystal drive electrode of the liquid crystal display panel can be used as is as a lead wire for connecting the chip.
本発明は、以上多くの実施例において説明した如く、異
方性導電ゴムシートを用いた、構造が簡単な工０チップ
実装構造に関するものであり、大きな効果は、実装コス
トの低減にある。また本発明の実装構造においては、実
装後、工０チップの不良が見つかった場合においても容
易にＩＣチップを交換出来るところにある。当然モール
ドして固定することも可能である。As described in the many embodiments above, the present invention relates to a simple, zero-chip mounting structure using an anisotropic conductive rubber sheet, and its major effect lies in the reduction of mounting costs. Further, in the mounting structure of the present invention, even if a defective chip is found after mounting, the IC chip can be easily replaced. Of course, it is also possible to fix it by molding.
異方性導電ゴムシート中の導電体の密度は、工０チップ
上のポンディングパッドの面積が１００μ憫平方である
ことを考えると、１平方センチメートル当り１００〜１
００００個程度が適当である。The density of the conductor in the anisotropic conductive rubber sheet is 100 to 1 per square centimeter, considering that the area of the bonding pad on the chip is 100μ square.
Approximately 0,000 pieces is appropriate.
第１図（ａ）〜（ａ）は本発明にて用いる異方性導電ゴ
ムシートを説明する図。
第２図〜第７図は、本発明によるＩＣチップの実装の実
施例の説明図。
第８図は、本発明による工０チップ実装を、液晶表示パ
ネルのドライバＩＣの実装に適用した場合の説明図。
１・・・・・・異方性導電ゴムシート
２・・・・・・母材ゴム
３・・・・・・導電体
４・・・・・・回路基板
５・・・・・・リード線
６・・・・・・位置合せ用の枠
７・・・・・・興方性導電ゴムシート
８・・・・・・工０チップ
９・・・・・・ポンディングパッド
１０・・・・・・押え板
１１・・・・・・段付き枠
１２・・・・・・グイシングツ−を用いて切断したＩＣ
チップ
１３・・・・・・中央に穴があいた異方性導電ゴムシー
ト１４・・・・・・バンプ
１５・・・・・・液晶パネルの下側基板１６・・・・・
・液晶パネルの上側基板１７・・・・・・実装されたド
ライバエ０チツプ１８ ・・・・・・
１９・・・・・・シール剤
第１図
第３図
第５図FIGS. 1(a) to 1(a) are diagrams illustrating an anisotropic conductive rubber sheet used in the present invention. FIGS. 2 to 7 are explanatory diagrams of examples of mounting an IC chip according to the present invention. FIG. 8 is an explanatory diagram when the zero-chip mounting according to the present invention is applied to mounting a driver IC of a liquid crystal display panel. 1... Anisotropic conductive rubber sheet 2... Base rubber 3... Conductor 4... Circuit board 5... Lead wire 6... Frame for alignment 7... Orthotropic conductive rubber sheet 8... Process 0 chip 9... Ponding pad 10...・・Press plate 11 ・・・Stepped frame 12 ・・・IC cut using the guiding tool
Chip 13... Anisotropic conductive rubber sheet with a hole in the center 14... Bump 15... Lower substrate of liquid crystal panel 16...
- Upper substrate 17 of the liquid crystal panel...Mounted driver bay 0 chip 18...19...Sealant Fig. 1 Fig. 3 Fig. 5
Claims (1)
た異方性導電ゴムシートを用いた半導体集積回路の実装
構造において、半導体集積回路のポンディングパッド位
置に対応したリード線が形成された回路基板と、該半導
体集積回路の間に該異方性導電ゴムシートをはさむ実装
構造であり、かつ該回路基板上には、あらかじめ該回路
基板と該半導体集積回路の位置合せ用の枠が設けられて
いることを特徴とする半導体集積回路の実装構造。 （２）位置合せ用の枠内に半導体集積回路を挿入後、異
方性導電ゴムシートが厚さ方向に歪んだ状態で、該半導
体集積回路基板を該粋に固定することを特徴とする特許
請求の範囲第一項記載の半導体集積回路の実装構造。 （３） 回路基板は、透明基板であることを特徴とす
る特許請求の範囲第一項記載の半導体集積回路の実装構
造。 （４）回路基板は、液晶表示パネルを構成する基板の一
部であることを特徴とする特許請求の範囲第−項及び第
三項記載の半導体集積回路の実装構造。 （５）′回路基板上のリード線は、液晶表示パネル上の
表示電極形成工程時に同時に形成されるリード線である
ことを特徴とする特許請求の範囲第−項及び第四項記載
の半導体集積回路の実装構造。 （６）異方性導電ゴムシート中の導電体は一平方センチ
メートル当り１００〜１００００個含まれていることを
特徴とする特許請求の範囲第一項記載の半導体集積回路
の実装構造。 （７）半導体集積回路上のｌンディングバッド電極は、
表面が金、ネサ膜あるいはポリシリコンであることを特
徴とする特許請求の範囲第一項記載の半導体集積回路の
実装構造。 （８１半導体集積回路上のポンディングパッド部は、バ
ンプが形成されていることを特徴とする特許請求の範囲
第一項記載の半導体集積回路の実装構造。 （９）異方性導電ゴムシートは、半導体集積回路の能動
素子領域に接触しない様な形状にパンチングされている
ことを特徴とする特許請求の範囲第一項記載の半導体集
積回路の実装構造。[Scope of Claims] (1) In a semiconductor integrated circuit mounting structure using an anisotropic conductive rubber sheet in which conductors are oriented in countless numbers in the thickness direction of the sheet, It has a mounting structure in which the anisotropic conductive rubber sheet is sandwiched between a circuit board on which lead wires are formed and the semiconductor integrated circuit, and the positions of the circuit board and the semiconductor integrated circuit are marked on the circuit board in advance. A mounting structure for a semiconductor integrated circuit, characterized in that a frame for alignment is provided. (2) A patent characterized in that after a semiconductor integrated circuit is inserted into an alignment frame, the semiconductor integrated circuit board is properly fixed in a state where the anisotropic conductive rubber sheet is distorted in the thickness direction. A mounting structure for a semiconductor integrated circuit according to claim 1. (3) The semiconductor integrated circuit mounting structure according to claim 1, wherein the circuit board is a transparent substrate. (4) The semiconductor integrated circuit mounting structure according to claims 1 to 3, wherein the circuit board is a part of a substrate constituting a liquid crystal display panel. (5)' A semiconductor integrated circuit according to claims 1 to 4, wherein the lead wires on the circuit board are lead wires formed simultaneously during the process of forming display electrodes on the liquid crystal display panel. Circuit implementation structure. (6) The semiconductor integrated circuit mounting structure according to claim 1, wherein the anisotropic conductive rubber sheet contains 100 to 10,000 conductors per square centimeter. (7) The landing pad electrode on the semiconductor integrated circuit is
A mounting structure for a semiconductor integrated circuit according to claim 1, wherein the surface is made of gold, Nesa film, or polysilicon. (81) The mounting structure of a semiconductor integrated circuit according to claim 1, characterized in that the bonding pad portion on the semiconductor integrated circuit is formed with a bump. (9) The anisotropic conductive rubber sheet is A mounting structure for a semiconductor integrated circuit according to claim 1, characterized in that the structure is punched in a shape that does not contact the active element region of the semiconductor integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56113828A JPS5815243A (en) | 1981-07-20 | 1981-07-20 | Mounting structure for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56113828A JPS5815243A (en) | 1981-07-20 | 1981-07-20 | Mounting structure for semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5815243A true JPS5815243A (en) | 1983-01-28 |
Family
ID=14622058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56113828A Pending JPS5815243A (en) | 1981-07-20 | 1981-07-20 | Mounting structure for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5815243A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61186061A (en) * | 1985-02-13 | 1986-08-19 | Fuji Xerox Co Ltd | Device for driving contact type image sensor or thermal head or the like |
| JPS62101042A (en) * | 1985-10-28 | 1987-05-11 | Minolta Camera Co Ltd | Loading structure to substrate of ic chip |
| JPH04369847A (en) * | 1990-08-30 | 1992-12-22 | Micron Technol Inc | Semiconductor assembly |
| US5563076A (en) * | 1993-09-29 | 1996-10-08 | Fuji Electric Co., Ltd. | Process for adjusting heights of plural semiconductor devices on a circuit board |
| EP1816904A1 (en) * | 2006-02-06 | 2007-08-08 | Lih Duo International Co., Ltd. | Memory module with rubber spring connector |
| JP2015065255A (en) * | 2013-09-25 | 2015-04-09 | 沖電気工業株式会社 | Photoelectric fusion module |
| US9139856B2 (en) | 2008-03-12 | 2015-09-22 | Tata Chemicals Ltd. | Process for production of galactooligosaccharides (GOS) |
| CN109923739A (en) * | 2016-11-09 | 2019-06-21 | 阿莫技术有限公司 | Functional contact device |
| CN110392492A (en) * | 2019-08-09 | 2019-10-29 | 苏州浪潮智能科技有限公司 | A kind of bed die component and its application method for circuit board crimping processing procedure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51100679A (en) * | 1975-03-03 | 1976-09-06 | Suwa Seikosha Kk |
-
1981
- 1981-07-20 JP JP56113828A patent/JPS5815243A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51100679A (en) * | 1975-03-03 | 1976-09-06 | Suwa Seikosha Kk |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61186061A (en) * | 1985-02-13 | 1986-08-19 | Fuji Xerox Co Ltd | Device for driving contact type image sensor or thermal head or the like |
| JPS62101042A (en) * | 1985-10-28 | 1987-05-11 | Minolta Camera Co Ltd | Loading structure to substrate of ic chip |
| JPH04369847A (en) * | 1990-08-30 | 1992-12-22 | Micron Technol Inc | Semiconductor assembly |
| US5563076A (en) * | 1993-09-29 | 1996-10-08 | Fuji Electric Co., Ltd. | Process for adjusting heights of plural semiconductor devices on a circuit board |
| EP1816904A1 (en) * | 2006-02-06 | 2007-08-08 | Lih Duo International Co., Ltd. | Memory module with rubber spring connector |
| US9139856B2 (en) | 2008-03-12 | 2015-09-22 | Tata Chemicals Ltd. | Process for production of galactooligosaccharides (GOS) |
| JP2015065255A (en) * | 2013-09-25 | 2015-04-09 | 沖電気工業株式会社 | Photoelectric fusion module |
| CN109923739A (en) * | 2016-11-09 | 2019-06-21 | 阿莫技术有限公司 | Functional contact device |
| CN110392492A (en) * | 2019-08-09 | 2019-10-29 | 苏州浪潮智能科技有限公司 | A kind of bed die component and its application method for circuit board crimping processing procedure |
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