JPS62101042A - Loading structure to substrate of ic chip - Google Patents

Loading structure to substrate of ic chip

Info

Publication number
JPS62101042A
JPS62101042A JP24245985A JP24245985A JPS62101042A JP S62101042 A JPS62101042 A JP S62101042A JP 24245985 A JP24245985 A JP 24245985A JP 24245985 A JP24245985 A JP 24245985A JP S62101042 A JPS62101042 A JP S62101042A
Authority
JP
Japan
Prior art keywords
chip
substrate
adhesive sheet
sheet
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24245985A
Other languages
Japanese (ja)
Inventor
Kiyoshi Seigenji
清玄寺 潔
Shunji Oku
奥 俊二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Minolta Co Ltd
Original Assignee
Minolta Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Minolta Co Ltd filed Critical Minolta Co Ltd
Priority to JP24245985A priority Critical patent/JPS62101042A/en
Publication of JPS62101042A publication Critical patent/JPS62101042A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29499Shape or distribution of the fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Conductive Materials (AREA)

Abstract

PURPOSE:To improve the workability of a loading process to a substrate of an IC chip by interposing anisotropic conductive adhesives between the IC chip and the substrate and bonding both the IC chip and the substrate. CONSTITUTION:A conductor pattern L on a circuit substrate B is covered with an insulating coverlet K. The coverlet K is removed only in a section connected to an IC in the conductor pattern. An IC pattern on an IC chip is covered with a passivation 10 (an insulating film) with the exception of a pad F section for connection. An insulating coat 20 is applied onto the circumferential side surface of the IC chip. The peripheral section of a resin as a mother material for an anisotropic conductive adhesive sheet C is protruded by pressing, thus realizing the sealing effect of the periphery of the IC.

Description

【発明の詳細な説明】 イ、産業上の利用分野 本発明はICチップを回路基板に実装する場合の接続及
び打止の方法に関する。
DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a connection and termination method when an IC chip is mounted on a circuit board.

ロ、従来の技術 従来ICチップを基板に取付ける場合、ICチップの接
続用導体パッドと基板側の導体パターンとの間を一々金
属ワイヤで接続しており、tCの封止は全く別工程で行
っていた。
B. Conventional technology Conventionally, when attaching an IC chip to a substrate, the connection conductor pads of the IC chip and the conductor pattern on the substrate side are connected with metal wires, and tC sealing is performed in a completely separate process. was.

I\1発明が解決しようとする間居点 従来、技術ではICバッ°ドと基板の導体パターンを接
続するのに金属ワイヤを用いているが、パッド等とワイ
ヤとのボンディングの諸条件は許容範囲がせまく、IC
とか基板が異ると条件も異るので、ボンディング条件の
設定がむつかしく、ワイヤを一本ずつボンディングして
行(ので能率的でなく、またtCの封止がボンディング
とは別の工程であるので、ICチップを回路基板に実装
する作業は能率が低かった。本発明はこのようなICチ
ップの回路基板への実装作業の高能率化を計ろうとする
ものである。
I\1 The problem that the invention aims to solve Conventionally, metal wires have been used to connect IC pads and conductor patterns on substrates, but the conditions for bonding between pads, etc. and wires are permissible. narrow range, IC
Since the conditions differ depending on the substrate, it is difficult to set the bonding conditions, and bonding the wires one by one is not efficient. However, the efficiency of mounting an IC chip onto a circuit board has been low.The present invention aims to improve the efficiency of mounting such an IC chip onto a circuit board.

二1問題点解決のための手段 近年異方導電性接着材シートが開発された。この材料は
相互に接着すべき二物体間にはさんで加熱加圧すること
により二物体を接着することができるシート状材料で、
しかも厚さ方向に導電性を有し、厚さと直角の方向即ち
シートの広がり方向には導電性を持たない異方導電性を
有する。
21 Means for Solving Problems Recently, an anisotropically conductive adhesive sheet has been developed. This material is a sheet-like material that can be used to bond two objects together by sandwiching them between the two objects and applying heat and pressure.
Moreover, it has anisotropic conductivity, having conductivity in the thickness direction and no conductivity in the direction perpendicular to the thickness, that is, in the direction in which the sheet spreads.

本発明は回路パターンの所定位置に上記異方導電イ↑接
着シートを介してICチップを置き、加熱加圧すること
により、一工程でICチップの回路パターンへの接続と
封止とを同時に完了するようにした。
The present invention simultaneously completes the connection and sealing of the IC chip to the circuit pattern in one step by placing the IC chip at a predetermined position of the circuit pattern via the anisotropically conductive adhesive sheet and applying heat and pressure. I did it like that.

ホ0作用 異方導電性接着シートは第1図で矢印で示すように厚さ
方向には導電性があるが、シート面と平行の方向には絶
縁体であるので、第1図に示すように二つの物体A、B
間に上記シートCをはさんで加熱加圧して二物体A、B
を接着した場合、二物体A、Bの互いに対向する導体パ
ターンa1、bl間及びa2.b2間は夫々シートCに
よって電気的に接続されるが、al、blの対及びa2
.b2の対の間はシートCの横方向の非導電性によって
絶縁されたま\である。つまり物体B側の回路パターン
bl、b2と物体A側の導体パターンat、a2とが、
AをBに接着する工程によって一度に接続されるのであ
り、A、B2物体間はシートCの接着性によって電気的
な接続の、1.rと同時に封止も完了しているのであり
、また相互接続すべき導体パターンの数2.配置、形状
等は任意であることは容易に理解されよう。
The anisotropically conductive adhesive sheet has conductivity in the thickness direction as shown by the arrow in Figure 1, but it is an insulator in the direction parallel to the sheet surface, so as shown in Figure 1. two objects A and B
Two objects A and B are made by heating and pressing the sheet C between them.
When bonding the two objects A and B, the mutually opposing conductor patterns a1 and bl and a2 . b2 are electrically connected by sheets C, but the pair of al, bl and a2
.. The pair b2 remains insulated by the lateral non-conductivity of sheet C. In other words, the circuit patterns bl, b2 on the object B side and the conductor patterns at, a2 on the object A side are
The process of gluing A to B connects them all at once, and the two objects A and B are electrically connected by the adhesive properties of sheet C. The sealing is completed at the same time as the number of conductor patterns to be interconnected. It is easily understood that the arrangement, shape, etc. are arbitrary.

へ、実施例 異方導電性接着シートは第2図に示したように合成樹脂
母材P中に導電性粒子mを分散させたもので、上下方向
に圧縮すると厚さ方向の粒子間隔が縮まり導電粒子同士
及び導電粒子と上下の加圧体とが樹脂Pの層厚方向に互
いに接触し上下の加圧体間には電気的導通が得られるが
、層の厚さと直角の方向には導電性粒子間隔は圧縮され
ないから、導電粒子同士の接触は起こらず、導電性も生
じない。導電性粒子としてはカーボン繊維(短(したも
の) 、N i、A u 、半田等の金属微粒子が用い
られ、粒子径は数十μm程度のものを主とし、数μm級
のものを混入させてもよい。接着シートの厚さは数十μ
mから100μm程度である。使用する導電性粒子の径
によって相互絶縁されているべき隣同士の導体パターン
間の間隔が決まり、粒子径10μmで導体間間隔は25
〜100μm1接着シートの厚さは20μm程度である
。ICチップの封正により耐湿効果を得るためには接着
シートは厚い方がよく通常200〜500μm程度ある
ことが望ましい。接着シートの厚さを太き(して、しか
も隣同士の導体パターン間の絶縁可能間隔を小さくする
には樹脂母材中に導電性繊維線材を厚さ方向に平行にし
て混入した第3図に示すような異方導電性接着シートが
用いられる。この図でPは樹脂、fが導電性繊維である
。導電性繊維線材としては、任意のものが用いられるが
、貴金属或は一般金属に貴金属を被覆したものを用いる
と、パッド面との電気的接触の耐久性の向上が得られ。
As shown in Fig. 2, the example anisotropically conductive adhesive sheet has conductive particles m dispersed in a synthetic resin matrix P, and when compressed in the vertical direction, the particle spacing in the thickness direction is reduced. The conductive particles and the upper and lower pressure bodies contact each other in the layer thickness direction of the resin P, and electrical continuity is obtained between the upper and lower pressure bodies, but there is no conductivity in the direction perpendicular to the layer thickness. Since the distance between the conductive particles is not compressed, contact between the conductive particles does not occur, and no conductivity occurs. As the conductive particles, carbon fibers (short ones), Ni, Au, metal fine particles such as solder are used, and the particle size is mainly about several tens of μm, but particles of several μm can be mixed in. The thickness of the adhesive sheet is several tens of microns.
It is about 100 μm from m. The spacing between adjacent conductor patterns that should be mutually insulated is determined by the diameter of the conductive particles used, and when the particle diameter is 10 μm, the spacing between the conductors is 25 μm.
~100 μm 1 The thickness of the adhesive sheet is about 20 μm. In order to obtain a moisture-resistant effect by sealing the IC chip, the thicker the adhesive sheet, the better, and it is usually desirable to have a thickness of about 200 to 500 μm. In order to increase the thickness of the adhesive sheet (and reduce the insulating distance between adjacent conductor patterns), conductive fiber wires are mixed into the resin base material parallel to the thickness direction (Fig. 3). An anisotropically conductive adhesive sheet as shown in the figure is used. In this figure, P is a resin and f is a conductive fiber. Any conductive fiber wire can be used, but precious metals or common metals can be used. If a material coated with a noble metal is used, the durability of electrical contact with the pad surface can be improved.

第6図A、Bはこの実施例に用いられ異方導電性接着シ
ートの例で、同図Aは加熱により軟化接着性を現す母材
のシートP中に導電性線材fを厚さ方向に揃えて埋設し
たもので、同図Bは樹脂シートPに導電性線材fの両端
をシート上下両面に露出させて埋設し、その表面に接着
剤層Hを設けたらのである。この接着剤層は熱可塑性樹
脂で加熱により軟化接着性を現す層を予め設けておいて
もよく、或は別のシートとして用、′αしておきICチ
ップ実装の際重ねて加熱加圧するようにしてもよく、或
はまた、実装工程で、IC表面或はシート2表面に接着
剤を塗布して加圧接着するようにしてもよい。
Figures 6A and 6B show examples of anisotropically conductive adhesive sheets used in this example, and Figure 6A shows conductive wires f placed in the thickness direction in a base material sheet P that exhibits softening adhesive properties when heated. The conductive wire f is buried in a resin sheet P with both ends thereof exposed on both the upper and lower surfaces of the resin sheet P, and an adhesive layer H is provided on the surface thereof. This adhesive layer may be prepared in advance with a layer of thermoplastic resin that exhibits adhesive properties by softening when heated, or it may be used as a separate sheet and then layered and heated and pressed when mounting the IC chip. Alternatively, in the mounting process, an adhesive may be applied to the surface of the IC or the surface of the sheet 2 and bonded under pressure.

第4図はICチップを基板上に実装した状態を示す。B
が回路基板であり、Lが基板上の導体パターンである。
FIG. 4 shows the IC chip mounted on the substrate. B
is a circuit board, and L is a conductor pattern on the board.

Kは導体パターンを覆う絶縁性のカバーレイで、導体パ
ターンのICと接続される部分だけカバーレイが除かれ
ている。ICh<ICチップでICパターンは接続用パ
ッドFの部分を除いてパッシベーション10(絶縁膜)
で覆われている。ICチップの周側面には絶縁コート2
0が塗布しである。Cが異方導電性接着シートであり、
mは導電性粒子である。接着シートの母材の樹脂は加圧
によって周辺部が盛り上りIC周囲の封止効果を実現し
ている。
K is an insulating coverlay that covers the conductor pattern, and the coverlay is removed only from the part of the conductor pattern that is connected to the IC. ICh<IC chip, the IC pattern has passivation 10 (insulating film) except for the connection pad F.
covered with. Insulating coat 2 on the circumferential side of the IC chip
0 is applied. C is an anisotropic conductive adhesive sheet,
m is a conductive particle. When pressurized, the base resin of the adhesive sheet bulges around the periphery, achieving a sealing effect around the IC.

第5図の実施例は基板BのIC取付は部が打ち抜かれて
いて、その周辺にICと接続すべき導体パターンLが配
設されている例で、異方導電性接着シートCによってI
Cと基板8間の回路接続とICCチップ全面正正が行わ
れている。
The embodiment shown in FIG. 5 is an example in which a part of the board B for mounting an IC is punched out, and a conductor pattern L to be connected to the IC is arranged around it, and an anisotropically conductive adhesive sheet C is used to attach the IC.
The circuit connection between C and the board 8 and the entire surface of the ICC chip are being corrected.

ト、効果 本発明方法は作業としてはICチップと基板との間に異
方導電性接着材を介在させて圧着するだけでICチップ
の結線と封止が完了してしまうので・ICチップの基板
への搭載工程の作業性が著しく向」ニする。
G. Effect: The method of the present invention completes the connection and sealing of the IC chip by simply interposing an anisotropically conductive adhesive between the IC chip and the substrate and crimping it. The workability of the loading process is significantly improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明方法を説明する厚さ方向に拡大した断面
図、第2図は異方導電性接着シートの断面拡大図、第3
図は他の型の異方導電性接着シートの断面拡大図、第4
図は本発明の一実施例の断面図、第5図は本発明の他の
一実施例の断面図、第6図は更に他の型の異方導電性接
着シートの断面拡大図である。 代理人  弁理士 縣  浩 介 III図 Δ jlZ図
FIG. 1 is an enlarged cross-sectional view in the thickness direction for explaining the method of the present invention, FIG. 2 is an enlarged cross-sectional view of an anisotropically conductive adhesive sheet, and FIG.
The figure is an enlarged cross-sectional view of another type of anisotropically conductive adhesive sheet.
5 is a cross-sectional view of another embodiment of the present invention, and FIG. 6 is an enlarged cross-sectional view of yet another type of anisotropically conductive adhesive sheet. Agent Patent Attorney Hiroshi Agata III Figure Δ jlZ Figure

Claims (1)

【特許請求の範囲】[Claims]  ICチップを同ICチップが装着される基板上に、夫
々の相互接続されるICパッド及び導体パターンを対向
させ、上記ICチップと基板との間に異方導電性接着材
を介在させて両者を接着することを特徴とするICチッ
プの基板への搭載構造。
An IC chip is mounted on a board on which the IC chip is mounted, with the IC pads and conductor patterns to be interconnected facing each other, and an anisotropically conductive adhesive is interposed between the IC chip and the board to bond them together. A structure for mounting an IC chip onto a substrate, which is characterized by adhesive bonding.
JP24245985A 1985-10-28 1985-10-28 Loading structure to substrate of ic chip Pending JPS62101042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24245985A JPS62101042A (en) 1985-10-28 1985-10-28 Loading structure to substrate of ic chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24245985A JPS62101042A (en) 1985-10-28 1985-10-28 Loading structure to substrate of ic chip

Publications (1)

Publication Number Publication Date
JPS62101042A true JPS62101042A (en) 1987-05-11

Family

ID=17089406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24245985A Pending JPS62101042A (en) 1985-10-28 1985-10-28 Loading structure to substrate of ic chip

Country Status (1)

Country Link
JP (1) JPS62101042A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62190344U (en) * 1986-05-26 1987-12-03
JPH0329207A (en) * 1988-12-05 1991-02-07 Hitachi Chem Co Ltd Composition for circuit connection and connection method and connection structure of semiconductor chip using the composition

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5815243A (en) * 1981-07-20 1983-01-28 Seiko Epson Corp Mounting structure for semiconductor integrated circuit
JPS60100441A (en) * 1983-11-05 1985-06-04 Mitsubishi Electric Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5815243A (en) * 1981-07-20 1983-01-28 Seiko Epson Corp Mounting structure for semiconductor integrated circuit
JPS60100441A (en) * 1983-11-05 1985-06-04 Mitsubishi Electric Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62190344U (en) * 1986-05-26 1987-12-03
JPH0329207A (en) * 1988-12-05 1991-02-07 Hitachi Chem Co Ltd Composition for circuit connection and connection method and connection structure of semiconductor chip using the composition

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