JPH04369847A - Semiconductor assembly - Google Patents

Abstract

PURPOSE: To provide a semiconductor assembly utilizing an elastomer sheet having anisotropic conductivity as parts of an interconnection between at least one die (wafer) and a plurality of externally accessible edge part conductors. CONSTITUTION: A semiconductor assembly includes at least one die 10 having substantially flat first and second engaging surfaces and an outer side edge part defining a die configuration. A base part with an opening formed and receives a die. A mutual connection plate 15 has at least one substantially flat engaging surface facing to the substantially flat first engaging surface of the die received in the substrate opening. At least one of conductive pads 12, 16 on the engaging surface of the flat plate is spatially aligned or positioned with respect to a corresponding conductive pad on the first engaging surface of the die. A sheet of an elastomer material 20 having anisotropic conductivity resides between the first engaging surface of the die and the engaging surface of the mutual connection flat.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention applies to semiconductor die (wafer)
Regarding packaging. The present invention uses an anisotropically conductive elastomer sheet to attach to one or more dies (wafers).
and a plurality of externally accessible edge conductors.

0002

BACKGROUND OF THE INVENTION Semiconductor assemblies that include one or more die are typically soldered or otherwise connected to an associated printed circuit board to provide the necessary electrical contacts or connectors. requires individual packaging for each die. The electronics industry's search for new connector formats is driven by high contact pad densities, high frequency operation,
Driven by the need for connections with reduced size, low cost, and ease of replacement.

0003

SUMMARY OF THE INVENTION The present invention arose from an effort to redesign the single inline memory module (SIMM). In such modules, a plurality of integrated storage circuits are interconnected on a substrate containing traces leading to conventional edge conductors, where the module is connected to a motherboard in a computer or other special application. allows it to be fitted into the Current packaging requirements for integrated circuits include placing the die in individual packages with external contacts. The package must be securely attached to the printed circuit board, and the integrated circuit contacts must be soldered to make interconnections to the printed circuit board pads and traces.

A general example of current SIMM technology is shown in FIG. A number of packaged storage integrated circuits 27 are mounted in-line along supporting printed circuit board 13. Integrated circuit contacts 28 are soldered to traces 29 on board 13 and routed to a row of edge conductors 14. Production of such modules not only requires assembly of the plates shown in FIG. 2, but also requires packaging and assembly of the individual integrated circuits themselves. Fabrication of SIMMs requires several steps to lock and connect the integrated circuit and circuitry on circuit board 13. Replacing the replacement circuit 27 within the completed assembly is not only difficult but time consuming.

[0005]

SUMMARY OF THE INVENTION Although not limited to SIMM applications, the present invention provides a method for each die having conductive pads along one surface and a corresponding one aligned in registration with the conductive pads of the die. Anisotropically conductive elastomeric sheets are utilized to form multiple electrical paths between interconnect plates having conductive pads. The pads and interconnect plates compress the intervening sheets of elastomeric material to complete the desired electrical connections. The interconnect plate may include traces leading to conventional edge connector elements. The resulting physical module containing these dies is relatively simple in construction. It does not require packaging of individual dies and facilitates replacement of dies within a module when this is required.

The present invention can be applied to multi-chip assemblies of more than one type of semiconductor die. Dies can be utilized as separate units or in wafer form. In the context of this document, the term "die" is intended to encompass individual chips singulated from an entire wafer as well as from an entire wafer of integrated circuit configurations. In the context of the present invention, large numbers of die can be assembled in high density packaging without wire bonding, tape autobonding or other conventional interconnection techniques applied to such die. The present invention includes a novel structure for aligning the die with respect to the interconnect plate.

A preferred embodiment of the invention is illustrated in the accompanying drawings.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In accordance with the present invention, a semiconductor assembly has substantially planar first and second engagement surfaces, a defined thickness therebetween, and defines a die outer shape. a die having an outer edge and a first engagement surface including one or more conductive pads; and a base having an aperture formed therein, the base aperture having an aperture shape complementary to the die outer shape. a peripheral edge defining a base aperture, the aperture being dimensioned to receive and engage the die, the die being so received within the base aperture, the aperture edge engaging the die edge; a base for spatially fixing the die in a selected orientation in a plane parallel to the first planar engagement surface of the die, and facing the first planar engagement surface of the die received within the base opening; an interconnection plate having at least one substantially planar engagement surface, the planar engagement surface of the plate having one or more conductive pads and conductive traces formed thereon; an interconnect plate with at least one conductive pad on the flat engagement surface of the sheet spatially aligned with one conductive pad on the first engagement surface of the die received within the base aperture; a sheet of anisotropically conductive elastomeric material having cross-thickness conductivity between the first interengaging surface of the die and the interengaging surface of the interconnect plate; a sheet interposed between the base and the interconnect plate and at least one conductive pad of the die through the sheet of elastomeric material having anisotropic conductivity;
and clamping means for engaging the substrate and interconnect plate to urge the die and plate toward each other in spatial alignment so as to conductively engage the two conductive pads.

The invention will first be explained in principle with reference to FIGS. 1 and 12-15, which schematically illustrate the basic elements of an assembly according to the invention. The packaged semiconductor assembly shown in these figures includes a die 10 having a substantially planar first engagement surface 60 and a substantially planar second engagement surface 61 (FIGS. 13 and 14). designed and have thicknesses defined therebetween. Die 10 has an outer edge 62 that defines the outer shape of the die. In the illustrated embodiment, the outer shape is square or rectangular in shape. 1st
The engagement surface 60 of includes one or more conductive pads, with only a single conductive pad 12 shown in FIG. 12 for clarity of the drawing.
~Illustrated in FIG. Die 10 can be any desired type of semiconductor die. It can be a single unit. More generally, the packaged assembly includes a plurality of dies 10, which can be identical to each other or can include a variety of integrated circuits and/or components and/or shapes. .

Dies 10 are mounted within a support housing or base 11 having respective apertures 63 formed therein. The base opening 63 has a peripheral edge 64 (FIGS. 13 and 14).
, the peripheral edge defining the shape of the aperture 63 complementary to the outer shape of the die 10 defined by the edge 62 of the die. Opening edge 64 is not visible in FIG. 12 due to the degree of magnification. Note that opening 63 is sized to receive and engage die 10 in a snug fit. In particular, the die 10 is received within the base aperture 63 such that the aperture edge 64 engages the die edge 62, positioning the die in a selected orientation in a plane parallel to the first planar engagement surface 60 of the die. to fix it spatially. The preferred fit is large enough to receive the die, but sufficiently snug to prevent appreciable movement of the die 10 within the opening 63.

More particularly, base 11 includes a first planar engagement surface 70 and an opposing second planar engagement surface 72 . Base opening 63 is in the form of a recess formed into base 11 from base first flat engagement surface 70 . The recess has a flat recess bottom surface 75 (FIG. 13) that defines a recess or opening depth approximately equal to the thickness of die 10 (FIG. 15). The die 10 is received within the recess or aperture 63, the die second flat engagement surface 61 is received against the flat recess bottom surface 75, and the die first flat engagement surface 60 is received against the base flat recess bottom surface 75. It is substantially coplanar with the first flat engagement surface 70 (FIG. 15).

The packaged semiconductor assembly also includes an interconnect plate 15. Plate 15 has opposed planar first engagement surfaces 66 and second engagement surfaces 67 . First planar engagement surface 66 faces first planar engagement surface 60 of die 10 received within base opening 63 . The first planar engagement surface 66 of the plate has a region 69 (FIG. 1) spatially aligned with the die 10. Area 6
9 has one or more conductive pads 16 and associated conductive traces 17. As is apparent from the drawings, the conductive pad 16 shown in FIG. 1 on the flat engagement surface 66 of the plate.
are spatially aligned with conductive pads 12 on first engagement surface 60 of die 10 received within aperture 63 . The conductive traces 17 can be led from one area to another in the form of a conventional pattern of edge connectors 18 (FIG. 1) or to input/output connections. Portions of traces 17 may be covered with a layer of electrically insulating material 19 (FIG. 12) to prevent short circuits along their respective paths.

Interposed between die 10 and plate 15 is a sheet of anisotropically conductive elastomeric material, indicated generally at 20. Elastomeric sheet 20 is a commercially available product. It is conductive across its thickness and non-conductive across its width and length. This type of material is commonly known as "elastomeric uniaxial conductive interconnect" or ECPI. Examples of suitable interconnect materials between die 10 and plate 15 are given in "New Z-Direction Anisotropic Conductive Composite Materials" by Jin et al. in the November 15, 1988 issue of Applied Physics, pages 6008-6010. , which is incorporated herein by reference. Other available materials with equivalent conductive properties can be substituted for the specifically described materials.

In the illustrated embodiment, the elastomeric sheet 20 is comprised of parallel columns of conductive spheres 25 separated by elastomeric insulating material 26 (FIG. 12).
. Each column or chain of spheres 25 forms a conductive path through insulating material 26, for example electrically interconnecting conductive pads 12 and 16. The density of the columns of spheres 25 should be such that there are multiple conductive paths across each pair of spatially aligned pads 12,16.

Clamping means are provided for engaging the base 11 and the interconnect plate 15 to force the die 10 and the plate 15 toward each other in spatial alignment and to provide anisotropic electrical conductivity. At least one conductive pad 12 of the die 10 is conductively engaged with at least one conductive pad 16 of the interconnect plate 15 through a sheet 20 of elastomeric material. In other words, the elastomeric sheet 20 is preferably compressed between the die 10 and the plate 15 so as to absorb small surface variations of the opposing surfaces that come into contact with it. The resulting electrical connection is routed through traces 17 to conductors 18, which can be attached to an external circuit board or to other electronic devices (not shown) by conventional connector techniques. In the illustrated embodiment, the clamping means includes a pair of rigid outer backing plates 22. One plate 22 overlies the second flat engagement surface 67 of the interconnect plate 15 and the other plate overlies the flat engagement surface 72 of the base 11. Means for compressing the plates 12 inwardly relative to each other could be provided by screws or other clamps, as will become clear from the subsequent discussion of other embodiments.

3-5 illustrate the application of the present invention to the production of single in-line memory module (SIMM) electronic storage devices. Such modules are used as storage expansion boards in personal computers. They include a plurality of memory circuits attached to a supporting circuit board for attachment to the mother board by conventional edge conductors. A single in-line storage module constructed in accordance with this disclosure includes substrate 36 (
(corresponding to the interconnect plate described above) and an overlapping pressure plate 30 (corresponding to the substrate described above) having a recessed opening 37 formed therein. Pressure plate 30 covers all but one edge of board 36, exposing edge conductors 34 formed on board 36 for interconnection to an associated circuit board or conventional connector (not shown). Leave it as is. Rows of dies 31 containing desired storage circuitry components can be individually placed within complementary recesses 37 formed across one engagement surface of pressure plate 30. An interposed elastomeric interconnect is illustrated at 33. Appropriate fasteners (not shown) could couple pressure plate 30 and substrate 36 to apply appropriate compressive forces to interconnect 33. The entire module can be easily constructed without soldering or bonding contacts. Die 31 can be supported within complementary recesses 37 without permanent fixtures and can be easily interchanged for testing, repair or replacement.

FIGS. 6 and 7 show an alternative structure. In this assembly, base interconnect plate 40 is provided with edge conductors 41 . The pressure plate has three components: a frame 42;
, a perforated insert 43 and a rigid backing sheet or plate 44. Perforated insert 43 includes a hole or aperture 79 formed through insert 43 between its respective opposing planar engagement surfaces. The various holes 79 are complementary in shape and size to each individual die 47 positioned therein. The thickness of the substrate 43 is approximately the same as the thickness of each die. An elastomeric interconnect 45 is interposed between die 47 positioned within perforated insert 43 and supporting interconnect substrate 40 . Substrate 40 includes conductive pads and traces (not shown) leading to edge connectors. A fastener in the form of a bolt 46 (Fig.
) structurally connects the components of the assembly, maintains them in alignment with each other, and applies compressive force to the elastomeric interconnect 45.

FIGS. 8-11 illustrate embodiments that utilize the entire wafer. This is particularly applicable to applications requiring a large number of memory circuit chips, but can be applied to other types of chips. The stacked semiconductor assembly shown in FIG. 8 includes a circuit wafer 5 that includes a number of separate chips 54 and opposed interconnect plates in the form of an integral wafer 51.
0 and initially includes the conductive paths and wires leading to the edge conductor 52. Wafer flat 5 across wafer 50
5 is cut short to leave the edge connector 52 exposed for subsequent assembly. Also, wafer 5
1 may optionally include a die and/or circuit device.

Two wafers 50, 51 are mounted on opposite sides of an elastomeric interconnect 53 and supported within a recess in an outer backing plate 56 (FIG. 8). In this embodiment, individual handling of each chip 54 is not required. High density mounting of storage chips in usable module assemblies can be achieved at low cost.

The invention has been described in somewhat specific language with respect to structural features. However, it is to be understood that the invention is not limited to the specific features shown and described, since the instrumentalities and structures disclosed herein constitute preferred forms of carrying out the invention. The invention is therefore claimed in any of its forms and modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

[Brief explanation of the drawing]

FIG. 1 is an exploded schematic perspective view of the basic elements of the invention.

FIG. 2 is a schematic plan view of the prior art single inline storage module (SIMM) described in the Prior Art section above.

FIG. 3 is an exploded perspective view of a SIMM made in accordance with the present invention.

FIG. 4 is an exploded elevational view of the SIMM of FIG. 3.

[Figure 5] Assembled S cut at the line 5-5 in Figure 3
An enlarged cross-sectional view of the IMM.

FIG. 6 is an exploded perspective view of a second embodiment of the invention.

7 is an enlarged cross-sectional view of the assembled components of FIG. 6 taken along line 7-7 of FIG. 6;

FIG. 8 is an assembled side view of the third embodiment.

FIG. 9 is a plan view of the structure of FIG. 8;

FIG. 10 is a cross-sectional view taken along line 10-10 of FIG. 8.

FIG. 11 is a plan view of a wafer with an integrated wafer scale.

FIG. 12 is an enlarged exploded cross-sectional view showing the basic elements of the semiconductor assembly of FIG. 1;

13 is an enlarged exploded cross-sectional view showing the basic elements of the conductor assembly of FIG. 1, but not as enlarged as FIG. 12;

FIG. 14 is an enlarged plan view of a single die and substrate assembled into the assembly of FIGS. 1, 12, and 13;

FIG. 15 is an enlarged cutaway sectional view of some portions of the enlarged views of FIGS. 1, 12, and 13;

[Explanation of symbols]

10 die 11 housing or base
12, 16 conductive pad 15 interconnect board 17 conductive trace
18 Edge connector 19 Layer of electrically insulating material 20 Sheet of elastomeric material with anisotropic conductivity 25 Conductive spheres 26 Elastomeric insulating material 30 Pressure plate 31, 47 Die 34, 41, 52 Edge conductor 36 Substrate 37 Opening 40 Base interconnection plate
42 Frame 43 Insert 44 Backing sheet or plate 4
5, 53 interconnect 46 volts
50 circuit wafer 51 wafer 54 chip 56
outer backing plate

Claims (15)

[Claims] 1. First and second engagement surfaces that are substantially flat;
a die having an outer edge having a thickness defined therebetween and defining a die outer shape, the first engagement surface including one or more conductive pads; a base formed therein, the base aperture having a peripheral edge defining an aperture shape complementary to the die outer shape, the aperture being dimensioned to receive and engage the die; is so received within the base aperture and the aperture edge engages the die edge to spatially fix the die in a selected orientation in a plane parallel to the first planar engagement surface of the die. an interconnection plate having a base and at least one generally planar engagement surface facing a first planar engagement surface of a die received within the base opening, the planar engagement surface of the plate a first engagement of the die having one or more conductive pads and conductive traces formed thereon, the at least one conductive pad of the planar engagement surface of the plate being received within the base opening; a sheet of anisotropic electrically conductive elastomeric material having an interconnect plate spatially aligned with one conductive pad on a surface and electrically conductive in a direction across the thickness of the sheet; a sheet interposed between the base and the interconnect plate between the first interengaging surface of the die and the interengaging surface of the interconnect plate; and at least one conductive pad of the die. a base and a base for pressing the die and plate toward each other in spatial alignment so as to conductively engage at least one conductive pad of the interconnect plate through a sheet of elastomeric material having an electrical conductivity of and clamping means for engaging an interconnect plate. 2. The semiconductor assembly of claim 1, wherein the interconnect plate includes a plurality of edge conductors operably connected to the traces. 3. The interconnection plate includes a second planar engagement surface opposite the one planar engagement surface, the base includes the planar engagement surface, and the assembly includes a second planar engagement surface of the interconnection plate. The semiconductor assembly of claim 1 including a rigid backing plate overlying the planar engagement surface and the planar engagement surface of the substrate. 4. The base body includes first and second engagement surfaces and a thickness defined therebetween, the base aperture extending through the base body between the first and second engagement surfaces of the base body. The semiconductor assembly described in item 1. 5. The interconnection plate includes a second planar engagement surface opposite the one planar engagement surface, and the assembly includes a second planar engagement surface of the interconnection plate and a second planar engagement surface of the substrate. 5. The semiconductor assembly of claim 4 including a rigid backing plate overlying the flat engagement surface of the semiconductor assembly. 6. The substrate includes a first planar engagement surface;
a base opening defined by a recess formed into the base from the first flat engagement surface of the base, the recess having a flat recess bottom surface, and the recess having a depth approximately equal to the die thickness; , a die is received within the recess, a second planar engagement surface of the die is received against a planar recess bottom surface, and a first engagement surface of the die is received against a planar recess bottom surface.
2. The semiconductor assembly of claim 1, wherein the planar engagement surface of the base is substantially coplanar with the first planar engagement surface of the base. 7. The interconnection plate includes a second planar engagement surface opposite the one planar engagement surface, the base body includes the second planar engagement surface, and the assembly comprises: 7. The semiconductor assembly of claim 6 including a rigid backing plate overlying the second planar engagement surface and the second planar engagement surface of the substrate. 8. First and second engagement surfaces that are substantially flat;
an engagement surface including one or more conductive pads, a thickness defined therebetween, and an outer edge defining a die outer shape; and an outer edge defining a die outer shape. has
a base having a first engagement surface having a plurality of dies including one or more conductive pads and a plurality of apertures formed therein, the base apertures having an aperture shape complementary to an outer shape of the die; a peripheral edge defining a peripheral edge, each aperture dimensioned to receive and engage a respective die, each die being so received within the respective base aperture, the aperture edge defining a peripheral edge; a base that engages a respective die edge to spatially secure the respective die in a selected orientation in a plane parallel to the first planar engagement surface of the respective die; an interconnection plate having at least one substantially planar engagement surface facing a first planar engagement surface of the die, the planar engagement surface of the plate having a plurality of substantially planar engagement surfaces formed thereon; conductive pads and conductive traces, the conductive pads on the planar engagement surface of the plate being spaced apart with respective conductive pads on the first planar engagement surface of the die received within the base aperture. a sheet of anisotropic electrically conductive elastomeric material having interconnection plates aligned in a direction and electrically conductive in a direction across the thickness of the sheet;
The sheet is interposed between the base and the interconnect plate between the first interengaging surface of the die and the interengaging surface of the interconnect plate and conductive pads of the die in an anisotropic manner. the base and interconnect plate to force the die and plate toward each other in spatial alignment so as to conductively engage the conductive pads of the interconnect plate through the sheet of electrically conductive elastomeric material; and engaging clamping means. 9. The semiconductor assembly of claim 8, wherein the interconnect plate includes a plurality of edge conductors operably connected to the traces. 10. The interconnection plate includes a second planar engagement surface opposite the one planar engagement surface, the substrate includes a planar engagement surface, and the assembly comprises a second planar engagement surface of the interconnection plate. 9. The semiconductor assembly of claim 8, including a rigid backing plate overlying the planar engagement surface and the planar engagement surface of the substrate. 11. The base body includes first and second engagement surfaces and a thickness defined therebetween, wherein the base aperture is connected to the first engagement surface of the base body.
9. The semiconductor assembly of claim 8, wherein the semiconductor assembly extends throughout the substrate between the first and second engagement surfaces. 12. The interconnection plate includes a second planar engagement surface opposite the one planar engagement surface, and the assembly includes a second planar engagement surface of the interconnection plate and a second planar engagement surface of the substrate. Claim 11 comprising a rigid backing plate overlying the flat engagement surface of the
A semiconductor assembly described in . 13. The base includes a first flat engagement surface, the base opening is defined by a recess formed into the base from the first flat engagement surface of the base, and the recess has a flat recess bottom. a surface, the recesses have a depth approximately equal to the respective die thickness, each die is received within the respective recess, and the second flat engagement surface of the die is in the flat recess bottom surface. 9. The semiconductor assembly of claim 8, wherein the semiconductor assembly is received abuttingly and wherein the first planar engagement surface of the die is substantially coplanar with the first planar engagement surface of the base. 14. The interconnection plate includes a second planar engagement surface opposite the one planar engagement surface, the base body includes the second planar engagement surface, and the assembly comprises: 14. The semiconductor assembly of claim 13, including a rigid backing plate overlying the second planar engagement surface and the second planar engagement surface of the substrate. 15. The semiconductor assembly of claim 19, wherein the die includes electronic storage arranged in a single in-line storage module.