JPS58149551A - 記憶制御方式 - Google Patents

記憶制御方式

Info

Publication number
JPS58149551A
JPS58149551A JP3132782A JP3132782A JPS58149551A JP S58149551 A JPS58149551 A JP S58149551A JP 3132782 A JP3132782 A JP 3132782A JP 3132782 A JP3132782 A JP 3132782A JP S58149551 A JPS58149551 A JP S58149551A
Authority
JP
Japan
Prior art keywords
main memory
address
unit
bank
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3132782A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6240741B2 (enExample
Inventor
Hiroshi Tamura
宏 田村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3132782A priority Critical patent/JPS58149551A/ja
Publication of JPS58149551A publication Critical patent/JPS58149551A/ja
Publication of JPS6240741B2 publication Critical patent/JPS6240741B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Complex Calculations (AREA)
JP3132782A 1982-02-27 1982-02-27 記憶制御方式 Granted JPS58149551A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3132782A JPS58149551A (ja) 1982-02-27 1982-02-27 記憶制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3132782A JPS58149551A (ja) 1982-02-27 1982-02-27 記憶制御方式

Publications (2)

Publication Number Publication Date
JPS58149551A true JPS58149551A (ja) 1983-09-05
JPS6240741B2 JPS6240741B2 (enExample) 1987-08-29

Family

ID=12328165

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3132782A Granted JPS58149551A (ja) 1982-02-27 1982-02-27 記憶制御方式

Country Status (1)

Country Link
JP (1) JPS58149551A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61103258A (ja) * 1984-10-24 1986-05-21 インターナショナル　ビジネス　マシーンズ　コーポレーション 多重プロセッサ・システム
US7346750B2 (en) 2003-09-16 2008-03-18 Nec Corporation Memory interleave system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61103258A (ja) * 1984-10-24 1986-05-21 インターナショナル　ビジネス　マシーンズ　コーポレーション 多重プロセッサ・システム
US7346750B2 (en) 2003-09-16 2008-03-18 Nec Corporation Memory interleave system

Also Published As

Publication number Publication date
JPS6240741B2 (enExample) 1987-08-29

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