JPS5814597A - Hybrid ic - Google Patents
Hybrid icInfo
- Publication number
- JPS5814597A JPS5814597A JP56111930A JP11193081A JPS5814597A JP S5814597 A JPS5814597 A JP S5814597A JP 56111930 A JP56111930 A JP 56111930A JP 11193081 A JP11193081 A JP 11193081A JP S5814597 A JPS5814597 A JP S5814597A
- Authority
- JP
- Japan
- Prior art keywords
- board
- substrate
- section
- weld ring
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
Landscapes
- Combinations Of Printed Boards (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明はハイトリ、ドＩＣに関し、詳しくは多段構造で
リードがディ、ｆとフラットの複合型のハイプリ、ドＩ
Ｃに係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-pressure IC, and more specifically to a hybrid high-pressure IC with a multi-stage structure and leads of di, f and flat.
Regarding C.
従来のハイプリラードＩＣはウェルドリングの内部底面
（基板部） Ｋ ＲＯＭ ４’ Ｒ９１１Ｍ等の全回路
を実装し、該ウェルドリングの開口部上面にキャッグを
ウェルドリングして回路を気密に封止する構造になって
いる。しかしながら、かかる構造のハイシリ、ドＩＣに
あっては、実装後の回路の一部分のみの特性を試験しよ
うとすると、素子と基板部とを接続するがンディングワ
イヤや基板部め配線・臂ターンを切断する力ど破壊試験
によらないと困難であるという問題があった。Conventional Hyprillard IC has a structure in which all the circuits such as K ROM 4' R911M are mounted on the internal bottom surface (substrate part) of the weld ring, and the circuit is hermetically sealed by welding a cag on the top surface of the opening of the weld ring. It has become. However, in high-silicon ICs with such a structure, when testing the characteristics of only a part of the circuit after mounting, it is necessary to cut the terminal wires that connect the element and the board, and the wiring and arm turns of the board. There was a problem in that it was difficult to do this without using a destructive force test.
本発明は上記問題点を解消する丸めになされたもので、
全回路中の機能別回路を基板め配線ノ々ターン等を破壊
せずに試験でき、かつ実装密度を向上し得るハイブリッ
ドＩＣを提供しようとするものである。The present invention has been made to solve the above problems,
It is an object of the present invention to provide a hybrid IC that can test functional circuits among all circuits without destroying wiring notches on the board, and can improve packaging density.
以下、本発明を一実施例に基づいて詳細に説明する。Hereinafter, the present invention will be explained in detail based on one embodiment.
図中１はウェルドリングであシ、このウェルドリング１
は内周壁部に２つの階段面ｊｌｓｊｌを有する３段構造
のセラＺｖり製のウェルドリング本体１と、この本体１
の上面に被着された環状金属板４とから構成されている
。そして、この本体１の内部底面（第１基板部）５には
複数のＩｃｇｌ〜６藝が同底面５の配線・譬ターン（図
示せず）にグイがンディンダされ、かケこれｇｘｃａ、
〜６＠上面の／膏、ド部（図示せず）は金ワイヤト・・
を介して前記底面５の別の配線／母ターンに接続され、
これら第１基板部５とＩＣ６１〜＃Ｓによシ機能別回路
としてのＲＯＭ部８を構成している。この１０Ｍ部１は
前記率゛−１の側壁から底面５の端部に延出した第１導
電膜９・・・及び第１スルホール１０・・・を介して前
記本体３下面に取付けた複数のディラグ型リード１１・
・・に接続している。1 in the figure is a weld ring, this weld ring 1
A weld ring body 1 made of Cera Zvri and having a three-stage structure having two stepped surfaces on the inner circumferential wall, and this body 1.
It consists of an annular metal plate 4 attached to the upper surface of the holder. Then, on the internal bottom surface (first board part) 5 of this main body 1, a plurality of ICGLs to 6 parts are connected to the wiring and wiring (not shown) on the bottom surface 5.
~6 @ Top surface / paste and do part (not shown) are gold wire...
connected to another wiring/mother turn on the bottom surface 5 via
These first board section 5 and ICs 61 to #S constitute a ROM section 8 as a functionally specific circuit. This 10M section 1 includes a plurality of conductive films 9 extending from the side walls of the ratio (-1) to the ends of the bottom surface 5 and attached to the lower surface of the main body 3 via first through holes 10. Dilag type lead 11・
...is connected to.
また、前記ウェルドリング本体１の第１階段面２１には
第１基板（第２基板部）１１が半田層ＩＪを介して固定
されている。この第１基板１１には、複数のＩＣＩ４１
〜１４！が同基板１２の配線／豐ターン（図示せず）に
ダイーンディンーされ、かつこれらＩ ＣＪ ４１〜１
４！の上面の・譬、ド部（図示せず）は金ワイヤト・・
を介して開基ｔ８１１上の別の配線Ｉ譬ターンＫｌ！続
され、これら第２基板部１１とｌＣｆ４１〜１４！によ
シ機能別回路としての第１ＲＷＭ部１ｊを構成している
。また、この第１ＲＷＭ部１５は前記本体Ｓから第１階
段面１１に延出した第２導電膜１−に半田部１ｒを介し
て接続され、かつ第２導電膜１＃は第２スルホール１１
・・・を介して前記第１導電膜膜−一・に接続されてい
る。Further, a first substrate (second substrate portion) 11 is fixed to the first stepped surface 21 of the weld ring main body 1 via a solder layer IJ. This first board 11 includes a plurality of ICIs 41
~14! are die-dine-dyed to the wiring/tooth turn (not shown) of the same board 12, and these I CJ 41-1
4! The top part (not shown) is made of gold wire.
Another wiring I example turn Kl on the open base t811 through ! These second substrate parts 11 and lCf41-14! The first RWM section 1j is configured as a functionally specific circuit. Further, the first RWM section 15 is connected to the second conductive film 1- extending from the main body S to the first step surface 11 via the solder section 1r, and the second conductive film 1# is connected to the second through hole 11.
... is connected to the first conductive film-1.
更に、前記本体１の第１階段面１１ Ｋは第２基板１１
Ｃ第３基板部）が半田層１１′を介して固定されている
。とＯ第２基板１＃には複数のｒｃｘａ＠〜２０マ及び
プンデンサｊ ｚｌ 、 ２１嘗が同基板１＃の配＠Ｉ
やターン（図示せず）に接続され、かつこれらＩ Ｃｊ
ｅ＠ 〜Ｊ ａｔの／＃。Furthermore, the first step surface 11K of the main body 1 is connected to the second substrate 11.
C third substrate portion) is fixed via a solder layer 11'. and O second board 1# has a plurality of rcxa@~20mm and pundensa j zl, 21 years arranged on the same board 1#
and turns (not shown), and these I Cj
e@ ~ J at's/#.
ド部（図示せず）は金ワイヤｒ−・を介して同基板１＃
の別の配線ｄターンに接続され、これら第３基板部１Ｍ
、ＩＣｌ０１〜２０マ及びコン通りて外部Ｋｇ設した複
数Ｏフラット型リードｊ１・・・に半田部１１′を介し
て接続しておシ、かつ骸７″）、）型リードｊ ｊ−・
・の第２階段面２■に位置する部分は第３スルホール１
４・・・を介して前記第８導電展１ｉＫＩＩＩＩｔ続し
ている。そして、前記ウェルドリング本体１上には前記
ＲＯＭ部８、第１．第２ＲＷＭ部１１．２１を気密に封
止するための蓋体２ｊが本体１上の環状金属板４とのウ
ェルディングによ）固定されている。The board part (not shown) is connected to the same board 1# through the gold wire r-.
are connected to another wiring d-turn of these third board parts 1M.
, ICl01-20, connect to multiple O flat type leads j1... provided externally through solder parts 11' through solder parts 7''), ) type leads j j-.
・The part located on the second step surface 2■ is the third through hole 1
The eighth conductive conductor 1iKIIIt is continued through 4.... Then, on the weld ring main body 1, the ROM section 8, the first . A lid 2j for hermetically sealing the second RWM section 11.21 is fixed to the annular metal plate 4 on the main body 1 by welding.
しかして、本発明によればウェルドリング本体１を内周
壁部に２つの階段面ｊｌｅｊｌを有する３段構造とし、
内部底面５を第１基板部とし、かつ第１．第２の階段面
２１ｍ１Ｈに第２゜第３基板部１１．１ｆを設す、これ
ら基板部Ｊ。According to the present invention, the weld ring main body 1 has a three-stage structure having two step surfaces on the inner circumferential wall,
The inner bottom surface 5 is the first substrate part, and the first. These substrate portions J include a second and third substrate portion 11.1f provided on the second step surface 21m1H.
１１．１ｆＫＩＣ等を接続しテＲＯＭ部１、第１゜第２
のｍ部Ｊ ｓ ｅ ｘ Ｉ を上下方向に構成する、つ
１１１３次元方向に実装するため、高密度のノ・イツリ
ッドＩＣを得ることができる。しかも、３次元方向での
実装参本宅嗜による高密度化がなされるととに伴ない、
入出力端子数がＩｌツケーゾの寸法で制約される場合が
あるが、リードをディ、グ型リード１１・・・とフラッ
ト型リード２Ｓ・・・との複合化によりｅ記制約を解消
できる。11. Connect the 1f KIC, etc. to the ROM section 1, 1st and 2nd
Since the m part J s e x I of is configured in the vertical direction and is mounted in the 1113-dimensional direction, it is possible to obtain a high-density no-itrid IC. Moreover, with the increase in density due to three-dimensional implementation,
Although the number of input/output terminals is sometimes restricted by the dimensions of the Il connector, the restriction can be overcome by combining the leads with the dig-type leads 11, . . . and the flat-type leads 2S, .
を九、基板部を多段構造とし、それら基板部１．１１．
１９に機能別回路、例えハＲＯＭ ＠ ａ、第１．第２
０部Ｍ部１！！、１１とするととＫよシ、各基板部毎に
ＩＣ等を実装してから基板別Ｋｍ卯別回路（例えば１０
Ｍ部１）の特性試験を行なうことができ、試験に合格し
た回路の基、板部だけ多段構造にできる。したがって、
従来の如く全回路を一つの基板に組込んだ場合のように
ワイヤを外したり、配線Δターンを切断したすするよう
カ破壊試験を行なわすに各機能別回路の特性チェ、りを
行なうことができ、試験作業の効率化と品質の信頼性向
上を達成し得るノ・イプリ、ドＩＣを得ることができる
。9. The substrate portion has a multi-stage structure, and the substrate portions 1.11.
19 shows functional circuits, for example, ROM@a, 1st. Second
Part 0 M part 1! ! , 11, and then K, IC etc. are mounted on each board, and then the circuit for each board is Km (for example, 10
A characteristic test can be performed on the M section 1), and only the substrate and plate sections of circuits that have passed the test can be made into a multi-stage structure. therefore,
As in the case where all the circuits are assembled on one board as in the past, the characteristics of each functional circuit must be checked in order to perform a destructive test by removing the wire or cutting the wiring delta turn. As a result, it is possible to obtain an original IC that can improve the efficiency of testing work and improve the reliability of quality.
なお、本発明に係るハイプリッＰＩＣは上記実施例の如
く基板部を３段構造にすみ場合に限らず、２段或いは４
段以上の構造にしてもよい。It should be noted that the high-prip PIC according to the present invention is not limited to the case where the substrate part has a three-layer structure as in the above embodiment, but can also have a two-layer or four-layer structure.
The structure may have more than tiers.
八
を丸、機能別回路は上記実施例の如きＲＯＭや部層、に
限らず、その他の回路にしてもよい。The 8th circle indicates that the functional circuits are not limited to the ROM and sublayers as in the above embodiments, but may be other circuits.
以上詳述した如く、本発明によれば回路の実装密度を著
しく向上できると共に、全回路を機能別回路として各段
に分けることによシワイヤ管外し九シ、基板の配線Δタ
ーン等を破壊せずに試験でき品質の信頼性向上を図るこ
とができる等顕著な効果を有するハイブリッドＩＣを提
供できるものである。As described in detail above, according to the present invention, the packaging density of the circuit can be significantly improved, and by dividing all the circuits into functional circuits into each stage, it is possible to eliminate the shear wire pipe removal, the wiring delta turn of the board, etc. Accordingly, it is possible to provide a hybrid IC that has remarkable effects such as being able to be tested without any problems and improving reliability of quality.
図は本発明の一実施例を示す３段構造のハイプリ、ドＩ
Ｃの断面図である。
１・・・ウェルドリング、Ｓ・・・ウェルドリング本体
、４・・・環状金属板、５−・内部底面（第１基板部）
−１〜ｇ、＊１４＠〜Ｊ４１ａＩＯ１〜２０マ・・・Ｉ
Ｃ，Ｆ−・・金ワイヤ、ｌｌ−ＲＯＭ部、１１・・・デ
ィラグ型リード、１２−第１基板（第２基板部）、Ｊ
Ｊ−・・第１ＲＷＭ部、１９・・・第２基板（第８基板
部）、トドー＠２ＲＷＭ部、ｊ １−・・７フツト型リ
ード、２５−・蓋体。The figure shows an embodiment of the present invention with a three-stage structure of Hypuri and DeI.
FIG. 1... Weld ring, S... Weld ring body, 4... Annular metal plate, 5-- Internal bottom surface (first substrate part)
-1~g, *14@~J41aIO1~20ma...I
C, F-...Gold wire, 11-ROM section, 11--Dilag type lead, 12-1st board (2nd board part), J
J-...1st RWM section, 19--2nd substrate (8th substrate section), Todo@2RWM section, j 1-...7 foot type lead, 25--lid body.
Claims (1)
回路が実装された複数の基板管設け、かつ前記ウェルト
リジグに前記基板と接続するフラット型リード及びディ
、ｆ型リードを取付けたことを特徴とするバイプリ、ド
ＩＣ。A plurality of substrate tubes with circuits mounted for different functions are provided on each step surface of the weld ring having a multi-step structure, and flat type leads and D and F type leads connected to the substrates are attached to the welding jig. Bipuri, de IC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56111930A JPS5814597A (en) | 1981-07-17 | 1981-07-17 | Hybrid ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56111930A JPS5814597A (en) | 1981-07-17 | 1981-07-17 | Hybrid ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5814597A true JPS5814597A (en) | 1983-01-27 |
Family
ID=14573686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56111930A Pending JPS5814597A (en) | 1981-07-17 | 1981-07-17 | Hybrid ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5814597A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005286337A (en) * | 2004-03-30 | 2005-10-13 | General Electric Co <Ge> | High-density connection between multiple circuit boards |
-
1981
- 1981-07-17 JP JP56111930A patent/JPS5814597A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005286337A (en) * | 2004-03-30 | 2005-10-13 | General Electric Co <Ge> | High-density connection between multiple circuit boards |
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