JPH09181215A - Semiconductor device, manufacture and packaging thereof - Google Patents

Semiconductor device, manufacture and packaging thereof

Info

Publication number
JPH09181215A
JPH09181215A JP7336637A JP33663795A JPH09181215A JP H09181215 A JPH09181215 A JP H09181215A JP 7336637 A JP7336637 A JP 7336637A JP 33663795 A JP33663795 A JP 33663795A JP H09181215 A JPH09181215 A JP H09181215A
Authority
JP
Japan
Prior art keywords
mounting
semiconductor device
wiring board
main body
overlapping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7336637A
Other languages
Japanese (ja)
Other versions
JP3942206B2 (en
Inventor
Toshiyuki Takahashi
敏幸 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Akita Electronics Systems Co Ltd
Original Assignee
Hitachi Ltd
Akita Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Akita Electronics Co Ltd filed Critical Hitachi Ltd
Priority to JP33663795A priority Critical patent/JP3942206B2/en
Publication of JPH09181215A publication Critical patent/JPH09181215A/en
Application granted granted Critical
Publication of JP3942206B2 publication Critical patent/JP3942206B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a small-sized and highly integrated semiconductor device which allows easy and reliable packaging test. SOLUTION: A semiconductor device comprises at least a packaging main body 4 having a wiring board 2 with external terminals 6 on a surface, an overlap portion 5 having a wiring board on which an electronic part including at least a semiconductor chip is mounted, and at least a fold portion 3 having the flexible wiring board 2 which electrically and mechanically connects the packaging main body 4 and the overlap portion 5 which are of the same type or different types of material. The overlap portion 5 is folded at the fold portion 3 and laid on the predetermined packaging main body 4. The packaging main body 4, the fold portion 3 and the wiring board 2 of the overlap portion 5 comprise flexible material (resin film) which can be integrated and can be transparent. The packaging main body 4 also has external terminals within its region overlapped with the electronic-part mounting region of the overlap portion 5. The overlap portion 5 is fixed to the packaging main body 4 with fixing means (adhesive). The mounting region of the semiconductor chip (electronic part) is covered with a seal member 7.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は表面実装型の半導体
装置およびその製造方法ならびにその実装方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type semiconductor device, a method for manufacturing the same and a method for mounting the same.

【0002】[0002]

【従来の技術】IC,LSI等半導体装置の封止(パッ
ケージ)形態として、気密封止,非気密封止等がある。
また、半導体装置の実装形態の違いにより、リード挿入
型,表面実装型がある。
2. Description of the Related Art As a sealing (package) form of a semiconductor device such as an IC or LSI, there are hermetic sealing, non-hermetic sealing and the like.
Further, there are a lead insertion type and a surface mounting type depending on the mounting form of the semiconductor device.

【0003】たとえば、SIP(Single Inline Packag
e),ZIP (Zigzag Inline Package),PGA(Pin Gr
id Array) 等は基板の挿入孔にリードを挿入するリード
挿入型パッケージであり、SOP (Small Outline L-Le
aded Package) ,SOJ(Small Outline J-Leaded Pac
kage) ,QFP(Quad Flat Package),QFJ(QuadFl
at J-Leaded Package) ,BGA(Ball Grid Array),
HGA(Hall Grid Array)は表面実装型パッケージであ
る。
For example, SIP (Single Inline Packag)
e), ZIP (Zigzag Inline Package), PGA (Pin Gr
id Array) is a lead insertion type package in which leads are inserted into the insertion holes of the board, and SOP (Small Outline L-Le
aded Package), SOJ (Small Outline J-Leaded Pac
kage), QFP (Quad Flat Package), QFJ (QuadFl)
at J-Leaded Package), BGA (Ball Grid Array),
HGA (Hall Grid Array) is a surface mount type package.

【0004】前記SOP,SOJは、ICチップを封止
したパッケージの2方向にリードピン(リード)を出す
構造であり、前記QFP,QFJはパッケージの4方向
にリードピンを出す構造である。
The SOP and SOJ have a structure in which lead pins (leads) are provided in two directions of a package in which an IC chip is sealed, and the QFP and QFJ have a structure in which lead pins are provided in four directions of the package.

【0005】また、PGA,BGAはパッケージの下面
に複数列のピングリッドやボールグリッドを出す構造で
あり、HGAは基板を貫通するスルーホール状のグリッ
ドを有する構造である。
The PGA and BGA have a structure in which a plurality of rows of pin grids and ball grids are provided on the lower surface of the package, and the HGA has a through-hole grid penetrating the substrate.

【0006】前記HGAについては、日経BP社発行
「日経エレクトロニクス」1995年4月24日号(No.634)、
P20に記載されている。また、前記他のパッケージ技術
については、同社発行「VLSIパッケージング技術
(上)」1993年5月15日発行、P76〜P84に記載されて
いる。
The HGA is described in "Nikkei Electronics," issued by Nikkei BP, April 24, 1995 (No. 634),
P20. The other packaging technology is described in "VLSI Packaging Technology (above)" issued by the same company, May 15, 1993, P76 to P84.

【0007】[0007]

【発明が解決しようとする課題】従来のSOP,SO
J,QFP,QFJ等QFPで代表される表面実装型半
導体装置では、パッケージの周辺にリード(外部端子)
が突出することから、実装基板に半導体装置を実装した
際、半田による実装部(半田実装部)が容易に目視で
き、実装の良否を容易に目視判断できる利点がある。
[Problems to be Solved by the Invention] Conventional SOP, SO
In surface mounting type semiconductor devices represented by QFP such as J, QFP, QFJ, leads (external terminals) are provided around the package.
Because of the protrusion, when a semiconductor device is mounted on a mounting board, a mounting portion (solder mounting portion) formed by solder can be easily visually observed, and there is an advantage that the quality of mounting can be easily visually determined.

【0008】しかし、昨今では半導体装置の高密度・高
集積・高機能化が図られる結果、信号ピン(リード)が
増大し、ピンピッチ(リードピッチ)が狭くなる傾向に
ある。このため、配線基板のランドとリードとを接続す
る半田が隣同士で接続するいわゆる半田ブリッジが発生
し、ショート不良を起こし易くなり、半田実装が難しく
なる。
However, in recent years, as a result of higher density, higher integration and higher functionality of semiconductor devices, the number of signal pins (leads) increases and the pin pitch (lead pitch) tends to narrow. For this reason, a so-called solder bridge in which the solder connecting the land of the wiring board and the lead is connected adjacent to each other is generated, which easily causes a short circuit defect, and makes solder mounting difficult.

【0009】このような半田ブリッジ等の不良発生を防
止するためには、リードピッチを大きくすればよいが、
リードピッチを大きくするとパッケージが大型化する。
In order to prevent such defects such as solder bridges, the lead pitch may be increased.
If the lead pitch is increased, the package becomes larger.

【0010】一方、BGA型半導体装置は、配線基板の
下面に信号ピン(リード)の変わりに外部端子としてバ
ンプ電極(ボール電極)を複数列に配設した構造(ボー
ルグリッド)となるため、外部端子ピッチを前記QFP
等の表面実装型半導体装置に比較して広くとれ、半田ブ
リッジが起き難くできるとともに、パッケージの小型化
が図れる。
On the other hand, the BGA type semiconductor device has a structure (ball grid) in which bump electrodes (ball electrodes) are arranged in a plurality of rows as external terminals instead of signal pins (leads) on the lower surface of the wiring board. Terminal pitch is QFP
In comparison with surface mount semiconductor devices such as the above, it can be widely used, solder bridges are less likely to occur, and the size of the package can be reduced.

【0011】特に、半導体チップの真下の配線基板部分
にボール電極を配置するものは、パッケージを略半導体
チップと同程度に小型化できるため、半導体装置の小型
化が図れ、実装面積を大幅に縮小できる(日経BP社発
行「日経エレクトロニクス」1995年1月16日号、No.62
6、P76〜P86)。
In particular, in the case where the ball electrode is arranged on the wiring board portion directly below the semiconductor chip, the package can be downsized to substantially the same size as the semiconductor chip, so that the semiconductor device can be downsized and the mounting area can be greatly reduced. Available (Nikkei BP's "Nikkei Electronics" January 16, 1995 issue, No.62
6, P76-P86).

【0012】しかし、この構造は配線基板が邪魔をし、
半田付け状態を目視検査することができないため、ボー
ル電極の接続信頼性の面で不安があった。
However, in this structure, the wiring board interferes,
Since the soldering state cannot be visually inspected, there was concern about the connection reliability of the ball electrode.

【0013】そこで、配線基板を透明な材質で形成し、
ボール電極の半田付け状態を基板を通して確認できるも
の(日経BP社発行「日経マイクロデバイス」1994年10
月号、P17) や基板を貫通するスルーホールを信号ピン
の替わりに使用することで半田の吸い上がり状態を目視
検査できるHGAが開発されている。
Therefore, the wiring board is formed of a transparent material,
What can confirm the soldering condition of the ball electrode through the board (“Nikkei Microdevice” issued by Nikkei BP, 1994 10
An HGA has been developed that can visually inspect the state of solder wicking by using a through-hole that penetrates the board or a board instead of a signal pin.

【0014】しかし、この2つの構造の半導体装置は、
実装時の半田付け状態を目視する目的で開発された構造
であるため、半導体チップの真下部分にはボール電極や
スルーホールを設けることができず、パッケージが半導
体チップよりも遥に大型となる。
However, the semiconductor device having these two structures is
Since the structure was developed for the purpose of visually checking the soldering state during mounting, the ball electrode and the through hole cannot be provided directly below the semiconductor chip, and the package becomes much larger than the semiconductor chip.

【0015】本発明の目的は、実装時の実装状態が目視
できる小型の半導体装置およびその製造方法ならびにそ
の実装方法を提供することにある。
An object of the present invention is to provide a small-sized semiconductor device in which the mounting state at the time of mounting can be visually observed, a manufacturing method thereof, and a mounting method thereof.

【0016】本発明の他の目的は、実装時の実装状態が
目視できかつ集積度の高い小型の半導体装置およびその
製造方法ならびにその実装方法を提供することにある。
Another object of the present invention is to provide a small-sized semiconductor device in which a mounting state at the time of mounting can be visually observed and which has a high degree of integration, a manufacturing method thereof, and a mounting method thereof.

【0017】本発明の前記ならびにそのほかの目的と新
規な特徴は、本明細書の記述および添付図面からあきら
かになるであろう。
The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

【0018】[0018]

【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を簡単に説明すれば、下
記のとおりである。
The following is a brief description of an outline of typical inventions disclosed in the present application.

【0019】(半導体装置) (1)一面に外部端子を設けた配線板からなる少なくと
も一つの実装本体部と、少なくとも半導体チップを含む
電子部品を搭載した配線板からなる一つの重畳部と、前
記実装本体部と前記重畳部のうち同種または異種のもの
を電気的かつ機械的に連結する可撓性の配線板からなる
少なくとも一つの折返部とを有し、前記重畳部は前記折
返部で折り返えされて所定の実装本体部や重畳部上に積
み重ねられる構成となっている。一例では、前記実装本
体部および折返部3ならびに重畳部5はそれぞれ一つと
なっている。また、前記実装本体部および折返部ならび
に重畳部の配線板は一体となりかつ透明となる可撓性体
(樹脂フィルム)で構成されている。前記重畳部の電子
部品搭載領域が重なる実装本体部領域内にも外部端子が
設けられている。前記重畳部は前記実装本体部に接着剤
や接着テープによる固定手段によって固定されている。
前記半導体チップの搭載領域は封止体で被われている。
(Semiconductor Device) (1) At least one mounting main body portion including a wiring board having external terminals provided on one surface, and one overlapping portion including a wiring board on which an electronic component including at least a semiconductor chip is mounted, A mounting body portion and at least one folding portion made of a flexible wiring board that electrically and mechanically connects the same kind or different kinds of the overlapping portion, and the overlapping portion is folded at the folding portion. It is returned and stacked on a predetermined mounting main body portion or overlapping portion. In one example, the mounting main body portion, the folding portion 3, and the overlapping portion 5 are each one. Further, the wiring board of the mounting main body portion, the folded-back portion and the overlapping portion is formed of a flexible body (resin film) which is integral and transparent. External terminals are also provided in the mounting body portion area where the electronic component mounting areas of the overlapping portion overlap. The overlapping portion is fixed to the mounting main body by fixing means such as an adhesive or an adhesive tape.
The mounting area of the semiconductor chip is covered with a sealing body.

【0020】(2)前記手段(1)の構成において、実
装本体部の上に複数の重畳部が前記実装本体部に連なる
折返部の折り返しによって積み重ねられている。
(2) In the structure of the above-mentioned means (1), a plurality of overlapping portions are stacked on the mounting body portion by folding back the folding portion connected to the mounting body portion.

【0021】(3)前記手段(2)の構成において、前
記実装本体部および重畳部の配線板は非可撓性体で形成
されている。
(3) In the configuration of the above-mentioned means (2), the mounting main body portion and the wiring board of the overlapping portion are formed of a non-flexible body.

【0022】(4)前記手段(1)の構成において、前
記外部端子は前記配線板を貫通するスルーホールの内壁
とその縁に設けた導体層によって形成されている。
(4) In the structure of the above-mentioned means (1), the external terminal is formed by the inner wall of the through hole penetrating the wiring board and the conductor layer provided on the edge thereof.

【0023】(5)前記手段(1)の構成において、前
記折返部の折り返し時の曲率半径を規定する折り返し形
状規定手段が設けられている。
(5) In the structure of the means (1), there is provided a folded shape defining means for defining a radius of curvature of the folded portion when the folded portion is folded back.

【0024】(半導体装置の製造方法) (6)一面に外部端子を設ける台座を有する配線板から
なる少なくとも一つの実装本体部と、少なくとも半導体
チップを含む電子部品を搭載する領域を有する配線板か
らなる一つの重畳部と、前記実装本体部と前記重畳部の
うち同種または異種のものを電気的かつ機械的に連結す
る可撓性の配線板からなる少なくとも一つの折返部とを
少なくとも有し、前記重畳部は前記折返部で折り返えさ
れて所定の実装本体部や重畳部上に積み重ねられる構成
の配線基板を用意する工程と、前記重畳部に半導体チッ
プを含む電子部品の搭載と電極と配線の電気的接続を行
う工程と、前記電子部品搭載領域を封止体で被う工程
と、前記実装本体部の台座に半田バンプ電極を形成する
工程と、前記配線板の不要部分を切断除去する工程と、
所定の折返部を折り返して所定の実装本体部上に重畳部
を積み重ねる工程とを有する。一例では、前記実装本体
部および折返部ならびに重畳部を形成する配線板は一枚
の透明な樹脂フィルム(配線フレーム)からなり、前記
実装本体部および折返部ならびに重畳部はそれぞれ一つ
となっている。また、前記実装本体部上に重畳部を積み
重ねる際、前記重畳部を接着剤や接着テープで仮固定す
る。
(Manufacturing Method of Semiconductor Device) (6) From a wiring board having at least one mounting main body made of a wiring board having a pedestal on one surface of which external terminals are provided, and an area for mounting electronic components including at least a semiconductor chip. And at least one folding portion made of a flexible wiring board that electrically and mechanically connects the same type or different types among the mounting body portion and the overlapping portion. A step of preparing a wiring board having a configuration in which the overlapping part is folded back at the folding part and stacked on a predetermined mounting main body part or the overlapping part; mounting of an electronic component including a semiconductor chip on the overlapping part and an electrode; A step of electrically connecting the wiring, a step of covering the electronic component mounting area with a sealing body, a step of forming a solder bump electrode on a pedestal of the mounting main body section, and cutting an unnecessary portion of the wiring board. Disconnecting and removing,
And folding the predetermined folded-back portion to stack the overlapping portion on the predetermined mounting main body portion. In one example, the wiring board forming the mounting body portion, the folded portion, and the overlapping portion is made of one transparent resin film (wiring frame), and the mounting body portion, the folding portion, and the overlapping portion are each one. . Further, when stacking the overlapping portion on the mounting main body portion, the overlapping portion is temporarily fixed with an adhesive or an adhesive tape.

【0025】(7)前記手段(6)の構成において、実
装本体部に設けられる外部端子は実装本体部を形成する
配線板に設けられたスルーホールの内壁とその縁に設け
た導体層(HGA構造)とによって形成されている。
(7) In the structure of the above-mentioned means (6), the external terminals provided on the mounting body are the inner wall of the through hole provided on the wiring board forming the mounting body and the conductor layer (HGA) provided on the edge thereof. Structure) and.

【0026】(半導体装置の実装方法) (8)一面に外部端子を設けた透明な配線板からなる少
なくとも一つの実装本体部と、少なくとも半導体チップ
を含む電子部品を搭載した配線板からなる一つの重畳部
と、前記実装本体部と前記重畳部のうち同種または異種
のものを電気的かつ機械的に連結する可撓性の配線板か
らなる少なくとも一つの折返部とを有し、前記重畳部は
前記折返部で折り返えされて所定の実装本体部や重畳部
上に積み重ねられる半導体装置を実装基板に実装する方
法であって、前記実装基板のランド上に前記実装本体部
の外部端子を重ねて加熱して外部端子を前記ランドに固
定した後、前記実装本体部の透明な配線板を通して外部
端子の接続状態を検査(目視検査)し、その後前記実装
基板に固定した実装本体部上に前記重畳部を重ねる。前
記実装本体部上に重畳部を積み重ねる際、前記重畳部を
接着剤や接着テープで固定する。一例では、前記実装本
体部および折返部ならびに重畳部を形成する配線板は一
枚の透明な可撓性樹脂フィルムからなり、前記実装本体
部および折返部ならびに重畳部はそれぞれ一つとなって
いる。
(Semiconductor Device Mounting Method) (8) At least one mounting body made of a transparent wiring board having external terminals provided on one surface, and one wiring board having an electronic component including at least a semiconductor chip mounted thereon. A superposed portion, and at least one folded portion formed of a flexible wiring board that electrically and mechanically connects the same or different types of the mounting main body portion and the superposed portion, and the superposed portion is A method of mounting on a mounting board a semiconductor device which is folded back at the folding section and stacked on a predetermined mounting body section or overlapping section, wherein external terminals of the mounting body section are stacked on lands of the mounting board. After heating to fix the external terminal to the land, the connection state of the external terminal is inspected (visual inspection) through the transparent wiring board of the mounting main body, and then it is placed on the mounting main body fixed to the mounting board. The overlapping parts are overlapped. When stacking the overlapping portion on the mounting main body portion, the overlapping portion is fixed with an adhesive or an adhesive tape. In one example, the wiring board that forms the mounting main body portion, the folded portion, and the overlapping portion is made of one transparent flexible resin film, and the mounting main body portion, the folding portion, and the overlapping portion are each one.

【0027】(9)配線板からなりかつ外部端子はスル
ーホールの内壁とその縁に設けた導体層で形成される少
なくとも一つの実装本体部と、少なくとも半導体チップ
を含む電子部品を搭載した配線板からなる一つの重畳部
と、前記実装本体部と前記重畳部のうち同種または異種
のものを電気的かつ機械的に連結する可撓性の配線板か
らなる少なくとも一つの折返部とを有し、前記重畳部は
前記折返部で折り返えされて所定の実装本体部や重畳部
上に積み重ねられる半導体装置を実装基板に実装する方
法であって、前記実装基板のランド上に前記実装本体部
の外部端子を重ねた後、前記ランドまたは外部端子にあ
らかじめ設けられた接合材を溶かして前記外部端子を前
記ランドに接続し、その後前記実装本体部のスルーホー
ル内に吸い上げられた接合材の有無によって外部端子の
接続状態を検査(目視検査)し、ついで前記実装基板に
固定した実装本体部上に前記重畳部を重ねる。前記接合
材を溶かして前記外部端子を前記ランドに接続した後、
前記実装本体部のスルーホール内に吸い上げられた接合
材にプローブ・ピンを当てて電気特性検査を行う。前記
実装本体部上に重畳部を積み重ねる際、前記重畳部を接
着剤や接着テープで固定する。一例では、前記実装本体
部および折返部ならびに重畳部を形成する配線板は一枚
の透明な可撓性樹脂フィルムからなり、前記実装本体部
および折返部ならびに重畳部はそれぞれ一つとなってい
る。
(9) A wiring board which is composed of a wiring board and whose external terminals include at least one mounting body formed of an inner wall of the through hole and a conductor layer provided on the edge thereof, and an electronic component including at least a semiconductor chip. And one at least one folded portion made of a flexible wiring board that electrically and mechanically connects the same type or different types of the mounting body portion and the overlapping portion, A method of mounting a semiconductor device, wherein the overlapping portion is folded back at the folding portion and stacked on a predetermined mounting main body portion or the overlapping portion on a mounting substrate, wherein the mounting main body portion of the mounting main body portion is mounted on a land of the mounting substrate. After stacking the external terminals, melt the bonding material provided in advance on the lands or the external terminals to connect the external terminals to the lands, and then suck up into the through holes of the mounting body. The presence or absence of the bonding material was examined the connection state of the external terminals (visual inspection), and then overlaying the superposed portions on the mounting board in a fixed mounting body portion on. After melting the bonding material and connecting the external terminal to the land,
A probe pin is applied to the bonding material sucked up in the through hole of the mounting body to perform an electrical characteristic inspection. When stacking the overlapping portion on the mounting main body portion, the overlapping portion is fixed with an adhesive or an adhesive tape. In one example, the wiring board that forms the mounting main body portion, the folded portion, and the overlapping portion is made of one transparent flexible resin film, and the mounting main body portion, the folding portion, and the overlapping portion are each one.

【0028】(半導体装置)前記(1)の手段によれ
ば、(a)半導体装置は、折返部で自由に折り返しがで
き、必要に応じて実装本体部の上に重畳部を積み重ねる
構造となっていることと、配線板(可撓性配線基板)が
透明体であることから、重畳部を実装本体部に重ねない
状態では配線板の裏面の外部端子を目視できる。
(Semiconductor Device) According to the above-mentioned means (1), (a) the semiconductor device can be freely folded at the folding portion, and the overlapping portion is stacked on the mounting main body portion as necessary. In addition, since the wiring board (flexible wiring board) is a transparent body, the external terminals on the back surface of the wiring board can be visually observed when the overlapping portion is not overlapped with the mounting main body portion.

【0029】(b)半導体装置は重畳部を開くことによ
っていつでも配線板を通して配線板の裏面の外部端子を
目視できるため、半導体装置を実装基板に実装した後で
も外部端子の半田実装状態を目視検査できるため、実装
本体部の配線板には、半導体チップ等が重なる部分にも
外部端子を配置できることになり、半導体装置の小型化
および多ピン化が図れる。
(B) In the semiconductor device, the external terminals on the back surface of the wiring board can be visually inspected through the wiring board at any time by opening the overlapping portion. Therefore, the solder mounting state of the external terminals can be visually inspected even after the semiconductor device is mounted on the mounting board. Therefore, the wiring board of the mounting main body can be provided with external terminals even in a portion where the semiconductor chip and the like overlap each other, and the semiconductor device can be miniaturized and the pin count can be increased.

【0030】(c)半導体装置は、折返部で自由に折り
返しができ、必要に応じて実装本体部の上に重畳部を積
み重ねる構造となっているが、必要に応じて重畳部を実
装本体部に接着剤や接着テープによって仮固定を含めて
固定できるため、半導体装置の取扱性が向上する。
(C) The semiconductor device has a structure in which the folded portion can be freely folded and the superposed portion is stacked on the mounting main body portion as needed. However, the superposed portion is mounted as necessary. Since it can be fixed including temporary fixing with an adhesive or an adhesive tape, the handling of the semiconductor device is improved.

【0031】(d)半導体装置は、実装本体部4下面に
半田によってバンプ電極を形成する際、バンプ電極形成
後、実装本体部のみを薬品に浸け、半導体チップが搭載
された重畳部を薬品に浸けないようにできるため、コス
トが高く付く無洗浄タイプの半田を用いることなく半田
フラックスを使用する半田を用いてバンプ電極を形成す
ることができるため、半導体装置の製造コストの低減が
達成できる。
(D) In the semiconductor device, when the bump electrodes are formed on the lower surface of the mounting body 4 by soldering, after forming the bump electrodes, only the mounting body is soaked in a chemical, and the overlapping portion on which the semiconductor chip is mounted is exposed to the chemical. Since the bump electrodes can be formed by using solder that uses a solder flux without using the non-cleaning type solder, which is expensive and does not cost much, it is possible to reduce the manufacturing cost of the semiconductor device.

【0032】前記(2)の手段によれば、実装本体部に
複数の重畳部を積み重ねることができるため、前記手段
(1)の構成による効果に加えて更なる高集積化が達成
できる。
According to the above-mentioned means (2), since a plurality of overlapping portions can be stacked on the mounting main body portion, further high integration can be achieved in addition to the effect of the constitution of the above-mentioned means (1).

【0033】前記(3)の手段によれば、実装本体部お
よび重畳部の配線板は非可撓性体となっているが、実装
本体部と重畳部を電気的かつ機械的に連結する折返部は
可撓性の配線板で形成されていることから、前記手段
(1)の構成による効果を得ることができる。
According to the above-mentioned means (3), the wiring board of the mounting main body portion and the overlapping portion is a non-flexible body, but the folding back for electrically and mechanically connecting the mounting main body portion and the overlapping portion. Since the part is formed of the flexible wiring board, the effect of the configuration of the means (1) can be obtained.

【0034】前記(4)の手段によれば、実装本体部に
設けられる外部端子は、配線板を貫通するスルーホール
の内壁とその縁に設けた導体層によって形成されている
ことから、実装時、スルーホール内に吸い上がる半田
(接合材)の有無を観察できるため、外部端子を半導体
チップ等が重ねられる実装本体部の領域にも配置でき、
半導体装置の小型化,多ピン化が達成できる。
According to the above-mentioned means (4), since the external terminal provided in the mounting main body is formed by the inner wall of the through hole penetrating the wiring board and the conductor layer provided at the edge thereof, Since it is possible to observe the presence of solder (bonding material) sucked into the through-holes, external terminals can be placed in the area of the mounting body where semiconductor chips etc. are stacked,
It is possible to reduce the size of semiconductor devices and increase the number of pins.

【0035】前記(5)の手段によれば、半導体装置の
折返部には折り返し形状規定手段が設けられていて、折
返部を折り返す際、折返部に大きなストレスが掛かるよ
うな小さな曲率半径で曲がることがないようにされてい
ることから、折返部で繰り返して折り返し動作しても折
返部が劣化しない。
According to the above-mentioned means (5), the folded-back shape of the semiconductor device is provided in the folded-back portion, and when the folded-back portion is folded back, the folded-back portion is bent with a small radius of curvature so that a great stress is applied to the folded-back portion. Since it is prevented from occurring, the folding portion does not deteriorate even if the folding portion repeatedly performs the folding operation.

【0036】(半導体装置の製造方法)前記(6)の手
段によれば、透明な樹脂フィルムを主体として形成され
た配線板(配線フレーム)を用い、従来確立されたリー
ドフレームによる半導体装置製造技術と同様に製造が行
えるため、高品質の折り返し重畳構造のBGA型の半導
体装置を生産性良く製造することができる。
(Manufacturing Method of Semiconductor Device) According to the above-mentioned means (6), a wiring board (wiring frame) formed mainly of a transparent resin film is used, and a semiconductor device manufacturing technique by a lead frame established conventionally is used. Since the manufacturing can be performed in the same manner as described above, a high quality BGA type semiconductor device having a folded and superposed structure can be manufactured with high productivity.

【0037】前記(7)の手段によれば、透明な樹脂フ
ィルムを主体として形成された配線板(配線フレーム)
を用い、従来確立されたリードフレームによる半導体装
置製造技術と同様に製造が行えるため、高品質の折り返
し重畳構造のHGA型の半導体装置を生産性良く製造す
ることができる。
According to the above means (7), a wiring board (wiring frame) formed mainly of a transparent resin film
Since manufacturing can be performed in the same manner as in the semiconductor device manufacturing technology using a lead frame which has been established conventionally, it is possible to manufacture a high quality HGA type semiconductor device having a folded and superposed structure with high productivity.

【0038】(半導体装置の実装方法)前記(8)の手
段によれば、(a)外部端子が設けられる実装本体部の
配線板(可撓性配線板)が透明体となっていることか
ら、外部端子を実装基板のランドに重ね合わせる際、ラ
ンドと外部端子の重なり具合を目視観察できるため、位
置合わせが正確かつ容易となる。
(Semiconductor Device Mounting Method) According to the means (8), (a) the wiring board (flexible wiring board) of the mounting main body portion on which the external terminals are provided is a transparent body. When the external terminals are superposed on the lands of the mounting board, the degree of overlap between the lands and the external terminals can be visually observed, so that the alignment can be accurately and easily performed.

【0039】(b)外部端子が設けられる実装本体部の
配線板(可撓性配線基板)が透明体となっていることか
ら、外部端子とランドとの半田付け状態を目視検査でき
るため、実装の良否検査が容易となるとともに、実装の
信頼性を高めることができる。
(B) Since the wiring board (flexible wiring board) of the mounting main body portion on which the external terminals are provided is a transparent body, the soldering state of the external terminals and the lands can be visually inspected. The quality inspection can be facilitated and the mounting reliability can be improved.

【0040】(c)半導体装置の半導体チップを搭載し
た重畳部は、実装後外部端子が配置された実装本体部上
に重ねれば良いことから、実装本体部には中央部分をも
含めて全域に外部端子を配置できるため半導体装置は小
型となり、実装面積の縮小化が達成できる。
(C) Since the superposed portion on which the semiconductor chip of the semiconductor device is mounted may be superposed on the mounting main body portion on which the external terminals are arranged after mounting, the mounting main body portion includes the entire area including the central portion. Since the external terminals can be arranged on the semiconductor device, the semiconductor device can be downsized, and the mounting area can be reduced.

【0041】前記(9)の手段によれば、(a)実装は
実装本体部のスルーホール内に外部端子とランドを接続
する接合材が吸い上げられているか否かを目視等で確認
することによって行えるため、実装の良否検査が正確か
つ容易となる。
According to the means (9), (a) mounting is performed by visually confirming whether or not the bonding material for connecting the external terminal and the land is sucked up in the through hole of the mounting body. Since it can be performed, the quality inspection of mounting becomes accurate and easy.

【0042】(b)実装後スルーホール内に吸い上げら
れた接合材にプローブ・ピンを当ててインサーキット・
テスト等の電気特性検査を行うことができる。
(B) After mounting, apply a probe pin to the bonding material sucked up in the through hole and apply in-circuit
It is possible to perform an electrical characteristic inspection such as a test.

【0043】(c)半導体装置の半導体チップを搭載し
た重畳部は、実装後外部端子が配置された実装本体部上
に重ねれば良いことから、実装本体部には中央部分をも
含めて全域に外部端子を配置できるため半導体装置は小
型となり、実装面積の縮小化が達成できる。
(C) Since the superposed portion on which the semiconductor chip of the semiconductor device is mounted may be superposed on the mounting main body portion on which the external terminals are arranged after mounting, the mounting main body portion includes the entire area including the central portion. Since the external terminals can be arranged on the semiconductor device, the semiconductor device can be downsized, and the mounting area can be reduced.

【0044】[0044]

【発明の実施の形態】以下、図面を参照して本発明の実
施の形態を詳細に説明する。なお、発明の実施の形態を
説明するための全図において、同一機能を有するものは
同一符号を付け、その繰り返しの説明は省略する。
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

【0045】(実施形態1)図1乃至図6は本発明の一
実施形態(実施形態1)の半導体装置を示す図であり、
図1は半導体装置の外観を示す斜視図、図2は重畳部を
半開き状態とした半導体装置の模式的斜視図、図3は半
導体装置の正面図、図4は展開状態の半導体装置を示す
模式的底面図、図5は展開状態の半導体装置において封
止体の一部を除いた状態を示す模式的底面図、図6は展
開状態の半導体装置の一部を示す拡大断面図である。
(Embodiment 1) FIGS. 1 to 6 are views showing a semiconductor device according to an embodiment (Embodiment 1) of the present invention.
1 is a perspective view showing the external appearance of a semiconductor device, FIG. 2 is a schematic perspective view of a semiconductor device in which a superposed portion is in a half-opened state, FIG. 3 is a front view of the semiconductor device, and FIG. 4 is a schematic diagram of the semiconductor device in a developed state. FIG. 5 is a schematic bottom view showing a state in which a part of the sealing body is removed in the semiconductor device in a developed state, and FIG. 6 is an enlarged cross-sectional view showing a part of the semiconductor device in a developed state.

【0046】本実施形態1の半導体装置は、表面実装型
の半導体装置となり、下面にバンプ状の外部端子を複数
列格子状に配置したグリッドアレイ構造となり、従来の
BGA型半導体装置と同様な構造となっている。
The semiconductor device according to the first embodiment is a surface-mounting type semiconductor device, and has a grid array structure in which bump-shaped external terminals are arranged in a plurality of rows in a grid pattern on the lower surface, which is similar to the conventional BGA type semiconductor device. Has become.

【0047】本実施形態1の半導体装置1は、外観的に
は図1および図2に示すように、可撓性(フレキシブ
ル)の配線板(配線基板)2を中間の折返部3で折り返
した構造となっている。積層されたもののうち、下部は
実装本体部4を形成し、その下面には半田で形成された
複数の外部端子6がグリッドアレイ状に設けられてい
る。また、上部は重畳部5を形成し、上面には半導体チ
ップ等を封止した封止体7が設けられている。
In the semiconductor device 1 of the first embodiment, as shown in FIGS. 1 and 2 in appearance, a flexible wiring board (wiring board) 2 is folded back at an intermediate folding portion 3. It has a structure. The lower part of the stacked ones forms the mounting main body 4, and a plurality of external terminals 6 formed of solder are provided in a grid array on the lower surface thereof. In addition, a superposed portion 5 is formed on the upper portion, and a sealing body 7 encapsulating a semiconductor chip or the like is provided on the upper surface.

【0048】可撓性の配線板(可撓性配線基板)2は、
図4〜図6に示すように絶縁性の透明(光透過性)の樹
脂フィルム8と、この樹脂フィルム8の裏面に形成され
た所望パターンの配線10と、前記配線10を部分的に
被う絶縁性の保護膜13とからなっている。前記樹脂フ
ィルム8は、たとえばポリイミドフィルムで形成されて
いる。また、配線10は酸化錫と酸化アンチモンの化合
物からなる透明な膜で形成されている。この配線10は
ポリイミドフィルムの表面に酸化錫と酸化アンチモンの
化合物を蒸着した後所望のパターンにエッチングするこ
とによって形成される。また、前記保護膜13はポリイ
ミド樹脂によって形成されている。
The flexible wiring board (flexible wiring board) 2 is
As shown in FIGS. 4 to 6, an insulating transparent (light-transmitting) resin film 8, a wiring 10 having a desired pattern formed on the back surface of the resin film 8, and the wiring 10 partially covered. It is composed of an insulating protective film 13. The resin film 8 is formed of, for example, a polyimide film. The wiring 10 is formed of a transparent film made of a compound of tin oxide and antimony oxide. The wiring 10 is formed by depositing a compound of tin oxide and antimony oxide on the surface of a polyimide film and then etching it into a desired pattern. The protective film 13 is made of polyimide resin.

【0049】配線10は前記実装本体部4から折返部3
を通って重畳部5に亘って延在している。重畳部5で
は、配線10の先端は可撓性配線基板2に接着剤11を
介して固定される半導体チップ12の近傍に延在してい
る。また、実装本体部4では、配線10の先端部分には
半田バンプ電極からなる外部端子6が固定されている。
なお、図4および図5では、一部の外部端子6から配線
10を延在させ、他部の外部端子6からは配線10を延
在させてないが、実際は全ての外部端子6から配線10
が重畳部5に向かって延在している(以下、同様の図で
も同じ)。
The wiring 10 is formed from the mounting body 4 to the folded portion 3
And extends over the overlapping portion 5. In the overlapping portion 5, the tip of the wiring 10 extends in the vicinity of the semiconductor chip 12 fixed to the flexible wiring board 2 with an adhesive 11. Further, in the mounting main body 4, an external terminal 6 made of a solder bump electrode is fixed to a tip portion of the wiring 10.
4 and 5, the wiring 10 is extended from a part of the external terminals 6 and the wiring 10 is not extended from the external terminals 6 of other parts, but in reality, the wiring 10 is extended from all the external terminals 6.
Extend toward the superimposing portion 5 (hereinafter, the same applies to the same drawings).

【0050】半導体チップ12は、前述のように接着剤
11を介して可撓性配線基板2に固定されている。ま
た、半導体チップ12の電極と、この半導体チップ12
に近接する配線10の先端部分は、導電性のワイヤ14
によって電気的に接続されている。
The semiconductor chip 12 is fixed to the flexible wiring board 2 via the adhesive 11 as described above. In addition, the electrodes of the semiconductor chip 12 and the semiconductor chip 12
The tip portion of the wiring 10 close to the
Are electrically connected by

【0051】また、前記半導体チップ12を取り囲むよ
うに絶縁性のプラスチックからなる矩形体の樹脂流れ止
め枠15が絶縁性の接着剤16を介して可撓性配線基板
2に固定されている。この樹脂流れ止め枠15内には所
定の厚さに絶縁性の樹脂17が充填されて封止体7が形
成されている。前記封止体7は前記半導体チップ12や
ワイヤ14を封止している。
A rectangular resin flow stop frame 15 made of insulating plastic is fixed to the flexible wiring board 2 via an insulating adhesive 16 so as to surround the semiconductor chip 12. The resin flow stop frame 15 is filled with an insulating resin 17 with a predetermined thickness to form the sealing body 7. The sealing body 7 seals the semiconductor chip 12 and the wires 14.

【0052】本実施形態1において、前記実装本体部4
に積み重ねられる重畳部5は、実装本体部4に重ねただ
けの状態でも良いが、その取扱時、重畳部5が動かない
ようにするため、接着テープや接着剤によって実装本体
部4に仮固定させておく(固定手段)と良い。
In the first embodiment, the mounting body 4
The stacking portion 5 to be stacked on the mounting body portion 4 may be simply stacked on the mounting body portion 4. However, in order to prevent the stacking portion 5 from moving during handling, it is temporarily fixed to the mounting body portion 4 with an adhesive tape or an adhesive. It is better to let it (fixing means).

【0053】また、本実施形態1の半導体装置1は、図
3に示すように、重畳部5を開いて実装本体部4,折返
部3,重畳部5を同一平面上に展開した状態で保管する
こともできる。
Further, the semiconductor device 1 of the first embodiment is stored in a state in which the overlapping portion 5 is opened and the mounting body portion 4, the folding portion 3, and the overlapping portion 5 are developed on the same plane as shown in FIG. You can also do it.

【0054】本実施形態1の半導体装置1においては、
前記可撓性配線基板2は透明体で形成されている。この
ため、図2および図3に示すように、折返部3を中心に
重畳部5を開いて重畳部5を実装本体部4上から外した
状態では、可撓性配線基板2を通して可撓性配線基板2
の裏面に設けられた外部端子6を目視することができ
る。図2では、可撓性配線基板2を通して目視できる外
部端子6の状態をハッチングを施して示す(以下、平面
図および底面図でハッチングを施した配線10部分は外
部端子6を指す)。
In the semiconductor device 1 of the first embodiment,
The flexible wiring board 2 is formed of a transparent body. Therefore, as shown in FIGS. 2 and 3, when the overlapping portion 5 is opened around the folded-back portion 3 and the overlapping portion 5 is removed from the mounting main body portion 4, the flexible wiring board 2 is flexible. Wiring board 2
The external terminal 6 provided on the back surface of the can be visually observed. In FIG. 2, the state of the external terminals 6 that can be visually seen through the flexible wiring board 2 is shown by hatching (hereinafter, the hatched wiring 10 portion in the plan view and the bottom view indicates the external terminals 6).

【0055】つぎに、本実施形態1の半導体装置1の製
造方法について説明する。
Next, a method of manufacturing the semiconductor device 1 according to the first embodiment will be described.

【0056】図7乃至図12は本実施形態1の半導体装
置の製造方法に係わる図であって、図7は製造に使用す
る配線フレームの模式的平面図、図8は樹脂流れ止め枠
を固定した配線フレームを示す模式的平面図、図9は配
線フレームに半導体チップを固定した状態を示す模式的
平面図、図10はワイヤボンディングがなされた配線フ
レームを示す模式的平面図、図11は封止体が形成され
た配線フレームを示す模式的平面図、図12は外部端子
が形成された配線フレームを示す模式的平面図である。
7 to 12 are views relating to the method for manufacturing the semiconductor device of the first embodiment. FIG. 7 is a schematic plan view of a wiring frame used for manufacturing, and FIG. 8 is a resin flow stop frame fixed. 9 is a schematic plan view showing the formed wiring frame, FIG. 9 is a schematic plan view showing a state where a semiconductor chip is fixed to the wiring frame, FIG. 10 is a schematic plan view showing a wiring frame to which wire bonding is performed, and FIG. 11 is a seal. FIG. 12 is a schematic plan view showing a wiring frame on which a stopper is formed, and FIG. 12 is a schematic plan view showing a wiring frame on which external terminals are formed.

【0057】最初に配線フレーム20を用意する。この
配線フレーム20は、可撓性の透明なポリイミドフィル
ムに配線を形成した配線板となり、単位パターンは図7
に示すように、細長矩形状の可撓性配線基板部21と、
この可撓性配線基板部21の外側に延在する矩形枠状の
フレーム部22と、前記フレーム部22と配線フレーム
20とを接続する吊り部23とからなっている。吊り部
23は、可撓性配線基板部21の4隅と可撓性配線基板
部21の一対の長辺の中央にそれぞれ設けられている。
配線フレーム20のパターンは、ポリイミドフィルムを
プレスによって打ち抜くことによって形成される。ま
た、必要ならば、前記フレーム部22の縁に沿って、ガ
イド孔や位置決め孔を設けておいても良い。また、製造
においては、前記配線フレーム20は多連フレーム状あ
るいはテープ状であっても良い。
First, the wiring frame 20 is prepared. The wiring frame 20 is a wiring board in which wiring is formed on a flexible transparent polyimide film, and the unit pattern is as shown in FIG.
As shown in FIG.
The flexible wiring board portion 21 includes a frame portion 22 having a rectangular frame shape extending outside and a suspension portion 23 connecting the frame portion 22 and the wiring frame 20. The hanging portions 23 are provided at four corners of the flexible wiring board portion 21 and at the centers of a pair of long sides of the flexible wiring board portion 21, respectively.
The pattern of the wiring frame 20 is formed by punching a polyimide film with a press. If necessary, guide holes and positioning holes may be provided along the edge of the frame portion 22. Further, in manufacturing, the wiring frame 20 may be in the form of multiple frames or a tape.

【0058】前記可撓性配線基板部21は、中央部分が
折返部3、その左側の矩形部分が実装本体部4、その右
側の矩形部分が重畳部5となる。折返部3部分は前記吊
り部23で吊られている。
In the flexible wiring board portion 21, the central portion is the folding portion 3, the left side rectangular portion is the mounting body portion 4, and the right side rectangular portion is the overlapping portion 5. The folded-back portion 3 part is suspended by the suspension portion 23.

【0059】前記可撓性配線基板部21には、図7に示
すように、配線10が設けられている。この配線10
は、絶縁性の樹脂フィルム8、たとえば、ポリイミドフ
ィルム8の表面に、酸化錫と酸化アンチモンの化合物を
蒸着した後所望のパターンにエッチングすることによっ
て形成される。配線10は実装本体部4から折返部3を
通って重畳部5にまで到達している。
Wirings 10 are provided on the flexible wiring board portion 21, as shown in FIG. This wiring 10
Is formed by vapor-depositing a compound of tin oxide and antimony oxide on the surface of an insulating resin film 8, for example, a polyimide film 8, and then etching it into a desired pattern. The wiring 10 reaches the overlapping portion 5 from the mounting body portion 4 through the folding portion 3.

【0060】重畳部5の中央の矩形部分は半導体チップ
搭載領域となるが、前記配線10の先端は、この半導体
チップ搭載領域に向かって先端を臨ませるパターンとな
っている。また、実装本体部4においては、配線10の
先端は、円形のバンプ電極用の台座24を形成するよう
になっている。これら台座24はグリッドアレイ状に配
置されている。
The rectangular portion at the center of the superposed portion 5 becomes a semiconductor chip mounting area, but the tip of the wiring 10 has a pattern in which the tip faces the semiconductor chip mounting area. In addition, in the mounting body 4, the tip of the wiring 10 forms a pedestal 24 for the bump electrode, which is circular. These pedestals 24 are arranged in a grid array.

【0061】また、前記配線10においては、半導体チ
ップ搭載領域に望む先端部分および台座24を除く部分
は、ポリイミド樹脂からなる絶縁性の保護膜13で被わ
れている(図6参照、図6および図27以外では保護膜
13は省略)。
Further, in the wiring 10, a portion except the tip portion and the pedestal 24 desired in the semiconductor chip mounting region is covered with an insulating protective film 13 made of a polyimide resin (see FIGS. 6, 6 and 6). The protective film 13 is omitted except for FIG. 27).

【0062】つぎに、図8に示すように、配線フレーム
20の可撓性配線基板部21の重畳部5に樹脂流れ止め
枠15を接着剤16を介して固定する(図6参照)。す
なわち、半導体チップ搭載領域を囲むように樹脂フィル
ム8に絶縁性のプラスチックからなる樹脂流れ止め枠1
5を固定する。前記樹脂流れ止め枠15の内側には、配
線10の先端部分が延在する。前記樹脂流れ止め枠15
は、後に行う樹脂封止の際、溶けた樹脂の流出を防止す
る働きをする。
Next, as shown in FIG. 8, the resin flow stop frame 15 is fixed to the overlapping portion 5 of the flexible wiring board portion 21 of the wiring frame 20 with the adhesive 16 (see FIG. 6). That is, the resin flow stop frame 1 made of insulating plastic is formed on the resin film 8 so as to surround the semiconductor chip mounting area.
5 is fixed. The tip portion of the wiring 10 extends inside the resin flow stop frame 15. The resin flow stop frame 15
Has a function of preventing melted resin from flowing out at the time of resin sealing performed later.

【0063】つぎに、図9に示すように、重畳部5の中
央の半導体チップ搭載領域に半導体チップ12を接着剤
11を介して固定する(図6参照)。この場合、半導体
チップ12を接着テープを用いて樹脂フィルム8に固定
しても良い。
Next, as shown in FIG. 9, the semiconductor chip 12 is fixed to the central semiconductor chip mounting region of the overlapping portion 5 with the adhesive 11 (see FIG. 6). In this case, the semiconductor chip 12 may be fixed to the resin film 8 using an adhesive tape.

【0064】つぎに、図10に示すように、ワイヤボン
ディングを行い、前記半導体チップ12の図示しない電
極と、半導体チップ12に近接する配線10の先端部分
を導電性のワイヤ14で接続する(図6参照)。
Next, as shown in FIG. 10, wire bonding is performed to connect the electrode (not shown) of the semiconductor chip 12 and the tip of the wiring 10 adjacent to the semiconductor chip 12 with a conductive wire 14 (FIG. 6).

【0065】つぎに、図11に示すように、前記樹脂流
れ止め枠15内の樹脂フィルム8上に樹脂17を充填し
て硬化させて封止体7を形成する。これによって、半導
体チップ12,ワイヤ14および樹脂流れ止め枠15内
の配線10等は、封止体7で封止される(図6参照)。
Next, as shown in FIG. 11, the resin 17 is filled on the resin film 8 in the resin flow stop frame 15 and cured to form the sealing body 7. As a result, the semiconductor chip 12, the wires 14, and the wiring 10 and the like in the resin flow stop frame 15 are sealed with the sealing body 7 (see FIG. 6).

【0066】つぎに、図12に示すように、配線10の
実装本体部4側の先端の台座24上に半田ボールを載せ
て溶融させ、バンプ電極となる外部端子6を形成する
(図6参照)。
Next, as shown in FIG. 12, a solder ball is placed on the pedestal 24 at the tip of the mounting body 4 side of the wiring 10 and melted to form the external terminal 6 to be a bump electrode (see FIG. 6). ).

【0067】つぎに、前記配線フレーム20において、
吊り部23を矩形状の可撓性配線基板部21の縁に沿っ
て切断し、図4に示すように可撓性配線基板2からな
り、実装本体部4,折返部3,重畳部5とからなる半導
体装置1を製造する。
Next, in the wiring frame 20,
The hanging portion 23 is cut along the edge of the rectangular flexible wiring board portion 21, and is composed of the flexible wiring board 2 as shown in FIG. 4, and includes the mounting body portion 4, the folding portion 3, and the overlapping portion 5. The semiconductor device 1 is manufactured.

【0068】本実施形態1の半導体装置1は、図3に示
すように、重畳部5を開いて実装本体部4,折返部3,
重畳部5を同一平面上に展開した状態で保管しても良
く、また、図1に示すように、重畳部5を折返部3の部
分で折り返して実装本体部4に重ねた状態で保管しても
良い。なお、積み重ねた状態で半導体装置1を保管する
場合、重畳部5が実装本体部4からずれるのを嫌う場合
は、重畳部5を実装本体部4に対して接着テープ(弱粘
着性テープ)や接着剤(弱粘着性接着剤)で仮固定させ
ておくと良い。
As shown in FIG. 3, the semiconductor device 1 according to the first embodiment opens the overlapping portion 5 and mounts the mounting body portion 4, the folding portion 3, and the folding portion 3.
The overlapping portion 5 may be stored in a state of being developed on the same plane, or, as shown in FIG. 1, the overlapping portion 5 may be folded back at the folding portion 3 and stored in a state of being stacked on the mounting main body portion 4. May be. If the semiconductor devices 1 are stored in a stacked state and the disposition of the overlapping portion 5 from the mounting body portion 4 is disliked, the overlapping portion 5 may be attached to the mounting body portion 4 with an adhesive tape (weak adhesive tape) or It is advisable to temporarily fix it with an adhesive (weakly adhesive).

【0069】つぎに、本実施形態1の半導体装置1の実
装について説明する。図13乃至図15は本実施形態1
の半導体装置の実装状態を示す図であり、図13は半導
体装置の実装開始状態を示す模式図、図14は半田付け
後重畳部を途中まで反転させた状態の半導体装置を示す
正面図、図15は半田付け後重畳部を実装本体部に重ね
合わせた状態を示す半導体装置の正面図である。
Next, mounting of the semiconductor device 1 according to the first embodiment will be described. 13 to 15 show the first embodiment.
FIG. 13 is a view showing a mounted state of the semiconductor device, FIG. 13 is a schematic view showing a mounted start state of the semiconductor device, FIG. 14 is a front view showing the semiconductor device in a state in which a superposed portion is partially inverted after soldering, FIG. 15 is a front view of the semiconductor device showing a state where the superposed portion is superposed on the mounting main body portion after soldering.

【0070】本実施形態1の半導体装置1を実装基板3
0に実装する際、図13に示すように、半導体装置1を
展開状態にして実装基板30のランド(配線)31上に
実装本体部4の外部端子6を重ね、外部端子6を一時的
に加熱して溶解(半田リフロー処理)することによって
外部端子6をランド31に固定できる。
The semiconductor device 1 according to the first embodiment is mounted on the mounting substrate 3
13, the semiconductor device 1 is expanded and the external terminals 6 of the mounting body 4 are overlapped on the lands (wiring) 31 of the mounting substrate 30 to temporarily mount the external terminals 6 as shown in FIG. The external terminal 6 can be fixed to the land 31 by heating and melting (solder reflow processing).

【0071】外部端子6をランド31上に正確に重ねる
位置決め作業は、可撓性配線基板2が透明体となってい
ることから、可撓性配線基板2を通してランド31およ
び外部端子6を目視できるため、容易かつ正確に行え
る。また、半田リフロー処理後のランド31と外部端子
6との接続の良否検査も可撓性配線基板2を通して目視
できるので、実装の良否の検査が容易かつ確実となる。
Since the flexible wiring board 2 is a transparent body, the land 31 and the external terminals 6 can be visually observed through the flexible wiring board 2 in the positioning work for accurately stacking the external terminals 6 on the lands 31. Therefore, it can be performed easily and accurately. Further, since the quality inspection of the connection between the land 31 and the external terminal 6 after the solder reflow process can be visually confirmed through the flexible wiring board 2, the quality inspection of the mounting is easy and reliable.

【0072】半田付け状態が悪い場合、あるいは半田ブ
リッジ等の不良現象が発生している場合は、実装した半
導体装置1を取り外し、再度新たな半導体装置1の実装
を行う。
When the soldering condition is poor or when a defective phenomenon such as a solder bridge occurs, the mounted semiconductor device 1 is removed and a new semiconductor device 1 is mounted again.

【0073】透明な可撓性配線基板2を通して可撓性配
線基板2の裏面の外部端子6を目視できる状態を図2に
示す。同図には、透視像として外部端子6のみをハッチ
ングを施して表示してある。
FIG. 2 shows a state in which the external terminals 6 on the back surface of the flexible wiring board 2 can be viewed through the transparent flexible wiring board 2. In the figure, only the external terminal 6 is hatched and shown as a perspective image.

【0074】つぎに、図14および図15に示すよう
に、重畳部5を矢印のように反転させ、重畳部5を実装
本体部4上に重ねる。この際、接着剤や接着テープを使
用して重畳部5を実装本体部4に固定する。この固定は
必要に応じて重畳部5を実装本体部4から剥離できる固
定でも良い。この場合、重畳部5が実装本体部4から剥
離できるため、必要に応じてランド31と外部端子6の
半田付け状態を確認できることになる。
Next, as shown in FIGS. 14 and 15, the superposition section 5 is inverted as indicated by the arrow, and the superposition section 5 is superposed on the mounting main body section 4. At this time, the overlapping portion 5 is fixed to the mounting body portion 4 using an adhesive or an adhesive tape. This fixing may be fixed so that the overlapping portion 5 can be separated from the mounting main body portion 4 if necessary. In this case, since the overlapping portion 5 can be peeled off from the mounting body portion 4, the soldering state of the land 31 and the external terminal 6 can be confirmed as necessary.

【0075】本実施形態1の半導体装置1は、下面に外
部端子6を有する実装本体部4の上に重畳部5を折返部
3で折り返して重ねる構造となっていることと、実装本
体部4,折返部3,重畳部5と連なる部分は透明の可撓
性配線基板2で形成されていることから、重畳部5を実
装本体部4に重ねない状態では可撓性配線基板2の裏面
の外部端子6を目視できる。
The semiconductor device 1 according to the first embodiment has a structure in which the overlapping portion 5 is folded back by the folding portion 3 and overlapped on the mounting body portion 4 having the external terminals 6 on the lower surface, and the mounting body portion 4 Since the portion connected to the folded-back portion 3 and the overlapping portion 5 is formed of the transparent flexible wiring board 2, the rear surface of the flexible wiring substrate 2 is not overlapped with the mounting body portion 4. The external terminal 6 can be visually observed.

【0076】したがって、半導体装置1を実装基板に実
装した状態でも、実装本体部4に重畳部5を重ねない状
態で可撓性配線基板2を通して可撓性配線基板2の裏面
の外部端子6の半田付け状態を目視で観察できるため、
半田付けの良否を容易かつ正確に検査することができ
る。
Therefore, even when the semiconductor device 1 is mounted on the mounting board, the external terminals 6 on the rear surface of the flexible wiring board 2 are passed through the flexible wiring board 2 without the overlapping portion 5 overlapping the mounting body 4. Since the soldering state can be visually observed,
It is possible to easily and accurately inspect the quality of soldering.

【0077】また、半導体チップを搭載した重畳部5
は、実装後外部端子6が配置された実装本体部4上に重
ねれば良いことから、実装本体部4には中央部分をも含
めて全域に外部端子6を配置でき、半導体装置1の小型
化および実装面積の縮小化を図ることができる。
Further, the superposing section 5 on which the semiconductor chip is mounted
Can be placed on the mounting body 4 on which the external terminals 6 are mounted after mounting, so that the external terminals 6 can be arranged in the entire mounting body 4 including the central portion, and the semiconductor device 1 can be compact. And the mounting area can be reduced.

【0078】すなわち、従来の表面実装型導体装置で、
外部端子の半田付け状態(実装状態)を目視できるよう
にするため基板を透明体としたものや、実装部分をスル
ーホールとして半田の吸い上がり状態から半田付け(実
装)の良否を検査するものであっても、半導体チップを
取り付ける基板部分には外部端子を設けることができな
いが、本実施形態1の半導体装置では、半導体チップの
搭載部分に対応する実装本体部4にも外部端子6を設け
ることができるため、半導体装置1の小型化および多ピ
ン化が達成できることになる。
That is, in the conventional surface mount type conductor device,
The board is made transparent so that the soldering status (mounting status) of the external terminals can be visually checked, and the quality of soldering (mounting) is checked from the sucked up status of the solder by using the mounting part as a through hole. Even if there is, the external terminal cannot be provided on the substrate portion to which the semiconductor chip is attached. However, in the semiconductor device of the first embodiment, the external terminal 6 is also provided on the mounting body portion 4 corresponding to the mounting portion of the semiconductor chip. Therefore, the semiconductor device 1 can be downsized and the number of pins can be increased.

【0079】本実施形態1の半導体装置1は、実装本体
部4の下面に半田によってバンプ電極を形成する際、バ
ンプ電極形成後、実装本体部4のみを薬品に浸け、半導
体チップが搭載された重畳部5を薬品に浸けないように
できる構造となっていることから、半田フラックスを使
用する半田を用いてバンプ電極を形成することができる
ため、半導体装置1の製造コストの低減が達成できる。
In the semiconductor device 1 of the first embodiment, when the bump electrodes are formed on the lower surface of the mounting body 4 by soldering, only the mounting body 4 is dipped in a chemical after the bump electrodes are formed, and the semiconductor chip is mounted. Since the overlapping portion 5 is structured so as not to be soaked in a chemical, the bump electrode can be formed by using the solder that uses the solder flux, so that the manufacturing cost of the semiconductor device 1 can be reduced.

【0080】すなわち、配線基板の下面に外部端子を設
けた従来のBGA型半導体装置の場合、配線基板の下面
の外部端子(バンプ電極)を薬品で洗浄して半田フラッ
クスを除去しようとすると、配線基板の上面のパッケー
ジ部分にも薬品が付き易く薬品洗浄ができないため、バ
ンプ電極形成コストが高くなる半田フラックスを使用し
ない無洗浄タイプの半田を使用せざるを得ない。しか
し、本実施形態1の半導体装置1では、重畳部5をクラ
ンプし、外部端子6(バンプ電極)が形成された実装本
体部4のみを薬品中に浸けて半田フラックスの洗浄除去
処理を行うことができる。
That is, in the case of the conventional BGA type semiconductor device in which the external terminals are provided on the lower surface of the wiring board, when the external terminals (bump electrodes) on the lower surface of the wiring board are cleaned with chemicals to remove the solder flux, the wiring Since the chemicals easily adhere to the package portion on the upper surface of the substrate and chemical cleaning cannot be performed, it is unavoidable to use a non-cleaning type solder that does not use solder flux, which increases the cost of forming bump electrodes. However, in the semiconductor device 1 according to the first embodiment, the overlapping portion 5 is clamped, and only the mounting main body portion 4 on which the external terminals 6 (bump electrodes) are formed is immersed in the chemical to perform the solder flux cleaning and removing process. You can

【0081】本実施形態1による半導体装置の製造方法
では、透明なポリイミドフィルム(樹脂フィルム)8を
主体として形成された配線板(配線フレーム20)を用
い、従来確立されたリードフレームによる半導体装置製
造技術と同様に製造が行えるため、高品質の折り返し重
畳構造のBGA型半導体装置を生産性良く製造すること
ができる。
In the method of manufacturing the semiconductor device according to the first embodiment, the wiring board (wiring frame 20) formed mainly of the transparent polyimide film (resin film) 8 is used, and the semiconductor device is manufactured by the conventionally established lead frame. Since the manufacturing can be performed in the same manner as the technology, it is possible to manufacture a high quality BGA type semiconductor device having a folded and superposed structure with high productivity.

【0082】また、製造された半導体装置1は、重畳部
5が外部端子6に接着剤や接着テープで仮固定されるた
め、取扱性が優れた半導体装置となる。
Further, the manufactured semiconductor device 1 is a semiconductor device having excellent handleability because the overlapping portion 5 is temporarily fixed to the external terminal 6 with an adhesive or an adhesive tape.

【0083】本実施形態1の半導体装置1の実装方法に
おいては、外部端子6が設けられる実装本体部4の配線
板(可撓性配線基板)2が透明体となっていることか
ら、外部端子6を実装基板30のランド31に重ね合わ
せる際、ランド31と外部端子6の重なり具合を目視観
察できるため、位置合わせが正確かつ容易となる。
In the method of mounting the semiconductor device 1 of the first embodiment, since the wiring board (flexible wiring board) 2 of the mounting body 4 on which the external terminal 6 is provided is a transparent body, the external terminal When the 6 is overlaid on the land 31 of the mounting substrate 30, the degree of overlap between the land 31 and the external terminal 6 can be visually observed, so that the alignment can be accurately and easily performed.

【0084】本実施形態1の半導体装置1の実装方法に
おいては、外部端子6が設けられる実装本体部4の配線
板(可撓性配線基板)2が透明体となっていることか
ら、外部端子6とランド31との半田付け状態を目視検
査できるため、実装の良否検査が容易となるとともに、
実装の信頼性を高めることができる。
In the method of mounting the semiconductor device 1 according to the first embodiment, since the wiring board (flexible wiring board) 2 of the mounting body 4 on which the external terminal 6 is provided is a transparent body, the external terminal Since the soldering state of the 6 and the land 31 can be visually inspected, the quality of the mounting can be easily inspected and
The reliability of implementation can be improved.

【0085】本実施形態1の半導体装置1の実装におい
ては、半導体装置1の半導体チップを搭載した重畳部5
は、実装後外部端子6が配置された実装本体部4上に重
ねれば良いことから、実装本体部4には中央部分をも含
めて全域に外部端子6を配置できるため半導体装置1は
小型となり、実装面積の縮小化が達成できる。
In the mounting of the semiconductor device 1 of the first embodiment, the superposition section 5 on which the semiconductor chip of the semiconductor device 1 is mounted is mounted.
Can be placed on the mounting body 4 on which the external terminals 6 are mounted after mounting, so that the external terminals 6 can be arranged in the entire mounting body 4 including the central portion, so that the semiconductor device 1 is small. Therefore, the mounting area can be reduced.

【0086】なお、本実施形態1の半導体装置1は、実
装時、必ずしも実装本体部4上に重畳部5を積み重ねる
構造としなくとも良い。すなわち、図14に示すよう
に、重畳部5を上方に直立させるようにした状態として
も良い。この場合、重畳部5は支持体(保持具)等によ
って支持する必要がある。このような実装構造では、可
撓性配線基板2を通して常時外部端子6の半田付け状態
を目視確認することができるとともに、重畳部5の表裏
面が大気と接していることから、放熱効果が高くなる。
It should be noted that the semiconductor device 1 of Embodiment 1 does not necessarily have a structure in which the superposing portion 5 is stacked on the mounting main body portion 4 at the time of mounting. That is, as shown in FIG. 14, the overlapping portion 5 may be upright upward. In this case, the overlapping portion 5 needs to be supported by a support (holder) or the like. In such a mounting structure, the soldering state of the external terminals 6 can always be visually confirmed through the flexible wiring board 2, and since the front and back surfaces of the overlapping portion 5 are in contact with the atmosphere, the heat dissipation effect is high. Become.

【0087】(実施形態2)図16および図17は本発
明の他の実施形態(実施形態2)である半導体装置に係
わる図であり、図16は半導体装置の斜視図、図17は
展開状態の半導体装置の模式的底面図である。
(Second Embodiment) FIGS. 16 and 17 are views relating to a semiconductor device according to another embodiment (second embodiment) of the present invention. FIG. 16 is a perspective view of the semiconductor device, and FIG. 17 is a developed state. 3 is a schematic bottom view of the semiconductor device of FIG.

【0088】本実施形態2の半導体装置1は、重畳部5
を実装本体部4に着脱自在に固定できる固定手段を有す
るものである。すなわち、図17に示すように、実装本
体部4の両側に嵌合孔35を有する嵌合雌部36を張り
出し形成しておくとともに、これら嵌合雌部36に対応
して重畳部5の両側に前記嵌合孔35に挿入嵌合する突
子37を形成しておく。
The semiconductor device 1 according to the second embodiment has the superposition section 5
It has a fixing means capable of removably fixing it to the mounting body 4. That is, as shown in FIG. 17, the fitting female portions 36 having the fitting holes 35 are formed on both sides of the mounting body portion 4 so as to project, and both sides of the overlapping portion 5 corresponding to these fitting female portions 36 are formed. A protrusion 37 that is inserted and fitted in the fitting hole 35 is formed in advance.

【0089】そして、図16に示すように、重畳部5を
折返部3で折り返して実装本体部4上に重畳部5を重ね
合わせた後、前記嵌合雌部36を引っ張って曲げ、突子
37を嵌合孔35に挿入嵌合させる。これによって、重
畳部5は実装本体部4に固定されることになり、移動し
ても重畳部5が実装本体部4から外れることがなく取扱
性が向上する。
Then, as shown in FIG. 16, the overlapping portion 5 is folded back at the folding portion 3 and the overlapping portion 5 is overlapped on the mounting main body portion 4, and then the fitting female portion 36 is pulled and bent to form a protrusion. 37 is inserted and fitted in the fitting hole 35. As a result, the overlapping portion 5 is fixed to the mounting body portion 4, and even if the overlapping portion 5 moves, the overlapping portion 5 does not come off from the mounting body portion 4, and the handleability is improved.

【0090】(実施形態3)図18および図19は本発
明の他の実施形態(実施形態3)である半導体装置に係
わる図であり、図18は半導体装置の模式的正面図、図
19は展開状態の半導体装置の模式的正面図である。
(Embodiment 3) FIGS. 18 and 19 are views relating to a semiconductor device according to another embodiment (embodiment 3) of the present invention. FIG. 18 is a schematic front view of the semiconductor device, and FIG. It is a typical front view of the semiconductor device in a developed state.

【0091】本実施形態3の半導体装置1は、折返部3
に加わるストレスの緩和のため、折り返し形状規定手段
を設けて折返部3の曲率半径を大きくした構造となって
いる。
The semiconductor device 1 according to the third embodiment has the folding portion 3
In order to relieve the stress applied to the fold-back portion, the fold-back shape defining means is provided to increase the curvature radius of the fold-back portion 3.

【0092】すなわち、前記実施形態1では、配線10
および外部端子6ならびに半導体チップ12等を、可撓
性配線基板2の同一面に形成したものであり、重畳部5
を実装本体部4に折り返して積み重ねた場合、実装重畳
部5の可撓性配線基板2の部分が実装本体部4の可撓性
配線基板2の部分に直接接触する構造となり、折返部3
の曲率半径が小さくなり、折返部3に大きな力が作用す
る。
That is, in the first embodiment, the wiring 10
The external terminal 6, the semiconductor chip 12, and the like are formed on the same surface of the flexible wiring board 2, and the overlapping portion 5 is formed.
When the components are folded back and stacked on the mounting body 4, the portion of the flexible wiring board 2 of the mounting overlapping portion 5 comes into direct contact with the portion of the flexible wiring board 2 of the mounting body 4, and the folding portion 3
Has a smaller radius of curvature, and a large force acts on the folded portion 3.

【0093】そこで、本実施形態3の半導体装置1で
は、図19に示すように、可撓性配線基板2の一面側に
外部端子6を形成するとともに、可撓性配線基板2の他
面側に半導体チップ12や半導体チップ12を被う封止
体7や樹脂流れ止め枠15を形成する構造となってい
る。そして、図示はしないが、配線10は可撓性配線基
板2の両面に設けられている。この表裏の配線10は、
可撓性配線基板2に設けられたスルーホールに充填され
る導体を介して電気的に接続されている。
Therefore, in the semiconductor device 1 of the third embodiment, as shown in FIG. 19, the external terminals 6 are formed on one surface side of the flexible wiring board 2 and the other surface side of the flexible wiring board 2 is formed. In this structure, the semiconductor chip 12, the sealing body 7 covering the semiconductor chip 12, and the resin flow stop frame 15 are formed. Although not shown, the wiring 10 is provided on both surfaces of the flexible wiring board 2. The wiring 10 on the front and back is
The flexible wiring board 2 is electrically connected through a conductor filled in a through hole provided in the flexible wiring board 2.

【0094】本実施形態3の半導体装置1は、図18に
示すように、重畳部5を折返部3で折り返して実装本体
部4に重ねた状態では、実装本体部4の可撓性配線基板
2部分に封止体7(樹脂流れ止め枠15)が載り、その
上に重畳部5の可撓性配線基板2部分が位置するため、
可撓性配線基板2で形成される折返部3の曲率半径は大
きくなり、折返部3に大きな力が作用しなくなり、重畳
部5は部分的に浮き上がることもなく実装本体部4に密
着する。また、重畳部5を繰り返して折り返しても折返
部3が劣化することがない。
As shown in FIG. 18, the semiconductor device 1 of the third embodiment has the flexible wiring board of the mounting body 4 when the overlapping portion 5 is folded back at the folding portion 3 and overlapped with the mounting body 4. Since the sealing body 7 (resin flow stop frame 15) is placed on the two portions, and the flexible wiring board 2 portion of the overlapping portion 5 is located thereon,
The radius of curvature of the folded-back portion 3 formed of the flexible wiring board 2 becomes large, a large force does not act on the folded-back portion 3, and the overlapping portion 5 is brought into close contact with the mounting body portion 4 without being partially lifted. Further, even if the overlapping portion 5 is repeatedly folded back, the folded portion 3 does not deteriorate.

【0095】本実施形態3の半導体装置1は、実施形態
1の半導体装置1と同様に可撓性配線基板2を通して外
部端子6を目視できるとともに、多ピン化,小型化が図
れる。また、製造においては半田フラックスを使用する
半田を用いてバンプ電極を形成することができるため製
造コストの低減が達成できる。
As in the semiconductor device 1 of the first embodiment, the semiconductor device 1 of the third embodiment allows the external terminals 6 to be visually inspected through the flexible wiring board 2, and the number of pins and the size can be reduced. Further, in manufacturing, the bump electrode can be formed by using the solder using the solder flux, so that the manufacturing cost can be reduced.

【0096】(実施形態4)図20および図21は本発
明の他の実施形態(実施形態4)である半導体装置に係
わる図であり、図20は半導体装置の模式的正面図、図
21は展開状態の半導体装置の模式的正面図である。
(Fourth Embodiment) FIGS. 20 and 21 are views relating to a semiconductor device according to another embodiment (fourth embodiment) of the present invention. FIG. 20 is a schematic front view of the semiconductor device, and FIG. It is a typical front view of the semiconductor device in a developed state.

【0097】本実施形態4の半導体装置1は、折り返し
形状規定手段を設けて折返部3の折り返しによる曲率半
径が常に一定にできる構造、換言するならば、折返部3
の曲率半径を必要以上小さくせずに折返部3が繰り返し
の折り返しで破損し難くするものである。
The semiconductor device 1 according to the fourth embodiment has a structure in which the folded shape defining means is provided so that the radius of curvature of the folded portion 3 can be kept constant, in other words, the folded portion 3
The fold-back portion 3 is less likely to be damaged by repeated fold-backs without making the radius of curvature of the above-mentioned smaller than necessary.

【0098】本実施形態4の半導体装置1は、図21に
示すように、折返部3に円柱状の曲げ保持心棒40が接
着剤を介して固定されている。
In the semiconductor device 1 of Embodiment 4, as shown in FIG. 21, a columnar bending holding mandrel 40 is fixed to the folded-back portion 3 with an adhesive.

【0099】したがって、図20に示すように、重畳部
5を折返部3で折り返して実装本体部4に重ねた場合、
折返部3は曲げ保持心棒40の太さよりも小さい曲率半
径で折り返えされることはなく、小さ過ぎる曲率半径と
なることによる折返部3部分への過大のストレスの発生
はなくなる。したがって、繰り返して折返部3部分で重
畳部5を折り返しても、折返部3部分が劣化することは
防止できる。
Therefore, as shown in FIG. 20, when the overlapping portion 5 is folded back at the folding portion 3 and overlapped with the mounting body portion 4,
The folded-back portion 3 is not folded back with a radius of curvature smaller than the thickness of the bending-holding mandrel 40, and excessive stress is not generated in the folded-back portion 3 due to the radius of curvature which is too small. Therefore, even if the overlapping portion 5 is repeatedly folded back at the folding portion 3, the deterioration of the folding portion 3 can be prevented.

【0100】また、重畳部5の折り返し時、曲げ保持心
棒40に沿うように折返部3を曲げることによって、半
導体装置1の外観形状は常に一定となり、外観も安定
し、商品性が高くなる。
Further, when the overlapping portion 5 is folded back, by bending the folding portion 3 along the bending holding mandrel 40, the external shape of the semiconductor device 1 is always constant, the external appearance is stable, and the commercialability is improved.

【0101】なお、前記実施形態3の半導体装置の場合
をも含み、樹脂流れ止め枠15の折返部3側の端を円弧
状の形状とすれば、折返部3を樹脂流れ止め枠15の折
返部3側の端の形状に沿わせて折り返すことができる。
In addition, including the case of the semiconductor device of the third embodiment, if the end of the resin flow stop frame 15 on the side of the turn-back portion 3 is formed in an arc shape, the turn-back portion 3 is turned over of the resin flow stop frame 15. It can be folded back along the shape of the end on the part 3 side.

【0102】本実施形態4の半導体装置1は、実施形態
1の半導体装置1と同様に可撓性配線基板2を通して外
部端子6を目視できるとともに、多ピン化,小型化が図
れる。また、製造においては半田フラックスを使用する
半田を用いてバンプ電極を形成することができるため製
造コストの低減が達成できる。
In the semiconductor device 1 of the fourth embodiment, the external terminals 6 can be seen through the flexible wiring board 2 as in the semiconductor device 1 of the first embodiment, and the number of pins and the size can be reduced. Further, in manufacturing, the bump electrode can be formed by using the solder using the solder flux, so that the manufacturing cost can be reduced.

【0103】(実施形態5)図22乃至図24は本発明
の他の実施形態(実施形態5)である半導体装置に係わ
る図であり、図22は半導体装置の外観を示す斜視図、
図23は半導体装置の模式的正面図、図24は展開状態
の半導体装置の模式的正面図である。
(Embodiment 5) FIGS. 22 to 24 are views relating to a semiconductor device which is another embodiment (embodiment 5) of the present invention, and FIG. 22 is a perspective view showing the appearance of the semiconductor device,
23 is a schematic front view of the semiconductor device, and FIG. 24 is a schematic front view of the semiconductor device in a developed state.

【0104】本実施形態5の半導体装置1は、小型化・
高集積化を図る構造であり、可撓性配線基板2の重畳部
5に半導体チップを組み込んだ封止体7(樹脂流れ止め
枠15)を有するとともに、可撓性配線基板2の実装本
体部4の外部端子6が設けられた面の反対面にも半導体
チップを組み込んだ封止体7(樹脂流れ止め枠15)を
配置したものである。これによって、半導体装置1の高
集積化,多ピン化,小型化が図れることになる。
The semiconductor device 1 according to the fifth embodiment is downsized.
It is a structure for high integration, and has a sealing body 7 (resin flow stop frame 15) in which a semiconductor chip is incorporated in the overlapping portion 5 of the flexible wiring board 2 and a mounting main body portion of the flexible wiring board 2. 4, a sealing body 7 (resin flow stop frame 15) incorporating a semiconductor chip is also arranged on the surface opposite to the surface on which the external terminals 6 are provided. As a result, the semiconductor device 1 can be highly integrated, have a large number of pins, and can be made compact.

【0105】図24に示す展開状態の半導体装置1にお
いて、重畳部5を折返部3で折り返して実装本体部4に
積み重ねることによって、図23および図22に示すよ
うな半導体装置1を得る。本実施形態では実装本体部4
および重畳部5において、可撓性配線基板2の同一面に
封止体7を設け、重畳部5を折り返した際、実装本体部
4の封止体7上に重畳部5の封止体7が重なる構成(折
り返し形状規定手段)となっていることから、折返部3
の曲率半径が大きくなる。
In the unfolded semiconductor device 1 shown in FIG. 24, the overlapping portion 5 is folded back by the folding portion 3 and stacked on the mounting body portion 4 to obtain the semiconductor device 1 as shown in FIGS. 23 and 22. In the present embodiment, the mounting body 4
In the overlapping portion 5, the sealing body 7 is provided on the same surface of the flexible wiring board 2, and when the overlapping portion 5 is folded back, the sealing body 7 of the overlapping portion 5 is placed on the sealing body 7 of the mounting body portion 4. And the folded portion 3 has a structure in which the folded portions overlap each other (folded shape defining means).
The radius of curvature of becomes large.

【0106】本実施形態4の半導体装置1は、実施形態
1の半導体装置1と同様に多ピン化,小型化が図れる。
また、製造においては半田フラックスを使用する半田を
用いてバンプ電極を形成することができるため製造コス
トの低減が達成できる。
The semiconductor device 1 of the fourth embodiment can be multi-pinned and miniaturized as in the semiconductor device 1 of the first embodiment.
Further, in manufacturing, the bump electrode can be formed by using the solder using the solder flux, so that the manufacturing cost can be reduced.

【0107】(実施形態6)図25乃至図28は本発明
の他の実施形態(実施形態6)である半導体装置に係わ
る図であり、図25は重畳部を半開き状態とした半導体
装置を示す斜視図、図26は半導体装置の模式的正面
図、図27は展開状態の半導体装置の一部を示す拡大断
面図、図28は半導体装置の実装状態における半田付け
状態を示す一部の拡大断面図である。
(Sixth Embodiment) FIGS. 25 to 28 are views relating to a semiconductor device according to another embodiment (sixth embodiment) of the present invention, and FIG. 25 shows a semiconductor device in which the overlapping portion is in a half-opened state. 26 is a schematic front view of the semiconductor device, FIG. 27 is an enlarged cross-sectional view showing a part of the semiconductor device in a developed state, and FIG. 28 is a partially enlarged cross-sectional view showing a soldering state in the mounted state of the semiconductor device. It is a figure.

【0108】本実施形態6の半導体装置1は、本実施形
態1の半導体装置1において、半田付け実装部分(外部
端子6)がHGA構造となるものである。
The semiconductor device 1 of the sixth embodiment is the same as the semiconductor device 1 of the first embodiment, except that the soldering mounting portion (external terminal 6) has the HGA structure.

【0109】すなわち、図25および図27に示すよう
に、透明な可撓性配線基板2の実装本体部4には、グリ
ッドアレイ状にスルーホール50が設けられているとと
もに、これらのスルーホール50の内周面およびその縁
には導体層51が設けられている。この導体層51が外
部端子6となる。したがって、各導体層51は配線10
と電気的に接続されている。実施形態では導体層51と
配線10は別々に形成されているが、同時に形成し一体
構造としても良い。
That is, as shown in FIGS. 25 and 27, the mounting body 4 of the transparent flexible wiring board 2 is provided with through holes 50 in a grid array and these through holes 50 are provided. A conductor layer 51 is provided on the inner peripheral surface and the edge thereof. The conductor layer 51 becomes the external terminal 6. Therefore, each conductor layer 51 is connected to the wiring 10
Is electrically connected to In the embodiment, the conductor layer 51 and the wiring 10 are formed separately, but they may be formed at the same time to have an integrated structure.

【0110】本実施形態6の半導体装置1を実装基板3
0に実装する場合は、半導体装置1の実装本体部4の下
面の外部端子6を、実装基板30のランド31に位置決
めして重ねた後、前記ランド31にあらかじめ設けられ
た半田バンプをリフローする。溶けた半田は導体層51
に濡れるとともに、表面張力によってスルーホール50
内に入り上昇し、スルーホール50の上面側にまで到達
する。なお、半田バンプは、前記導体層51に設けずに
実装基板30のランド31に設けておいても良い。
The semiconductor device 1 according to the sixth embodiment is mounted on the mounting substrate 3
In the case of mounting on 0, the external terminals 6 on the lower surface of the mounting body 4 of the semiconductor device 1 are positioned and overlapped with the lands 31 of the mounting substrate 30, and then the solder bumps previously provided on the lands 31 are reflowed. . The melted solder is the conductor layer 51.
The surface of the through hole 50
It goes inside and rises, and reaches the upper surface side of the through hole 50. The solder bump may be provided on the land 31 of the mounting substrate 30 instead of being provided on the conductor layer 51.

【0111】この結果、前記実装基板30のランド31
と、実装本体部4の外部端子6が半田53で接続された
か否かは、スルーホール50内に半田53が吸い上げら
れているか否かを目視確認することによって正確に分か
る。また、本実施形態6の半導体装置1の可撓性配線基
板2は、透明体となっていることから、半田付け状態を
可撓性配線基板2を通して目視検査することもできる。
As a result, the land 31 of the mounting board 30 is
Then, whether or not the external terminals 6 of the mounting body 4 are connected by the solder 53 can be accurately determined by visually confirming whether or not the solder 53 is sucked up into the through hole 50. Further, since the flexible wiring board 2 of the semiconductor device 1 of the sixth embodiment is a transparent body, the soldering state can be visually inspected through the flexible wiring board 2.

【0112】なお、半田バンプは導体層51側に形成し
ておいても良い。
The solder bumps may be formed on the conductor layer 51 side.

【0113】本実施形態6の半導体装置1は、実装基板
30に実装された状態では、半田付け部分は可撓性配線
基板2を突き抜けて露出している。すなわち、半田付け
部分はスルーホール50内に充填された半田53として
露出するため、この露出した半田53にプローブ・ピン
を当てることができる。したがって、従来のBGA型半
導体装置では行えなかったインサーキット・テスト等の
電気特性検査が行える。
In the state where the semiconductor device 1 of the sixth embodiment is mounted on the mounting substrate 30, the soldered portion penetrates the flexible wiring substrate 2 and is exposed. That is, since the soldered portion is exposed as the solder 53 filled in the through hole 50, the probe pin can be applied to the exposed solder 53. Therefore, an electrical characteristic test such as an in-circuit test, which cannot be performed by the conventional BGA type semiconductor device, can be performed.

【0114】前記スルーホール50は、実装本体部4に
半導体チップが組み込まれた重畳部5を、実装後に積み
重ねる構造となっていることから、実装本体部4には半
導体チップの位置に関係なくスルーホール50、すなわ
ち、外部端子6を配置できるため、実装本体部4の中央
部分にも外部端子6を配置できる。この結果、半導体装
置1の小型化が達成できるとともに、実装面積の縮小化
が達成できる。
Since the through hole 50 has a structure in which the superposed portion 5 in which the semiconductor chips are incorporated in the mounting body portion 4 is stacked after mounting, the mounting body portion 4 has a through hole regardless of the position of the semiconductor chip. Since the holes 50, that is, the external terminals 6 can be arranged, the external terminals 6 can also be arranged in the central portion of the mounting body 4. As a result, the semiconductor device 1 can be downsized and the mounting area can be reduced.

【0115】本実施形態6の半導体装置1は、実施形態
1の半導体装置1と同様に可撓性配線基板2を通して外
部端子6を目視できるとともに、多ピン化,小型化が図
れる。
In the semiconductor device 1 of the sixth embodiment, the external terminals 6 can be visually observed through the flexible wiring board 2 as in the semiconductor device 1 of the first embodiment, and the number of pins and the size can be reduced.

【0116】本実施形態6の半導体装置1において、可
撓性配線基板2は透明体でなくとも良い。すなわち、半
導体装置1の外部端子6と、実装基板30のランド31
との半田付け状態は、半導体装置1の実装本体部4に設
けられたスルーホール50内に半田53が吸い上げられ
たか否かを目視で検査できることから、実装本体部4の
可撓性配線基板2部分が不透明体であっても特に支障は
ない。すなわち、実装本体部4の全域にスルーホール5
0を設けて外部端子6を形成できることから、半導体装
置1の小型化が図れる。また、外部端子6をグリッドア
レイ状に配置することから、多ピン化が達成できる。ま
た、前記スルーホール50内に吸い上げられた半田53
にプローブ・ピンを当てることによってインサーキット
・テスト等の電気特性検査が可能となる。さらに、実装
本体部4の導体層51部分に半田バンプを形成する場
合、前記実施形態1の場合と同様に、封止体7等を薬品
に浸けることなく外部端子6(半田バンプ)の洗浄が行
えることから、半田フラックスを使用する半田によって
半田バンプを形成することができ、半導体装置1の製造
コストの低減が図れる。
In the semiconductor device 1 of the sixth embodiment, the flexible wiring board 2 need not be a transparent body. That is, the external terminal 6 of the semiconductor device 1 and the land 31 of the mounting substrate 30.
With respect to the soldering state of the flexible wiring board 2 of the mounting body 4, it can be visually inspected whether the solder 53 has been sucked up into the through hole 50 provided in the mounting body 4 of the semiconductor device 1. Even if the part is opaque, there is no particular problem. That is, the through hole 5 is formed in the entire mounting body portion 4.
Since the external terminal 6 can be formed by providing 0, the semiconductor device 1 can be downsized. Moreover, since the external terminals 6 are arranged in a grid array, a large number of pins can be achieved. Also, the solder 53 sucked up in the through hole 50.
It is possible to inspect electrical characteristics such as an in-circuit test by applying a probe pin to the. Further, when the solder bumps are formed on the conductor layer 51 of the mounting body 4, the external terminals 6 (solder bumps) can be cleaned without immersing the sealing body 7 or the like in a chemical as in the case of the first embodiment. Since it can be performed, the solder bump can be formed by the solder using the solder flux, and the manufacturing cost of the semiconductor device 1 can be reduced.

【0117】(実施形態7)図29乃至図31は本発明
の他の実施形態(実施形態7)である半導体装置に係わ
る図であり、図29は半導体装置の外観を示す斜視図、
図30は半導体装置の模式的正面図、図31は展開状態
の半導体装置の模式的平面図である。
(Embodiment 7) FIGS. 29 to 31 are views relating to a semiconductor device according to another embodiment (embodiment 7) of the present invention, and FIG. 29 is a perspective view showing the appearance of the semiconductor device,
30 is a schematic front view of the semiconductor device, and FIG. 31 is a schematic plan view of the semiconductor device in a developed state.

【0118】本実施形態7の半導体装置1は、外部端子
6部分がスルーホール50と導体層51で形成されるH
GA構造の例であり、実装本体部4において周辺部分に
スルーホール50を配置した構造である。本実施形態7
の半導体装置1は、実装本体部4の上面中央部分に封止
体7(樹脂流れ止め枠15)を配置した構造となってい
る。図示はしないが、前記封止体7の内部には半導体チ
ップが配置され、かつ半導体チップの電極と配線とはワ
イヤを介して電気的に接続されている。半導体チップ
は、実装本体部4と重畳部5にそれぞれ搭載され、高集
積化が図られている。
In the semiconductor device 1 of the seventh embodiment, the external terminal 6 portion is formed by the through hole 50 and the conductor layer 51.
This is an example of a GA structure, and is a structure in which through holes 50 are arranged in the peripheral portion of the mounting body 4. This Embodiment 7
The semiconductor device 1 has a structure in which the sealing body 7 (resin flow stop frame 15) is arranged in the central portion of the upper surface of the mounting body 4. Although not shown, a semiconductor chip is arranged inside the sealing body 7, and the electrodes and wirings of the semiconductor chip are electrically connected via wires. The semiconductor chips are mounted on the mounting body 4 and the superposing portion 5, respectively, so that high integration is achieved.

【0119】樹脂流れ止め枠15および封止体7が配置
される領域には、スルーホール50を設けることはでき
ないため、スルーホール50は樹脂流れ止め枠15の外
側の実装本体部4の領域に設けられている。したがっ
て、本実施形態7の半導体装置1においては、図29乃
至図31に示すように、実装本体部4は重畳部5よりも
大きなものとなる。
Since the through hole 50 cannot be provided in the area where the resin flow stop frame 15 and the sealing body 7 are arranged, the through hole 50 is provided outside the resin flow stop frame 15 in the area of the mounting body 4. It is provided. Therefore, in the semiconductor device 1 of the seventh embodiment, as shown in FIGS. 29 to 31, the mounting body portion 4 is larger than the overlapping portion 5.

【0120】本実施形態7において、可撓性配線基板2
は透明体であっても不透明体であっても良い。透明体の
場合は、可撓性配線基板2を通して外部端子6を目視で
きるので、実装において半田付け状態を目視できる利点
がある。
In the seventh embodiment, the flexible wiring board 2
May be transparent or opaque. In the case of a transparent body, since the external terminals 6 can be viewed through the flexible wiring board 2, there is an advantage that the soldering state can be viewed during mounting.

【0121】本実施形態7の半導体装置1は、実施形態
1の半導体装置1や実施形態6の半導体装置1と同様に
小型化,多ピン化が図れる。さらに、スルーホール50
内の吸い上げられた半田53にプローブ・ピンを当てる
ことによってインサーキット・テスト等の電気特性検査
を行うこともできる。
The semiconductor device 1 of the seventh embodiment can be downsized and have a large number of pins, like the semiconductor device 1 of the first embodiment and the semiconductor device 1 of the sixth embodiment. Furthermore, through hole 50
It is also possible to perform an electrical characteristic test such as an in-circuit test by applying a probe pin to the sucked solder 53 inside.

【0122】(実施形態8)図32および図33は本発
明の他の実施形態(実施形態8)である半導体装置に係
わる図であり、図32は半導体装置の外観を示す斜視
図、図33は展開状態の半導体装置において各重畳部の
封止体を部分的に取り除いた状態を示す底面図である。
(Embodiment 8) FIGS. 32 and 33 are views relating to a semiconductor device according to another embodiment (Embodiment 8) of the present invention. FIG. 32 is a perspective view showing the appearance of the semiconductor device, and FIG. FIG. 6B is a bottom view showing a state in which the sealing bodies of the respective overlapping portions are partially removed in the semiconductor device in the expanded state.

【0123】本実施形態8の半導体装置1は、実装本体
部4に積み重ねる重畳部5を複数とした例を示すもので
あり、さらに多数の半導体チップを組み込んで高集積
化,メモリ容量の増大や多機能化を図ったものである。
The semiconductor device 1 of the eighth embodiment shows an example in which a plurality of overlapping portions 5 are stacked on the mounting body portion 4. Further, a large number of semiconductor chips are incorporated to achieve high integration and increase in memory capacity. It is intended to be multifunctional.

【0124】本実施形態8の半導体装置1では、透明体
からなる可撓性配線基板2(ポリイミドフィルム等の樹
脂フィルム8)は十文字状のパターンとなっている。そ
して、十文字状の左側矩形部55を実装本体部4とし、
右側矩形部56,上側矩形部57,下側矩形部58およ
び十文字の中心部分の中央矩形部59の4つを重畳部5
としている。中央矩形部59とその周囲の左側矩形部5
5,右側矩形部56,上側矩形部57,下側矩形部58
とは配線10によって所定パターンに接続されている。
In the semiconductor device 1 of the eighth embodiment, the flexible wiring substrate 2 (resin film 8 such as polyimide film) made of a transparent material has a cross-shaped pattern. Then, the cross-shaped left side rectangular portion 55 is used as the mounting body portion 4,
The right side rectangular portion 56, the upper side rectangular portion 57, the lower side rectangular portion 58, and the central rectangular portion 59 at the center portion of the cross are overlapped with the overlapping portion 5.
And The central rectangular portion 59 and the surrounding left rectangular portion 5
5, right rectangular portion 56, upper rectangular portion 57, lower rectangular portion 58
Are connected to a predetermined pattern by wiring 10.

【0125】中央矩形部59と左側矩形部55,右側矩
形部56,上側矩形部57,下側矩形部58との間には
折返部3が設けられ、折返部3で順次折り返すことによ
って、実装本体部4上に中央矩形部59,右側矩形部5
6,上側矩形部57,下側矩形部58を積み重ねること
ができるようになっている。
The folding part 3 is provided between the central rectangular part 59 and the left rectangular part 55, the right rectangular part 56, the upper rectangular part 57, and the lower rectangular part 58. A central rectangular portion 59 and a right rectangular portion 5 are provided on the main body portion 4.
6, the upper rectangular portion 57 and the lower rectangular portion 58 can be stacked.

【0126】左側矩形部55には半田バンプ電極からな
る外部端子6がグリッドアレイ状に配設されている。
External terminals 6 made of solder bump electrodes are arranged in a grid array on the left rectangular portion 55.

【0127】前記右側矩形部56,上側矩形部57,下
側矩形部58,中央矩形部59の各重畳部5の可撓性配
線基板2には、半導体チップ12が固定されるととも
に、これら半導体チップ12の電極と配線10とは導電
性のワイヤ14で電気的に接続されている。また、右側
矩形部56,上側矩形部57,下側矩形部58,中央矩
形部59の可撓性配線基板2には樹脂流れ止め枠15が
半導体チップ12やワイヤ14等を囲むように固定され
ている。各樹脂流れ止め枠15内には半導体チップ12
やワイヤ14等を被うように樹脂17が充填され、封止
体7が形成されている。
The semiconductor chip 12 is fixed to the flexible wiring board 2 of each overlapping portion 5 of the right rectangular portion 56, the upper rectangular portion 57, the lower rectangular portion 58, and the central rectangular portion 59, and the semiconductor chips 12 are fixed to the flexible wiring substrate 2. The electrode of the chip 12 and the wiring 10 are electrically connected by a conductive wire 14. Further, the resin flow stop frame 15 is fixed to the flexible wiring board 2 of the right rectangular portion 56, the upper rectangular portion 57, the lower rectangular portion 58, and the central rectangular portion 59 so as to surround the semiconductor chip 12, the wire 14, and the like. ing. A semiconductor chip 12 is provided in each resin flow stop frame 15.
The resin 17 is filled so as to cover the wires 14, the wires 14, etc., and the sealing body 7 is formed.

【0128】図33は本実施形態8の展開状態の半導体
装置1を示すものである。このような展開状態の半導体
装置1は、実装本体部4上に順次重畳部5を積み重ね、
図32に示すような外観の半導体装置1として使用され
る。
FIG. 33 shows the semiconductor device 1 in the expanded state according to the eighth embodiment. In the semiconductor device 1 in such a developed state, the superposing section 5 is sequentially stacked on the mounting body section 4,
It is used as the semiconductor device 1 having the appearance as shown in FIG.

【0129】本実施形態8の半導体装置1は、図33に
示すような展開状態でも保管できるし、図32に示すよ
うに、組み立てられた状態でも保管できる。図32のよ
うに組立状態の場合は、実装本体部4に積み重ねられる
重畳部5が動かないようにしておくことが、破損等を考
えた場合望ましい。すなわち、図32の状態では、たと
えば、実装本体部4上に直接積み重ねられる実装本体部
4を接着剤や接着テープによって仮止めし、その後実装
本体部4に仮固定された重畳部5上に積み重ねられる重
畳部5を接着剤や接着テープによって順次仮固定するよ
うにする。
The semiconductor device 1 according to the eighth embodiment can be stored in the unfolded state as shown in FIG. 33 or in the assembled state as shown in FIG. In the case of the assembled state as shown in FIG. 32, it is desirable that the overlapping portion 5 stacked on the mounting body portion 4 does not move in consideration of damage or the like. That is, in the state of FIG. 32, for example, the mounting body 4 directly stacked on the mounting body 4 is temporarily fixed with an adhesive or an adhesive tape, and then stacked on the overlapping portion 5 temporarily fixed to the mounting body 4. The overlapping portions 5 to be formed are sequentially temporarily fixed with an adhesive or an adhesive tape.

【0130】これによって半導体装置1の取扱時、重畳
部5がずれたりして半導体装置1の組立状態の形状が崩
れなくなる。
As a result, when the semiconductor device 1 is handled, the overlapping portion 5 does not shift and the shape of the semiconductor device 1 in the assembled state does not collapse.

【0131】本実施形態8の半導体装置1は、重畳部5
が複数となるが、実施形態1の半導体装置1の場合と同
様に、実装本体部4の可撓性配線基板2が透明体となる
ことから、実装後可撓性配線基板2を通して外部端子6
の半田付け状態を目視検査することができる。
The semiconductor device 1 according to the eighth embodiment includes the superposing section 5.
However, as in the case of the semiconductor device 1 of the first embodiment, since the flexible wiring board 2 of the mounting body 4 is a transparent body, the external terminals 6 are mounted through the flexible wiring board 2 after mounting.
The soldering state of can be visually inspected.

【0132】本実施形態8の半導体装置1は、実施形態
1の半導体装置1と同様に小型化,多ピン化が図れると
ともに、さらに高集積化が達成できる。
Like the semiconductor device 1 of the first embodiment, the semiconductor device 1 of the eighth embodiment can be downsized and have a large number of pins, and further high integration can be achieved.

【0133】本実施形態8の半導体装置1は、実施形態
1の半導体装置1と同様に、製造においては半田フラッ
クスを使用する半田を用いてバンプ電極を形成すること
ができるため製造コストの低減が達成できる。
As in the semiconductor device 1 of the first embodiment, the semiconductor device 1 of the eighth embodiment can reduce the manufacturing cost because the bump electrodes can be formed by using the solder using the solder flux in the manufacturing process. Can be achieved.

【0134】本実施形態8では、配線10は可撓性配線
基板2の一面側にのみ設けた例としたが、可撓性配線基
板2の両面に配線10を設け、表裏面の配線10をスル
ーホールに充填した導体で電気的に接続する構造として
も良い。また、外部端子はスルーホールを利用したHG
A構造としても良い。
In the eighth embodiment, the wiring 10 is provided only on one surface side of the flexible wiring board 2. However, the wiring 10 is provided on both surfaces of the flexible wiring board 2 and the wirings 10 on the front and back surfaces are provided. A structure may be used in which the conductors filled in the through holes are electrically connected. In addition, the external terminal is a HG that uses a through hole.
It may be an A structure.

【0135】以上本発明者によってなされた発明を実施
形態に基づき具体的に説明したが、本発明は上記実施形
態に限定されるものではなく、その要旨を逸脱しない範
囲で種々変更可能であることはいうまでもない、たとえ
ば、前記実施形態では、配線10は透明な導電体よって
形成したが、透明でない金属膜で形成しても良い。たと
えば、配線はポリイミドフィルムに貼り付けた銅箔を所
望のパターンにエッチングすることによって形成しても
良い。この場合でも、透明な可撓性配線基板2を通し
て、かつ配線10と配線10との間から実装状態の外部
端子6の半田付け性の良否を検査できる。
Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say, for example, although the wiring 10 is formed of a transparent conductor in the above-described embodiment, it may be formed of a non-transparent metal film. For example, the wiring may be formed by etching a copper foil attached to a polyimide film into a desired pattern. Even in this case, it is possible to inspect the solderability of the mounted external terminal 6 through the transparent flexible wiring board 2 and between the wirings 10.

【0136】また、半導体装置1は全体を可撓性の配線
基板で形成したが、少なくとも折返部3だけが折り返し
自在であれば良く、実装本体部4や重畳部5の部分は可
撓体(非可撓体)でなくとも良い。たとえば、重畳部5
を通常の可撓性でない配線基板で形成し、実装本体部4
をガラスに導電性の透明な膜(酸化錫と酸化アンチモン
の化合物からなる透明な膜)で配線を形成したものとし
ても良い。
Although the semiconductor device 1 is entirely formed of a flexible wiring board, at least only the folding portion 3 can be folded back, and the mounting body portion 4 and the superposing portion 5 are flexible ( It does not have to be a non-flexible body. For example, the superposition unit 5
Is formed of a normal non-flexible wiring board, and the mounting body 4
The wiring may be formed on glass by a conductive transparent film (transparent film made of a compound of tin oxide and antimony oxide).

【0137】前記実施形態では、樹脂の流出を防止する
ための枠はプラスチックによる樹脂流れ止め枠を固定す
る手法を採用しているが、可撓性配線基板に直接絶縁性
インキを印刷することによって形成しても良い。また、
枠を使用せずに、トランスファモールドによって樹脂フ
ィルム8に直接封止体7を形成形成しても良い。
In the above-mentioned embodiment, the method of fixing the resin flow stop frame made of plastic is adopted as the frame for preventing the resin from flowing out. However, by printing the insulating ink directly on the flexible wiring substrate. You may form. Also,
The sealing body 7 may be formed directly on the resin film 8 by transfer molding without using a frame.

【0138】前記実施形態では半導体チップと配線との
接続はワイヤによって接続していたが、半導体チップを
フェイスダウンとしてフリップチップで接続したり、ビ
ームリードを使用して接続するようにしても良い。
In the above-mentioned embodiment, the semiconductor chip and the wiring are connected by the wire, but the semiconductor chip may be connected face down by the flip chip or by using the beam lead.

【0139】前記実施形態では、重畳部は単一の半導体
チップを搭載したものとしたが、複数の半導体チップの
搭載やチップ抵抗やチップコンデンサ等の受動部品を搭
載したもの、すなわち混成集積回路(ハイブリッドI
C)構成としても良い。
In the above-described embodiment, the superimposing part is mounted with a single semiconductor chip, but mounting with a plurality of semiconductor chips and passive components such as chip resistors and chip capacitors, that is, a hybrid integrated circuit ( Hybrid I
C) It may be configured.

【0140】前記実施形態では、外部端子は突出したバ
ンプ電極としたが、リードを植え付けた構造としても良
い。
In the above-mentioned embodiment, the external terminal is the bump electrode that protrudes, but a lead may be implanted.

【0141】前記実施形態では、樹脂フィルムの裏面に
所望パターンの配線を形成したが、配線は樹脂フィルム
の両面に形成してもよく、また絶縁体で配線をカバーす
ることで多層の配線構造としてもよい。これらの場合、
上下の各配線層はスルーホールで接続する。スルーホー
ルの内周面およびその縁には導体層が設けられている。
In the above-mentioned embodiment, the wiring of the desired pattern is formed on the back surface of the resin film, but the wiring may be formed on both surfaces of the resin film, or the wiring is covered with an insulator to form a multilayer wiring structure. Good. In these cases,
The upper and lower wiring layers are connected by through holes. A conductor layer is provided on the inner peripheral surface of the through hole and its edge.

【0142】前記実施形態では、パッケージのみを取り
上げているが、放熱フィンを上部に取り付けたり、放熱
板を挟み込んで熱対策することもできる。
In the above embodiment, only the package is taken up, but it is also possible to attach a heat radiation fin on the top or sandwich a heat radiation plate to take measures against heat.

【0143】本発明は少なくとも実装本体部の下面に外
部端子を有し、前記実装本体部の上に順次重畳部を積み
重ねる構造の半導体装置の製造技術および実装技術には
適用できる。
The present invention can be applied to a manufacturing technique and a mounting technique of a semiconductor device having a structure in which an external terminal is provided at least on the lower surface of the mounting main body, and the overlapping portions are sequentially stacked on the mounting main body.

【0144】前記各実施形態では、外部端子を有する実
装本体部4を1つとしたが、実装本体部4を複数として
も良い。すなわち、可撓性配線基板2を多方向に延在し
て実装本体部4や重畳部5を複数有する半導体装置1に
おいて、実装本体部4や重畳部5の先に折返部3を設け
て繰り返し実装本体部4や重畳部5を延在させる構造と
しても良い。この場合、複数の実装本体部4を平坦な実
装基板に実装しても良く、また複数の異なる面を有する
実装基板の各面に前記実装本体部4を実装し、それらの
実装本体部4から延在する重畳部5を折返部3で折り返
して各実装本体部4に積み重ねたり、または展開状態に
させ、もしくは直立状態として実装を行うようにしても
良い。この場合、半導体装置1の小型化・多機能化が図
れるばかりでなく、実装においては実装面積の狭小化,
実装空間の有効利用化が図れる。また、半導体装置1は
実装基板に搭載された部品上に実装することも可能であ
る。また、重畳部は各々個別に製作し、折り返し部で接
続して実施形態のような形態にしてもよい。その場合、
各重畳部ごとにテスト後良品のみを使ってモジュール化
できるため歩留りが向上する。
In each of the above-mentioned embodiments, the mounting main body 4 having the external terminals is one, but the mounting main body 4 may be plural. That is, in the semiconductor device 1 that has the flexible wiring substrate 2 extending in multiple directions and has a plurality of mounting body portions 4 and overlapping portions 5, the folding portion 3 is provided in front of the mounting body portion 4 and the overlapping portion 5 and repeated. The mounting main body portion 4 and the overlapping portion 5 may be extended. In this case, a plurality of mounting body parts 4 may be mounted on a flat mounting board, or the mounting body parts 4 may be mounted on each surface of a mounting board having a plurality of different surfaces, and The extending overlapping portion 5 may be folded back at the folding portion 3 to be stacked on each mounting body portion 4, or may be placed in an expanded state, or mounted in an upright state. In this case, not only the semiconductor device 1 can be downsized and multifunctional, but also the mounting area can be reduced in mounting.
Effective utilization of the mounting space can be achieved. Also, the semiconductor device 1 can be mounted on a component mounted on a mounting board. Further, the overlapping portions may be manufactured individually and connected at the folded portions to form the embodiment. In that case,
The yield can be improved because only non-defective products can be modularized after each test.

【0145】[0145]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

【0146】(1)半導体装置は、折返部で自由に折り
返しができ、必要に応じて実装本体部の上に重畳部を積
み重ねる構造となっていることと、配線板(可撓性配線
基板)が透明体であることから、重畳部を実装本体部に
重ねない状態では配線板の裏面の外部端子を目視でき
る。したがって、半導体装置の外部端子を実装基板のラ
ンドに重ね合わせる際、ランドと外部端子の重なり具合
を目視観察できるため、位置合わせが正確かつ容易とな
る。また、実装後、外部端子とランドとの半田付け状態
を目視検査できるため、実装の良否検査が容易となると
ともに、実装の信頼性を高めることができる。
(1) The semiconductor device has a structure in which the folded portion can be freely folded, and the overlapping portion is stacked on the mounting main body portion as necessary, and the wiring board (flexible wiring board) is provided. Since it is a transparent body, the external terminals on the back surface of the wiring board can be visually observed when the overlapping portion is not overlapped with the mounting main body portion. Therefore, when the external terminals of the semiconductor device are superposed on the lands of the mounting board, the degree of overlap between the lands and the external terminals can be visually observed, and the alignment can be accurately and easily performed. Further, since the soldering state of the external terminal and the land can be visually inspected after the mounting, the quality of the mounting can be easily inspected and the reliability of the mounting can be improved.

【0147】(2)半導体装置は重畳部を開くことによ
っていつでも配線板を通して配線板の裏面の外部端子を
目視できるため、半導体装置を実装基板に実装した後で
も外部端子の半田実装状態を目視検査できるため、実装
本体部の配線板には、半導体チップ等が重なる部分にも
外部端子を配置できることになり、半導体装置の小型化
および多ピン化が図れる。したがって、半導体装置の小
型化によって実装面積の縮小化を図ることができる。
(2) Since the semiconductor device allows the external terminals on the back surface of the wiring board to be visually inspected through the wiring board at any time by opening the overlapping portion, the solder mounting state of the external terminals can be visually inspected even after the semiconductor device is mounted on the mounting board. Therefore, the wiring board of the mounting main body can be provided with external terminals even in a portion where the semiconductor chip and the like overlap each other, and the semiconductor device can be miniaturized and the number of pins can be increased. Therefore, the mounting area can be reduced by downsizing the semiconductor device.

【0148】(3)実装本体部に複数の重畳部を順次積
み重ねる構造では高集積化が達成できる。
(3) High integration can be achieved in a structure in which a plurality of overlapping portions are sequentially stacked on the mounting main body portion.

【0149】(4)半導体装置は、折返部で自由に折り
返しができ、必要に応じて実装本体部の上に重畳部を積
み重ねる構造となっているが、必要に応じて重畳部を実
装本体部に接着剤や接着テープによって仮固定を含めて
固定できるため、半導体装置の取扱性が向上する。
(4) The semiconductor device has a structure in which the folded portion can be freely folded back, and the overlapping portion is stacked on the mounting body portion as needed. Since it can be fixed including temporary fixing with an adhesive or an adhesive tape, the handling of the semiconductor device is improved.

【0150】(5)半導体装置は、実装本体部下面に半
田によってバンプ電極を形成する際、バンプ電極形成
後、実装本体部のみを薬品に浸け、半導体チップが搭載
された重畳部を薬品に浸けないようにできるため、コス
トが高く付く無洗浄タイプの半田を用いることなく半田
フラックスを使用する半田を用いてバンプ電極を形成す
ることができるため、半導体装置の製造コストの低減が
達成できる。
(5) In the semiconductor device, when the bump electrodes are formed on the lower surface of the mounting body by soldering, after the bump electrodes are formed, only the mounting body is soaked in the chemical, and the overlapping portion on which the semiconductor chip is mounted is soaked in the chemical. Since the bump electrodes can be formed by using solder that uses solder flux without using non-cleaning type solder that is expensive, it is possible to reduce the manufacturing cost of the semiconductor device.

【0151】(6)透明な樹脂フィルムを主体として形
成された配線板を用い、従来確立されたリードフレーム
による半導体装置製造技術と同様に製造が行えるため、
高品質の折り返し重畳構造の半導体装置を生産性良く製
造することができる。
(6) Since a wiring board formed mainly of a transparent resin film can be manufactured in the same manner as the semiconductor device manufacturing technology using a lead frame established conventionally,
It is possible to manufacture a high quality semiconductor device having a folded and superposed structure with high productivity.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態(実施形態1)である半導
体装置の外観を示す斜視図である。
FIG. 1 is a perspective view showing the external appearance of a semiconductor device according to an embodiment (Embodiment 1) of the present invention.

【図2】本実施形態1の半導体装置において重畳部を半
開き状態とした模式的斜視図である。
FIG. 2 is a schematic perspective view of the semiconductor device according to the first embodiment with a superposed portion in a half-opened state.

【図3】本実施形態1の展開状態の半導体装置を示す正
面図である。
FIG. 3 is a front view showing the semiconductor device in a developed state according to the first embodiment.

【図4】本実施形態1の半導体装置の展開状態を示す模
式的底面図である。
FIG. 4 is a schematic bottom view showing a developed state of the semiconductor device of the first embodiment.

【図5】本実施形態1の展開状態の半導体装置において
封止体の一部を除いた状態を示す模式的底面図である。
FIG. 5 is a schematic bottom view showing a state in which a part of the sealing body is removed in the unfolded semiconductor device of the first embodiment.

【図6】本実施形態1の展開状態の半導体装置の一部の
拡大断面図である。
FIG. 6 is an enlarged cross-sectional view of a part of the semiconductor device in a developed state according to the first embodiment.

【図7】本実施形態1の半導体装置の製造に使用する配
線フレームの模式的平面図である。
FIG. 7 is a schematic plan view of a wiring frame used for manufacturing the semiconductor device of the first embodiment.

【図8】本実施形態1の半導体装置の製造において配線
フレームに樹脂流れ止め枠を固定した状態を示す模式的
平面図である。
FIG. 8 is a schematic plan view showing a state in which a resin flow stop frame is fixed to a wiring frame in the manufacture of the semiconductor device of the first embodiment.

【図9】本実施形態1の半導体装置の製造において配線
フレームに半導体チップを固定した状態を示す模式的平
面図である。
FIG. 9 is a schematic plan view showing a state in which a semiconductor chip is fixed to a wiring frame in manufacturing the semiconductor device of the first embodiment.

【図10】本実施形態1の半導体装置の製造においてワ
イヤボンディングがなされた配線フレームを示す模式的
平面図である。
FIG. 10 is a schematic plan view showing a wiring frame to which wire bonding is applied in manufacturing the semiconductor device of the first embodiment.

【図11】本実施形態1の半導体装置の製造において封
止体が形成された配線フレームを示す模式的平面図であ
る。
FIG. 11 is a schematic plan view showing a wiring frame in which a sealing body is formed in the manufacturing of the semiconductor device of the first embodiment.

【図12】本実施形態1の半導体装置の製造において外
部端子が形成された配線フレームを示す模式的平面図で
ある。
FIG. 12 is a schematic plan view showing a wiring frame in which external terminals are formed in the manufacturing of the semiconductor device of the first embodiment.

【図13】本実施形態1の半導体装置の実装開始状態を
示す模式図である。
FIG. 13 is a schematic diagram showing a mounting start state of the semiconductor device of the first embodiment.

【図14】本実施形態1の半導体装置の実装において、
半田付け後重畳部を途中まで反転させた状態を示す正面
図である。
FIG. 14 is a view showing mounting of the semiconductor device of the first embodiment,
It is a front view which shows the state which turned over the superimposition part halfway after soldering.

【図15】本実施形態1の半導体装置の実装において、
半田付け後重畳部を実装本体部に重ね合わせた状態を示
す正面図である。
FIG. 15 is a view showing mounting of the semiconductor device of the first embodiment,
It is a front view which shows the state which overlapped the superposition part after soldering on the mounting main body part.

【図16】本発明の他の実施形態(実施形態2)である
半導体装置の斜視図である。
FIG. 16 is a perspective view of a semiconductor device according to another embodiment (Embodiment 2) of the present invention.

【図17】本実施形態2の展開状態の半導体装置の模式
的底面図である。
FIG. 17 is a schematic bottom view of the semiconductor device in a developed state according to the second embodiment.

【図18】本発明の他の実施形態(実施形態3)である
半導体装置の正面図である。
FIG. 18 is a front view of a semiconductor device according to another embodiment (Embodiment 3) of the present invention.

【図19】本実施形態3の展開状態の半導体装置の正面
図である。
FIG. 19 is a front view of the semiconductor device according to the third embodiment in a developed state.

【図20】本発明の他の実施形態(実施形態4)である
半導体装置の正面図である。
FIG. 20 is a front view of a semiconductor device according to another embodiment (Embodiment 4) of the present invention.

【図21】本実施形態4の展開状態の半導体装置の正面
図である。
FIG. 21 is a front view of the semiconductor device according to the fourth embodiment in a developed state.

【図22】本発明の他の実施形態(実施形態5)である
半導体装置の外観を示す斜視図である。
FIG. 22 is a perspective view showing the outer appearance of a semiconductor device according to another embodiment (embodiment 5) of the present invention.

【図23】本実施形態5の半導体装置を示す正面図であ
る。
FIG. 23 is a front view showing the semiconductor device of the fifth embodiment.

【図24】本実施形態5の展開状態の半導体装置の正面
図である。
FIG. 24 is a front view of the semiconductor device in a developed state according to the fifth embodiment.

【図25】本発明の他の実施形態(実施形態6)である
半導体装置において重畳部を半開き状態とした斜視図で
ある。
FIG. 25 is a perspective view of a semiconductor device according to another embodiment (Embodiment 6) of the present invention in which the overlapping portion is in a half-opened state.

【図26】本実施形態6の半導体装置を示す正面図であ
る。
FIG. 26 is a front view showing the semiconductor device of the sixth embodiment.

【図27】本実施形態6の展開状態の半導体装置の一部
を示す拡大断面図である。
FIG. 27 is an enlarged cross-sectional view showing a part of the semiconductor device in a developed state according to the sixth embodiment.

【図28】本実施形態6の半導体装置の実装状態におけ
る半田付け状態を示す一部の拡大断面図である。
FIG. 28 is a partial enlarged cross-sectional view showing a soldered state of the semiconductor device of the sixth embodiment in a mounted state.

【図29】本発明の他の実施形態(実施形態7)である
半導体装置の外観を示す斜視図である。
FIG. 29 is a perspective view showing the outer appearance of a semiconductor device according to another embodiment (Embodiment 7) of the present invention.

【図30】本実施形態7の半導体装置を示す正面図であ
る。
FIG. 30 is a front view showing the semiconductor device of the seventh embodiment.

【図31】本実施形態7の展開状態の半導体装置を示す
模式的平面図である。
FIG. 31 is a schematic plan view showing a semiconductor device in a developed state according to the seventh embodiment.

【図32】本発明の他の実施形態(実施形態8)である
半導体装置の外観を示す斜視図である。
FIG. 32 is a perspective view showing the external appearance of a semiconductor device according to another embodiment (Embodiment 8) of the present invention.

【図33】本実施形態8の展開状態の半導体装置におい
て各重畳部の封止体を部分的に取り除いた状態を示す模
式的底面図である。
FIG. 33 is a schematic bottom view showing a state in which the sealing body of each overlapping portion is partially removed in the semiconductor device in the developed state of the eighth embodiment.

【符号の説明】[Explanation of symbols]

1…半導体装置、2…可撓性配線基板、3…折返部、4
…実装本体部、5…重畳部、6…外部端子、7…封止
体、8…樹脂フィルム(ポリイミドフィルム)、10…
配線、11…接着剤、12…半導体チップ、13…保護
膜、14…ワイヤ、15…樹脂流れ止め枠、16…接着
剤、17…樹脂、20…配線フレーム、21…可撓性配
線基板部、22…フレーム部、23…吊り部、24…台
座、30…実装基板、31…ランド、35…嵌合孔、3
6…嵌合雌部、37…突子、40…曲げ保持心棒、50
…スルーホール、51…導体層、53…半田、55…左
側矩形部、56…右側矩形部、57…上側矩形部、58
…下側矩形部、59…中央矩形部。
DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Flexible wiring board, 3 ... Folding part, 4
... mounting main body part, 5 ... superposed part, 6 ... external terminal, 7 ... sealing body, 8 ... resin film (polyimide film), 10 ...
Wiring, 11 ... Adhesive agent, 12 ... Semiconductor chip, 13 ... Protective film, 14 ... Wire, 15 ... Resin flow stop frame, 16 ... Adhesive agent, 17 ... Resin, 20 ... Wiring frame, 21 ... Flexible wiring board part , 22 ... Frame part, 23 ... Hanging part, 24 ... Pedestal, 30 ... Mounting board, 31 ... Land, 35 ... Fitting hole, 3
6 ... Fitting female part, 37 ... Protrusion, 40 ... Bending holding mandrel, 50
... Through hole, 51 ... Conductor layer, 53 ... Solder, 55 ... Left side rectangular part, 56 ... Right side rectangular part, 57 ... Upper side rectangular part, 58
... Lower rectangular part, 59 ... Central rectangular part.

Claims (17)

【特許請求の範囲】[Claims] 【請求項1】 一面に外部端子を設けた配線板からなる
少なくとも一つの実装本体部と、少なくとも半導体チッ
プを含む電子部品を搭載した配線板からなる一つの重畳
部と、前記実装本体部と前記重畳部のうち同種または異
種のものを電気的かつ機械的に連結する可撓性の配線板
からなる少なくとも一つの折返部とを有し、前記重畳部
は前記折返部で折り返えされて所定の実装本体部や重畳
部上に積み重ねられる構成となっていることを特徴とす
る半導体装置。
1. An at least one mounting main body made of a wiring board having external terminals provided on one surface, one superposed portion made of a wiring board mounting an electronic component including at least a semiconductor chip, the mounting main body and the At least one folding portion formed of a flexible wiring board that electrically and mechanically connects the same kind or different kinds of the overlapping portions, and the overlapping portion is folded back at the folding portion and has a predetermined length. A semiconductor device, which is configured to be stacked on the mounting main body part or the superimposing part.
【請求項2】 前記実装本体部および折返部ならびに重
畳部の配線板は一体となった可撓性体で構成されている
ことを特徴とする請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the wiring board of the mounting main body portion, the folded-back portion and the overlapping portion is formed of an integrated flexible body.
【請求項3】 前記実装本体部および重畳部の配線板は
非可撓性体で形成されていることを特徴とする請求項1
記載の半導体装置。
3. The wiring board of the mounting main body and the wiring board of the overlapping portion are formed of a non-flexible body.
13. The semiconductor device according to claim 1.
【請求項4】 前記重畳部の電子部品搭載領域が重なる
実装本体部領域内にも外部端子が設けられていることを
特徴とする請求項1乃至請求項3のいずれか1項記載の
半導体装置。
4. The semiconductor device according to claim 1, wherein an external terminal is also provided in a mounting body portion region where the electronic component mounting region of the overlapping portion overlaps. .
【請求項5】 前記実装本体部の配線板は配線板下面の
外部端子を目視できる透明体となっていることを特徴と
する請求項1乃至請求項4のいずれか1項記載の半導体
装置。
5. The semiconductor device according to claim 1, wherein the wiring board of the mounting main body is a transparent body through which external terminals on the lower surface of the wiring board can be visually observed.
【請求項6】 前記外部端子は前記配線板を貫通するス
ルーホールの内壁とその縁に設けた導体層によって形成
されていることを特徴とする請求項1乃至請求項4のい
ずれか1項記載の半導体装置。
6. The external terminal is formed by an inner wall of a through hole penetrating the wiring board and a conductor layer provided on an edge thereof. Semiconductor device.
【請求項7】 前記折返部の折り返し時の曲率半径を規
定する折り返し形状規定手段が設けられていることを特
徴とする請求項1乃至請求項6のいずれか1項記載の半
導体装置。
7. The semiconductor device according to claim 1, further comprising a folded shape defining means that defines a radius of curvature when the folded portion is folded.
【請求項8】 前記重畳部は前記実装本体部に固定手段
によって固定されていることを特徴とする請求項1乃至
請求項7のいずれか1項記載の半導体装置。
8. The semiconductor device according to claim 1, wherein the overlapping portion is fixed to the mounting main body by fixing means.
【請求項9】 前記電子部品の搭載領域は封止体で被わ
れていることを特徴とする請求項1乃至請求項8のいず
れか1項記載の半導体装置。
9. The semiconductor device according to claim 1, wherein the mounting area of the electronic component is covered with a sealing body.
【請求項10】 一面に外部端子を設ける台座を有する
配線板からなる少なくとも一つの実装本体部と、少なく
とも半導体チップを含む電子部品を搭載する領域を有す
る配線板からなる一つの重畳部と、前記実装本体部と前
記重畳部のうち同種または異種のものを電気的かつ機械
的に連結する可撓性の配線板からなる少なくとも一つの
折返部とを少なくとも有し、前記重畳部は前記折返部で
折り返えされて所定の実装本体部や重畳部上に積み重ね
られる構成の配線基板を用意する工程と、前記重畳部に
半導体チップを含む電子部品の搭載と電極と配線の電気
的接続を行う工程と、前記電子部品搭載領域を封止体で
被う工程と、前記実装本体部の台座に半田バンプ電極を
形成する工程と、前記配線板の不要部分を切断除去する
工程と、所定の折返部を折り返して所定の実装本体部上
に重畳部を積み重ねる工程とを有することを特徴とする
半導体装置の製造方法。
10. An at least one mounting main body part made of a wiring board having a pedestal on one surface of which an external terminal is provided, and one overlapping part made of a wiring board having an area for mounting an electronic component including at least a semiconductor chip, At least one mounting main body portion and at least one folding portion formed of a flexible wiring board that electrically and mechanically connects the same kind or different kinds of the overlapping portion, the overlapping portion being the folding portion. A step of preparing a wiring board that is folded back and stacked on a predetermined mounting body portion or a superposed portion; a step of mounting an electronic component including a semiconductor chip on the superposed portion and electrically connecting electrodes and wiring A step of covering the electronic component mounting area with a sealing body, a step of forming a solder bump electrode on a pedestal of the mounting body, a step of cutting and removing an unnecessary portion of the wiring board, and a predetermined folding step. And a step of folding back the parts and stacking the overlapping parts on a predetermined mounting main body part.
【請求項11】 前記実装本体部および折返部ならびに
重畳部を形成する配線板は一枚の透明な樹脂フィルムか
らなっていることを特徴とする請求項10記載の半導体
装置の製造方法。
11. The method of manufacturing a semiconductor device according to claim 10, wherein the wiring board that forms the mounting main body portion, the folded portion, and the overlapping portion is made of one transparent resin film.
【請求項12】 前記実装本体部上に重畳部を積み重ね
る際、前記重畳部を接着剤や接着テープで仮固定するこ
とを特徴とする請求項10または請求項11記載の半導
体装置の製造方法。
12. The method of manufacturing a semiconductor device according to claim 10, wherein, when stacking the superposed portion on the mounting main body portion, the superposed portion is temporarily fixed with an adhesive or an adhesive tape.
【請求項13】 一面に外部端子を設けた透明な配線板
からなる少なくとも一つの実装本体部と、少なくとも半
導体チップを含む電子部品を搭載した配線板からなる一
つの重畳部と、前記実装本体部と前記重畳部のうち同種
または異種のものを電気的かつ機械的に連結する可撓性
の配線板からなる少なくとも一つの折返部とを有し、前
記重畳部は前記折返部で折り返えされて所定の実装本体
部や重畳部上に積み重ねられる半導体装置を実装基板に
実装する方法であって、前記実装基板のランド上に前記
実装本体部の外部端子を重ねて加熱して外部端子を前記
ランドに固定した後、前記実装本体部の透明な配線板を
通して外部端子の接続状態を検査し、その後前記実装基
板に固定した実装本体部上に前記重畳部を重ねることを
特徴とする半導体装置の実装方法。
13. A mounting main body part made of a transparent wiring board having external terminals provided on one surface, one superposed part made of a wiring board mounting an electronic component including at least a semiconductor chip, and the mounting main body part. And at least one folding portion formed of a flexible wiring board that electrically and mechanically connects the same kind or different kinds of the overlapping portions, and the overlapping portion is folded back at the folding portion. A method of mounting a semiconductor device to be stacked on a predetermined mounting main body portion or a superposed portion on a mounting substrate, wherein the external terminal of the mounting main body portion is overlaid on a land of the mounting substrate to heat the external terminal. After being fixed to the land, the connection state of the external terminals is inspected through the transparent wiring board of the mounting main body, and then the superposing section is superposed on the mounting main body fixed to the mounting board. How to install the device.
【請求項14】 前記実装本体部上に重畳部を積み重ね
る際、前記重畳部を接着剤や接着テープで固定すること
を特徴とする請求項13記載の半導体装置の実装方法。
14. The method of mounting a semiconductor device according to claim 13, wherein, when stacking the overlapping portion on the mounting body portion, the overlapping portion is fixed with an adhesive or an adhesive tape.
【請求項15】 配線板からなりかつ外部端子はスルー
ホールの内壁とその縁に設けた導体層で形成される少な
くとも一つの実装本体部と、少なくとも半導体チップを
含む電子部品を搭載した配線板からなる一つの重畳部
と、前記実装本体部と前記重畳部のうち同種または異種
のものを電気的かつ機械的に連結する可撓性の配線板か
らなる少なくとも一つの折返部とを有し、前記重畳部は
前記折返部で折り返えされて所定の実装本体部や重畳部
上に積み重ねられる半導体装置を実装基板に実装する方
法であって、前記実装基板のランド上に前記実装本体部
の外部端子を重ねた後、前記ランドまたは外部端子にあ
らかじめ設けられた接合材を溶かして前記外部端子を前
記ランドに接続し、その後前記実装本体部のスルーホー
ル内に吸い上げられた接合材の有無によって外部端子の
接続状態を検査し、ついで前記実装基板に固定した実装
本体部上に前記重畳部を重ねることを特徴とする半導体
装置の実装方法。
15. A wiring board which comprises a wiring board and whose external terminals include at least one mounting body formed of an inner wall of a through hole and a conductor layer provided on an edge thereof, and a wiring board on which an electronic component including at least a semiconductor chip is mounted. And one at least folding portion formed of a flexible wiring board that electrically and mechanically connects the same type or different types of the mounting body portion and the overlapping portion, The superposition section is a method of mounting a semiconductor device that is folded back at the folding section and stacked on a predetermined mounting main body section or the superposition section onto a mounting board, wherein the mounting main body section is externally mounted on the land of the mounting board. After stacking the terminals, the bonding material provided in advance on the land or the external terminal was melted to connect the external terminal to the land, and then sucked into the through hole of the mounting body. A method for mounting a semiconductor device, comprising: inspecting a connection state of external terminals depending on the presence or absence of a bonding material, and then stacking the overlapping portion on a mounting main body portion fixed to the mounting substrate.
【請求項16】 前記接合材を溶かして前記スルーホー
ル部分の外部端子を前記ランドに接続した後、前記スル
ーホール内に吸い上げられた接合材にプローブ・ピンを
当てて電気特性検査を行うことを特徴とする請求項15
記載の半導体装置の実装方法。
16. The electrical characteristics test is performed by melting the bonding material and connecting the external terminal of the through hole portion to the land, and then applying a probe pin to the bonding material sucked into the through hole. Claim 15
A method for mounting a semiconductor device as described above.
【請求項17】 前記実装本体部上に重畳部を積み重ね
る際、前記重畳部を接着剤や接着テープで固定すること
を特徴とする請求項15または請求項16記載の半導体
装置の実装方法。
17. The method of mounting a semiconductor device according to claim 15, wherein, when stacking the superposed portion on the mounting main body portion, the superposed portion is fixed with an adhesive or an adhesive tape.
JP33663795A 1995-12-25 1995-12-25 Manufacturing method of semiconductor device Expired - Fee Related JP3942206B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33663795A JP3942206B2 (en) 1995-12-25 1995-12-25 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33663795A JP3942206B2 (en) 1995-12-25 1995-12-25 Manufacturing method of semiconductor device

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2002344930A Division JP2003158221A (en) 2002-11-28 2002-11-28 Semiconductor device, its manufacturing method, and its mounting method
JP2002344932A Division JP3795451B2 (en) 2002-11-28 2002-11-28 Mounting method of semiconductor device

Publications (2)

Publication Number Publication Date
JPH09181215A true JPH09181215A (en) 1997-07-11
JP3942206B2 JP3942206B2 (en) 2007-07-11

Family

ID=18301229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33663795A Expired - Fee Related JP3942206B2 (en) 1995-12-25 1995-12-25 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP3942206B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004105128A1 (en) * 2003-05-20 2004-12-02 Fujitsu Limited Semiconductor package
KR100460062B1 (en) * 2002-04-23 2004-12-04 주식회사 하이닉스반도체 Multi chip package and manufacturing method thereof
JP2007243207A (en) * 1999-08-19 2007-09-20 Seiko Epson Corp Wiring board and its manufacturing method, electronic component and its manufacturing method, circuit board, and electronic equipment
USRE45023E1 (en) 2000-10-16 2014-07-22 Naos Innovation, Llc Three-axis magnetic sensor, an omnidirectional magnetic sensor and an azimuth measuring method using the same
US20150192961A1 (en) * 2013-04-28 2015-07-09 Boe Technology Group Co., Ltd. Flexible substrate, display device and method for bonding electronic devices on flexible substrate

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101467517B1 (en) * 2013-03-22 2014-12-01 송유진 Stack-type semiconductor package and method of manufacturing the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007243207A (en) * 1999-08-19 2007-09-20 Seiko Epson Corp Wiring board and its manufacturing method, electronic component and its manufacturing method, circuit board, and electronic equipment
JP4716038B2 (en) * 1999-08-19 2011-07-06 セイコーエプソン株式会社 Electronic component and manufacturing method thereof
USRE45023E1 (en) 2000-10-16 2014-07-22 Naos Innovation, Llc Three-axis magnetic sensor, an omnidirectional magnetic sensor and an azimuth measuring method using the same
KR100460062B1 (en) * 2002-04-23 2004-12-04 주식회사 하이닉스반도체 Multi chip package and manufacturing method thereof
WO2004105128A1 (en) * 2003-05-20 2004-12-02 Fujitsu Limited Semiconductor package
US7279778B2 (en) 2003-05-20 2007-10-09 Fujitsu Limited Semiconductor package having a high-speed signal input/output terminal
US20150192961A1 (en) * 2013-04-28 2015-07-09 Boe Technology Group Co., Ltd. Flexible substrate, display device and method for bonding electronic devices on flexible substrate
US9651996B2 (en) * 2013-04-28 2017-05-16 Boe Technology Group Co., Ltd. Flexible substrate, display device and method for bonding electronic devices on flexible substrate

Also Published As

Publication number Publication date
JP3942206B2 (en) 2007-07-11

Similar Documents

Publication Publication Date Title
TWI430438B (en) Multilayer wiring substrate, stack structure sensor package, and method of manufacturing stack structure sensor package
US6646338B2 (en) Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument
EP1156705B1 (en) Wiring board, semiconductor device and method of producing, testing and packaging the same, and circuit board and electronic equipment
US6087716A (en) Semiconductor device package having a connection substrate with turned back leads and method thereof
US7679178B2 (en) Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof
KR20010090540A (en) Semiconductor device and process of prodution of same
JP2010093109A (en) Semiconductor device, method of manufacturing the same, and method of manufacturing semiconductor module
JP2011040602A (en) Electronic device and manufacturing method therefor
KR101046117B1 (en) Semiconductor device and manufacturing method thereof
JP2895022B2 (en) Manufacturing method of chip scale package
JP3074264B2 (en) Semiconductor device and its manufacturing method, lead frame and its manufacturing method
JP3942206B2 (en) Manufacturing method of semiconductor device
JP4191169B2 (en) Semiconductor device and mounting body
JP4038021B2 (en) Manufacturing method of semiconductor device
JP2003158221A (en) Semiconductor device, its manufacturing method, and its mounting method
JP3795451B2 (en) Mounting method of semiconductor device
US6645794B2 (en) Method of manufacturing a semiconductor device by monolithically forming a sealing resin for sealing a chip and a reinforcing frame by transfer molding
JP2001223325A (en) Semiconductor device
JP2669756B2 (en) Surface mount components and semi-finished products
JP4374251B2 (en) Semiconductor device
JP3076953B2 (en) TGA type semiconductor device
JPH0846077A (en) Ball grid array type semiconductor device and its manufacture
CN114999927A (en) Semiconductor package structure and manufacturing method thereof
JPH1022605A (en) Method for mounting hybrid electronic parts onto board
JPH0590335A (en) Semiconductor device

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20040415

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050315

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050516

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060124

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060324

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20060914

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20060914

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20061215

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20061215

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070320

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070403

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110413

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120413

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130413

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130413

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140413

Year of fee payment: 7

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees