JPS58145157A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58145157A JPS58145157A JP2963082A JP2963082A JPS58145157A JP S58145157 A JPS58145157 A JP S58145157A JP 2963082 A JP2963082 A JP 2963082A JP 2963082 A JP2963082 A JP 2963082A JP S58145157 A JPS58145157 A JP S58145157A
- Authority
- JP
- Japan
- Prior art keywords
- type
- film
- substrate
- regions
- type regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 claims abstract description 6
- 239000010407 anodic oxide Substances 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 abstract description 6
- 229910052984 zinc sulfide Inorganic materials 0.000 abstract description 4
- 239000005083 Zinc sulfide Substances 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052738 indium Inorganic materials 0.000 abstract description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 abstract description 2
- DRDVZXDWVBGGMH-UHFFFAOYSA-N zinc;sulfide Chemical compound [S-2].[Zn+2] DRDVZXDWVBGGMH-UHFFFAOYSA-N 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 2
- 238000007254 oxidation reaction Methods 0.000 abstract 2
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 10
- 238000009413 insulation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910004613 CdTe Inorganic materials 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000003623 enhancer Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 150000003498 tellurium compounds Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
＋ａ＋ 発明の技術分野
本発明は半導体装置の製造方法に係り、特に水銀・カド
ミウム・テルル化合物半導体を用いて集積回路装置を製
造する方法に関する。Detailed Description of the Invention +a+ Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an integrated circuit device using a mercury-cadmium-tellurium compound semiconductor.
ｔｂ＋ 従来技術と問題点
かねてより水銀・カドミウム・テルル（以下これをＨｇ
ＣｄＴｅと略記する）化合物半導体は、高い移動度（７
７にで敵方ｃｒｄ ／ Ｖ ｓｅｃ ）を示す半導体と
して知られている。このｔＬｇｃｄＴｅ基板上にＭｉｓ
型のＦ’ Ｋ ′ｌ’素子を形成すれば、高速の集積回
路を実現することが出来る。更に高速の集積回路装置を
構成ｊるには、同一基板上にエンハンスメン１！ｉν及
びディブレジョン型双方のＭ Ｉ Ｓ ト’ ＩＥ
’Ｉ”素子を形成することが望ましく、従って同一基板
内に選択的に所望濃度のｐ型領域とｒ１型領域を形成し
、しきい値を制御−１ねばならない。そＩ′１にＬＬ
ＩＩ Ｉｔ Ｃｄ ’ｌ’ Ｌ＋基板にイオン注入法を
用いてデー１電極ｌＩ！！、’Ｆ“にポｌ」ン・イオン
（Ｂ＋）等を所望濃度に注入−４る方法かあるが、ごの
方法は高価なイＡンｔ］＜人装置を要し、Ｍ造コストが
商くなる。tb+ Conventional technology and problems It has been known for some time that mercury, cadmium, tellurium
Compound semiconductors (abbreviated as CdTe) have high mobility (7
It is known as a semiconductor exhibiting an adversary crd/V sec) of 7. Mis on this tLgcdTe substrate
By forming F' K 'l' type elements, high-speed integrated circuits can be realized. In order to construct an even faster integrated circuit device, an enhancer 1! M I S to 'IE of both iν and diversion type
It is desirable to form an 'I' element, therefore, it is necessary to selectively form a p-type region and an r1-type region with a desired concentration in the same substrate, and to control the threshold value by -1.
II It Cd 'l' De 1 electrode lI! using ion implantation method on L+ substrate. ! There is a method of injecting pol ions (B+) etc. into 'F' to a desired concentration, but this method requires expensive equipment and requires high manufacturing costs. Become a business.
（ＣＩ 発明の目的
本発明の１」的は」二記問題点を解消し、＋１ ［Ｃ旧
゛ｅ基板１−にティプレジョン型及ヒエンハンスメント
１Ｂ′ｌ双方のＭｉｓ Ｆｌシ′Ｆ素子を容易に形成
し得る実用的な半導体装置の製造方法を提供するごとに
ある。(CI OBJECTS OF THE INVENTION The object of the present invention is to solve the problems mentioned above and to solve the problems mentioned above and to solve the problems mentioned above. The object of the present invention is to provide a practical method for manufacturing a semiconductor device that can be easily formed.
（（１）発明の構成
本発明は、ＩＩｇＣｄＴｅＭ ｈ Ｊ−に構成したＩｖ
ｉ ｌ Ｓダイオードか絶縁膜とし゛（陽極酸化膜を含
む場合には負のフラットバンド電圧を呈し、陽極酸化膜
を含まない場合には正のフラットバンド電圧を呈すると
いう現象を利用するもので、その特徴は、−導電型を有
するＨｇＣｄＴｅ基板表面の所定領域に逆導電型不純物
を導入して複数個の逆導電型領域を形成した後、前記複
数個の逆導電型領域の内から選ばれた所定の逆導電型領
域対に挾まれた区域表面に選択的に陽極酸化膜を形成す
る工程を含むことにある。((1) Structure of the Invention The present invention provides an Iv configured in IIgCdTeM h J-.
i l S diode or insulating film (it takes advantage of the phenomenon that if it contains an anodic oxide film, it exhibits a negative flat band voltage, and if it does not contain an anodic oxide film, it exhibits a positive flat band voltage; The feature is that - after introducing an opposite conductivity type impurity into a predetermined region on the surface of a HgCdTe substrate having a conductivity type to form a plurality of opposite conductivity type regions, a predetermined region selected from among the plurality of opposite conductivity type regions is introduced. The method includes the step of selectively forming an anodic oxide film on the surface of the area sandwiched between the pair of regions of opposite conductivity type.
（ｅｌ 発明の実施例
以下本発明の一実施例として、ｐ型１（ｇＣｄＴｅ基板
上にディブレシロン型及びエンハンスメント型のＭＩＳ
ＦＥＴを形成する例を、第１図〜第６図の要部断面
図により製造工程の順に説明する。Embodiment of the Invention Below, as an embodiment of the present invention, a p-type 1 (dibresilon type and enhancement type MIS on a gCdTe substrate) will be described.
An example of forming an FET will be explained in the order of manufacturing steps with reference to main part sectional views of FIGS. 1 to 6.
まず第１図に示す如（、ｐ型１１ｇｃｄＴｅ基板１表面
にリフトオフ法等により、前記基板１表面の所定部分に
インジュウム（Ｉｎ）層２を形成し、次いで加熱処理を
施して上記Ｉｎを基板ｌ内に拡散せしめ、ｎ１型領域３
，４．５を形成する。このあと前記基板１表面に被着せ
るＩｎを除去する。ここまでの工程は通常の製造工程に
従って進めて良い。First, as shown in FIG. 1, an indium (In) layer 2 is formed on a predetermined portion of the surface of a p-type 11gcdTe substrate 1 by a lift-off method or the like. n1 type region 3
, 4.5. Thereafter, the In deposited on the surface of the substrate 1 is removed. The steps up to this point may be carried out according to normal manufacturing steps.
次いで第２図に示す如く、上記基板ｌを苛性カリ溶液６
中に炭素（Ｃ）等からなる電極７と対向させて浸漬し、
基板１に対し電極７に１−の電圧を印加する等の方法に
より、基板ｌ全面に陽極酸化法を施し、ｗ４３図に見ら
れる如く陽極酸化膜８を例えば凡そ７００〔人〕の厚さ
に形成する。なおこの厚さは特に限定する必要はない。Next, as shown in FIG.
immersed in it facing an electrode 7 made of carbon (C) or the like,
The entire surface of the substrate 1 is anodized by applying a voltage of 1- to the electrode 7 of the substrate 1, and the anodic oxide film 8 is formed to a thickness of, for example, about 700 mm, as shown in Figure W43. Form. Note that this thickness does not need to be particularly limited.
次いで第４図に示ず如く、所定のパターンに従って形成
されたフォトレジスト膜９をマスクとして前記陽極酸化
膜８を選択的に除去し、ｎ１型領域３．４に挾まれた区
域１０上に陽極酸化膜８を残留せしめる。この陽極酸化
膜８のエツチングは、例えば希塩＠（ＨＯ２り溶液に浸
漬する等の方法により実施し得る。なお本工程において
、ｎ＋型領領域４５に挾まれた区域１１上には陽極酸化
膜８を残留せしめない。Next, as shown in FIG. 4, the anodic oxide film 8 is selectively removed using a photoresist film 9 formed according to a predetermined pattern as a mask, and an anode is formed on the area 10 sandwiched between the n1 type regions 3.4. The oxide film 8 is left behind. This etching of the anodic oxide film 8 can be carried out, for example, by immersion in a dilute salt@(HO2) solution.In this step, the anodic oxide film 8 is Do not allow 8 to remain.
このあと上記フォトレジスト膜９を除去したのち、通常
の製造工程に従って第５図に示ずようにｎ＋型領領域３
４．５上、に開口（電極窓） １２を有する硫化亜鉛（
ＺｎＳ）等よりなる絶縁膜１３を、例えばリフトオフ法
を用いて厚さ凡そ３０００ （人〕に形成する。この厚
さも特に限定する必要はないが、設計上或いは製造工程
上の要請を考慮すると凡そ２０００〜６０００ （人〕
程度が望ましいようである。Thereafter, after removing the photoresist film 9, the n+ type region 3 is removed according to the normal manufacturing process as shown in FIG.
4.5 Zinc sulfide (with opening (electrode window) 12 on top)
An insulating film 13 made of ZnS or the like is formed to a thickness of approximately 3000 mm by using, for example, a lift-off method.This thickness also does not need to be particularly limited, but it can be approximately 2000-6000 (people)
It seems that a certain degree is desirable.
次いで上記開口１２部においてｎ＋＋域３，４．５とオ
ーミック接触せるアルミニウム（ＡＡ）電極１４．１５
．１６を形成すると共に、前記絶縁膜１２上の前記ｎ＋
型領領域、５に挾まれた区域１１に対応する位置にＡｌ
ｌ電極１７を形成することにより、第６図に示ず如きｌ
ＩｇｃｄＴｅ化合物半導体を用いた集積回路装置が完成
する。Next, an aluminum (AA) electrode 14.15 is placed in ohmic contact with the n++ region 3, 4.5 at the opening 12.
．． 16 and the n+ on the insulating film 12.
Al is placed at the position corresponding to the area 11 sandwiched between the mold area and 5.
By forming the l electrode 17, the l electrode as shown in FIG.
An integrated circuit device using an IgcdTe compound semiconductor is completed.
上記第６図に示す集積回路装置において、チャネル部（
図の区域１０）に陽極酸化Ｍ８を具備する素子Ａはしき
い値が負となり、チャネル部（図の区域１１）に陽極酸
化膜を有しない素子Ｂのしきい値は正となるため、素子
Ａ及びＢはそれぞれディブレシロン型及びエンハンスメ
ント型のＭＩＳＦＥＴを構成する。In the integrated circuit device shown in FIG. 6 above, the channel portion (
Device A, which has anodized M8 in area 10 in the figure, has a negative threshold, and element B, which does not have an anodic oxide film in the channel part (area 11 in the figure), has a positive threshold. A and B constitute a dibresilon type MISFET and an enhancement type MISFET, respectively.
本発明に係る半導体装置の製造方法によれば、前述の如
（陽極酸化膜を所望部分に選択的に形成することによっ
て、ｌ１ｇｃｄＴｅ化合物半導体基板上にディブレジョ
ン型及びエンハンスメント型の双方の素子を容易に形成
することが出来、従来の製造方法の如く不純物濃度の微
妙な制御を必要としない。従って高速の集積回路装置を
容易に実現することが出来る。According to the method of manufacturing a semiconductor device according to the present invention, as described above (by selectively forming an anodic oxide film on a desired portion, both deresion type and enhancement type elements can be formed on a l1gcdTe compound semiconductor substrate). It can be easily formed and does not require delicate control of impurity concentration as in conventional manufacturing methods.Therefore, a high-speed integrated circuit device can be easily realized.
なお本発明は前記一実施例に限定されることなく、更に
種々変形して実施し得る。Note that the present invention is not limited to the one embodiment described above, and can be further modified and implemented in various ways.
例えば陽極酸化膜を選択的に形成するために上記一実施
例に示した方法は一つの例であって、通常用いられる如
何なる方法を用いても良い。For example, the method shown in the above embodiment for selectively forming an anodic oxide film is just one example, and any commonly used method may be used.
また使用するＨｇＣｄＴｅ化合物半導体基板はｐ型に限
定されるものではなく、ｎ型であっても良い。Further, the HgCdTe compound semiconductor substrate used is not limited to p-type, but may be n-type.
但しｎ型基板を用いた場合には前述の説明中のｎ型とｐ
型を総て反対にすることと、前記一実施例とは反対にチ
ャネル部に陽極酸化膜を設けた素子がエンハンスメント
型となることに留意する。However, when using an n-type substrate, the n-type and p-type in the above explanation
It should be noted that all the types are reversed, and that the element in which an anodic oxide film is provided in the channel portion, contrary to the one embodiment described above, becomes an enhancement type.
更に陽極酸化膜８或いは絶縁１１！ｌ１１３等の厚さ、
絶縁１０１３や電極１４〜１７の材質等も種々選択し得
るものである。Furthermore, an anodic oxide film 8 or insulation 11! Thickness of l113 etc.
Various materials can be selected for the insulation 1013 and the electrodes 14 to 17.
（ｆｌ 発明の詳細
な説明した如く本発明によれば、ディブレジョン型及び
エンハンスメンＩ・型の双方の半導体素子を、ｌＩｇｃ
ｄＴｅ化合物半導体基板上に容易に形成することが出来
るので、ＩＩｇＣｄＴｅよりなる集積回路装置の製作が
容易となり、しかも高価な製造装置を必要としない。(fl As described in detail, according to the present invention, both deregression type and enhancement type I type semiconductor devices can be manufactured by lIgc
Since it can be easily formed on a dTe compound semiconductor substrate, it becomes easy to manufacture an integrated circuit device made of IIgCdTe and does not require expensive manufacturing equipment.
第１図〜第６図は本発明に係る半導体装置の製造方法の
一実施例を、その製造工程の順に示す要部断面図である
。
図において、■はＨｇＣｄＴｅ化合物半導体基板、２は
Ｉｎ層、３〜５はｎ＋型領領域８は陽極酸化膜、９はフ
ォトレシスＩ・膜、ＩＯ及びＩＩはチャネル部、１３は
絶縁膜、１４〜１７は電極を示す。
代理人 弁理士 井桁貞−
第１ 図
第３図
４１ ｐFIGS. 1 to 6 are sectional views of essential parts of an embodiment of the method for manufacturing a semiconductor device according to the present invention, showing the manufacturing steps in order. In the figure, ■ is a HgCdTe compound semiconductor substrate, 2 is an In layer, 3 to 5 is an anodized film in the n+ type region 8, 9 is a photoresis I film, IO and II are a channel part, 13 is an insulating film, 14 to 5 17 indicates an electrode. Agent Patent Attorney Sada Igeta - Figure 1 Figure 3 41 p.
Claims (1)
導電型不純物を導入して複数個の逆導電型領域を形成し
た後、前記複数個の逆導電型領域の内から選ばれた所定
の逆導電型領域対に挾まれた区域表面に選択的に陽極酸
化膜を形成する工程を含むことを特徴とする半導体装置
の製造方法。After introducing an opposite conductivity type impurity into a predetermined region on the surface of a HgCdTe substrate having one conductivity type to form a plurality of opposite conductivity type regions, a predetermined opposite conductivity type impurity selected from the plurality of opposite conductivity type regions is formed. 1. A method of manufacturing a semiconductor device, comprising the step of selectively forming an anodic oxide film on a surface of an area sandwiched between a pair of mold regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2963082A JPS58145157A (en) | 1982-02-23 | 1982-02-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2963082A JPS58145157A (en) | 1982-02-23 | 1982-02-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58145157A true JPS58145157A (en) | 1983-08-29 |
Family
ID=12281401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2963082A Pending JPS58145157A (en) | 1982-02-23 | 1982-02-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58145157A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5188988A (en) * | 1988-07-27 | 1993-02-23 | Texas Instruments Incorporated | Passivation oxide conversion wherein an anodically grown oxide is converted to the sulfide |
-
1982
- 1982-02-23 JP JP2963082A patent/JPS58145157A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5188988A (en) * | 1988-07-27 | 1993-02-23 | Texas Instruments Incorporated | Passivation oxide conversion wherein an anodically grown oxide is converted to the sulfide |
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