JPS58140850A - Pre-reading control system of instruction - Google Patents

Abstract

PURPOSE:To increase the processing speed while maintaining the interchangeability of softwares, by invalidating all contents of an instruction buffer in case the difference is equal to a prescribed value between the instruction address of the instruction buffer and the instruction address of a main storage device. CONSTITUTION:The instructions and data are stored in a main storage device 1, and the instruction following that under execution and its subsequent instructions to be executed are read out and stored in an instruction buffer 2. The address of the instruction to be executed next is stored in a location counter 3, and the address of the next instruction to be stored in the buffer 2 is held at an advanced location counter 4. The address obtained when the writing is carried out to the device 1 is stored in an address register 5 with execution of an instruction. The contents of the counter 3 are subtracted by an arithmetic circuit 6 from the contents of the register 5. The result of the circuit 6 is fed to an output checking circuit 7, and the contents of the buffer 2 are all invalidated if all bits excepting lower 3 bits are all ''0'', the contents of the counter 3 are transferred to the counter 4. Then the instruction is read again to the buffer 2 from the device 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an instruction prefetching method in information processing*ITC such as this electronic computer.

[Inventive technique #IIs weight]

In recent years, as the application of information lI&ll1iIllill has progressed widely, the demand for l&uniform occlusion Φ has increased. This 3c answerbe is becoming more and more popular than ever before. One of them is a method in which the instructions of the central processing unit 111 (hereinafter referred to as 11cPU) of an electronic computer are prepared in advance. This method is used in an over-powered computer, where the command of the next address is important.
The command to carry out the next command, or the command of Fujin, is sent out one after another from the main memory in advance, and the Ai spirit memory inside the CPU (
(instruction buffer) According to this method I, it is possible to successively issue and execute instructions by CPUt2 in parallel.

It can greatly contribute to the same thing as Asahi Tsutsudo.

[back′j[-problems with technology]

However, if the above instruction prefetch method Y is applied as it is to the existing information processing j131Ifi, the following problem will occur. That is, when an event such as rewriting the instruction V in the main memory mm occurs due to the execution of a certain instruction,
For example, when the store instruction ◆ is execution s3, if the instruction at that storage address happens to be in the CPU
;If the instruction has been taken in, a problem will occur if the instruction in the main memory and the instruction in the instruction buffer become different. Figure 41 shows this situation [for illustrative purposes only, t is CP
U and J# are instruction buffers, and J# is a main storage device. The CPU is currently executing a certain instruction V, and the instruction that is scheduled to be executed in the instruction buffer 2o is stored in the instruction buffer 2o, that is, the instruction that is scheduled to be executed by the CPU.
Assume that the instruction stored at location 190b ace has already been taken in. In this situation, the letter C of address a is
Execution by PUMJC≦; Therefore, storage occurs at the top of the main memory 11og2, and the same address C changes. In other words, assume that the instruction at address J#g)ζ in the main memory has been rewritten. However, at this time, C in the instruction buffer 20
Since the wt in # is taken in before the above rewriting occurs, a discrepancy occurs between the contents of the instruction buffer 2o and the main storage device 3o. The CPU did not give up on this, and the old life of the C address stored in the instruction buffer "set"-sh◆[
Because I will execute it! The intended action of Rodala 7 will not be performed correctly.

A PF that avoids such problems and uses an instruction prefetch method
As a manual method for obtaining the above-mentioned V of the processing iA degree by i, several methods as shown below have been considered.

First, there is a method that completely prevents other instructions from being changed to IIF by executing an instruction at a hot address, as in the example of Aiki. However, if the instruction prefetch method is adopted to improve the processing speed of the existing #@ processing device, there is a possibility that a C binary program is created that rewrites two instructions.

The above-mentioned method of stopping the storage of commands t' and 41 is not preferable from the viewpoint of software compatibility.

The method of s2 is unconditional, taking into account the possibility that the instructions stored in the instruction buffer 20 may be replaced when a buffer is generated in the main memory 10 due to the execution of the i instruction. In this case, all the answers in the instruction buffer 2# are invalidated, and the instructions are successively issued from the beginning. This method solves the above-mentioned software compatibility problem, but considering that such things as changing the buds rarely occur in normal programs, even if #4N- is read ahead, the main memory W Device: 10 times C double waste C
There will be more secondary meals. Therefore, compared to the hardware fair cost increase C2 due to the adoption of the instruction look-ahead method, the result is not much higher than that of 14 points, and I do not consider it to be a desirable method.

As another method, the instructions in the main memory mwts- are rewritten 1+ls two-instruction buffer 731) (7) Contents t
'mbe, if the instruction exists in the instruction buffer 20, all instructions in the instruction Δ sofa 20 are focused;
There is a method of simultaneously rewriting the main memory @@10 and rewriting the command in the corresponding instruction buffer 20. However, although each of these methods solves the disadvantages of method C2 of '1712, it requires a considerably large amount of 8-domains, which increases the cost and cost of the information processing device as a whole.
The delta performance ratio becomes even worse.

:Object of the invention] The present invention has been made in consideration of these circumstances.
The purpose is to provide an instruction prefetching method that can simultaneously improve the processing mode of information processing 'Artt while maintaining compatibility with existing software by adding only a small number of 8-domains.

[Summary of the invention]

The present invention includes a first storage device that stores instructions and data, and a second storage device that sequentially stores instructions to be executed next and after the instruction being executed from the first storage device.
A memory *1g of the instruction being executed, a first memory Mml that holds the address of the next instruction to be executed, and a write address of the instruction ◆ that occurs to the first storage device 62. The control of 's4 to hold and the operations used for processing instructions.
In the information processing device C having Ll and an output test path for determining the output of this calculation path, the lth memory 1
When disseminating instructions to s3 and fourth storage device C: j! of the respective stored addresses. If the bit in the specific part indicated by this address difference is gold, then only 1;
Instructions stored in the 82 storage locations W2N! All invalid≦
Then, once again, the commands that are scheduled to be executed from the first command to the next and after are completed, and the second memory is completed.
(Two lives are stored ◆ It is a first order method.

〔Effect of the invention〕

Therefore, according to the present invention, the instruction that has already been prefetched into the storage device of the first storage device 2 is not invalidated, but is corrected only when there is a difference in the starting order between the instruction and the first storage device m1al. It becomes possible to do so. Reason 6: By taking advantage of software compatibility, it is possible to read instructions in advance more effectively than the bulky eight-domain C2. Further, the conventional problem can be solved and processing can be appropriately optimized by prefetching instructions.

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below. FIG. 2 is a factory diagram of an information processing apparatus showing the minimum parts necessary for explaining the present invention. In C2 of the same figure, 1 is data and a command (first memory Mid) to be stored, which is composed entirely of 2 bytes and is addressed in byte units. 2 is C after the command in progress.
The instructions ◆ are scheduled to be executed sequentially, and the main memory 1iK is
1 to a look-ahead control circuit (not shown) 6 2. A *instruction buffer (minimum memory of $2) that stores instructions issued one after another from a look-ahead control circuit (not shown) 6. This instruction buffer 2 can store the maximum number of instructions (8 bytes) in 1. It is configured so that it can be done. 3 is next C;
The logger VII counter serves as a storage device for storing the address of the instruction to be executed.
address)! The advanced 11 allocation counter 1 holds the 6% address v2 every time a new instruction is taken out from the instruction buffer 2 and moves to the next execution stage. Count up. In addition, each time an instruction is read from the main memory 1 and stored in the instruction buffer 2, the held address is counted up by 2. be done.

The mesotsu address register 5 is a fourth storage device, and is a register that stores the address when the continuation/input to the main storage devices 1-2 is performed since the execution of ◆≦2. be. Then 6 executes the instruction i; the operation l&! that performs the necessary operation. 1ill&, r is an output inspection circuit that checks whether all of the outputs of the arithmetic circuit C other than the lower three bits are 0, and its output is sent to a look-ahead control circuit (not shown). Pass 8 is calculation data to calculation mug! Send or
Performance x411vJl! Desired reno star; 62 used for transfer. Note that other registers in the CPU+2, namely the location counter 4. Components other than memory address register 5 are omitted.

Now, in the processor 1 shown in diagram s2, the main memory 1
The operation when plastering is performed on is as follows. In other words, the contents (address) of memory address register 5 are written simultaneously with the operation of writing the command to master register 1.
and the contents of the code 3 register 2 (#bank) are sent via the arithmetic circuit 61 nipath 1, and an operation to subtract the hard # from the former is executed. The resulting difference between the above addresses is sent to the output check 111jII7, and if all but the lower 3 bits are O, the contents of the instruction buffer 2 are completely invalidated by the look-ahead control circuit. At this time, the contents of the location counter 1 are transferred to the advanced location νm/counter 4 &;
The reading of the command from command/4 to 2 is performed again from the beginning. On the other hand, if all but the lower 3 bits of the output of operation tm1g are not 0, the contents of instruction buffer 2 are not invalidated.

Explain the meaning of the imperial works in C2 and above in detail.

Now, suppose that the contents of a't-v*n counter J are Hatake, and the value of memory address register i is b.
At this time, the instruction buffer 2c2 is a, (a −) −ji
), (a + 4"l, (a + 6)j, respectively) may contain instructions for 2Δite members starting from location. On the other hand, each space is a write address that corresponds to main memory field 1. from.

Hot ≦ & I very hot +7 ・・・・・・・・・・・・・・・
...When the relationship (1) is added, the command ΔTsufā- 2C: An address that has a possibility of being captured; and the command 1 to the main storage device 1J. C2. The above relationship (υ is O≦b −a (7・・・・・・・・・・・・・・・・
...L2), and can be shown as a magnitude relationship of address differences. This means that the lower 3 of address MCb-a)
Since this is equivalent to checking whether all bits other than the bits are 0, the customary processing code shown in the second picture book is the address of an instruction that may have already been taken. The contents of the instruction buffer 2 are invalidated only when the instruction is loaded.

As explained above, according to the method of the present invention, the arithmetic circuit 6 included in the CPU is used to store instructions stored in the CPU 2 and the main memory where the instructions are written. Difference from number 1! From this address difference, it is determined whether the contents of the write address have been taken into the instruction buffer (2≦2), so the instruction prefetch method is adopted. In order to maintain C2 well, the amount of 8-domains required is almost negligible, and since the output test path 1 only checks whether all upper bits are O, it can be constructed with a dirt circuit with a high rate of operation. According to method C2 of the present invention, even when writing is performed to the address of an instruction that may be in the instruction buffer 2 but the actual *t''- has not yet been captured, the instruction buffer 2 is This would invalidate the contents, but considering that according to normal software E:, instruction rewriting itself does not occur much, the decrease in efficiency due to C2 can be seen as a problem ≦ 2. .

In this way, the present invention provides a highly practical instruction prefetching method that effectively performs instruction prefetching while maintaining compatibility with existing software at an optimal cost/4 performance, and can be linked to the same processing speed. do.

In the above-described embodiment, the size of the instruction buffer is set to 8 bytes, but it is of course not necessary to limit the size to C2. However, the bit length to check whether all O's are checked by the output inspection circuit 1 changes depending on the size of the instruction/gutufa. 1 (2) As will be understood, the present invention can be implemented in various modifications without departing from its gist.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating problems V when the instruction prefetching method is adopted, and FIG. 2 is a block diagram showing an embodiment Y of the present invention. j (J...cpu, so...instruction buffer, Jo river memory am, 1...main memory, 2...instruction buffer, 1''-CI key counter, 4... Advanced Logistics 3. Counter, 5. Memory.
Address register, 6... Arithmetic circuit, 7... Output inspection circuit, 8... Pass.

Claims (1)

[Claims] The memory location of 'sl to store instructions and data V, and the next and subsequent flit of the executing instruction ◆ - the pre-charged instruction to be executed ◆ Vt A storage device, the address of the pre-powering instruction to be executed next to the instruction being executed & a 3rd @storage device, and the instruction being executed ◆The resulting instruction to the storage MiM of s1 1II4 storage device with write address Vt% and life◆
Here, there is an arithmetic circuit commonly used in sf'L, and an output test path and t to determine whether the specified bit of the output of this arithmetic path meets O or not; Key super second storage 1i [place bl [information J6 that continues to be negative by successively issuing the next instruction
11gI&C-, when writing command ◆ to the first storage device, the above ilIrlIr-step is executed.
1 and the 4th@arrangement/disposal to find the address of the address that was retained and examined, and the special 1 of the above address in the 4th @disposal inspection ■ road! All the instructions stored in the second storage device are invalidated only when it is determined that all the bits for - are O, and 1IIll&! The instruction prefetch control system is characterized in that the first storage device sequentially outputs the pre-power commands ◆ to be executed in the sixth order and thereafter and stores them in the second storage device.