JPS58139473A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the formation of mixing FETs by forming a plurality of normally ON and OFF FET channels on a semi-insulating substrate, respectively forming source and drain electrodes, then etching and removing part of a gate electrode forming part in the channel of the normally OFF FET and forming a gate electrode at the part. CONSTITUTION:The first insulating film 12a of the prescribed shape is formed on a semi-insulating substrate 11, a resist 13a is covered, and normally ON and OFF MESFET channels 15, 16a are formed by ion implantation on the surface layer of the exposed substrate 11. Then, the resist 13a is removed, annealed in AsH3 gas to activate N type impurity in the channels 15, 16a, and source and drain electrodes 17, 18 are respectively formed at the periphery of the surfaces. Thereafter, the center of the region 16a of the normally OFF is etched and removed, a gate electrode 19a is buried, and a gate electrode 19b is formed on the surface of the region 16.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a method of manufacturing a semiconductor device using two types of field effect transistors.

Field effect transistors (hereinafter abbreviated as FETs) can be classified into normally-off type and normally-off type depending on their threshold voltage. When FETs are used in digital integrated circuits, in order to make the integrated circuit highly integrated, normally-off transistors are used as round-blade switching transistors because of the small number of circuit components. Good.

Furthermore, in order to reduce the power consumption of the integrated circuit, it is better to use normally-off transistors as the switching transistors of the inverter.

FIG. 1 shows an example of a basic inverter using a conventional potassium arsenide NFF1 channel Schottky gate FET (hereinafter abbreviated as MES-FET). In this Fig. 1, for an IFi normally-off MES-FET,
2 is a normally-on MES-FgT.

When the input signal terminal 3 is at the so-called -1 level, which is close to the ground potential, the normally-off MES-PET I Fi is in the off state, and the synchronized MES-F is connected to the power supply terminal 5.
Almost no current flows through ET2, so that the potential of output signal terminal 4 is close to the potential of power supply terminal 5, a so-called high level.

Furthermore, when the input signal terminal 3 is at a so-called high level, the normally-off OMBS-FET 1 is in the on state,
When the signal flows from the power supply terminal 5 through the normally-on MES-FET 2, the output signal terminal 3 becomes a so-called low level due to the voltage drop within the normally-off MES-FET 2.

Even when the normally-on MES-FET 2 uses a resistor as a load, the area occupied by the load on the integrated circuit can be reduced.

A conventional method for manufacturing integrated circuits in which normally-on MES-FETs 2 and normally-off MEiS-FETIs coexist on the same wafer is illustrated in Figures 2(a) to 2.
Shown in Figure (d). In these Figures 2 (-~$2), 11 is a semi-insulating substrate, and this semi-insulating substrate 1
A first insulating film 12 is formed on 1, and a resist 1 is formed on it.
Apply 3.

This resist 13 is partially removed by photolithography, and #I2 is further removed using resist 13 as a mask.
As shown in the figure (&), by etching the first insulating film 12, a part of the surface of the semi-insulating substrate 11 is etched.

In this state, atoms such as 81 + Se, which become n-type impurities, are implanted into the semi-insulating substrate 11 by ion implantation, thereby forming a normally-on MES-F.
ET channel 15 is formed.

Next, the resist 13 is removed, a new resist 14 is applied so as to extend over the area (in Fig. 2), a portion of this resist 14 is removed by photolithography, and the resist 14 is used as a mask. By etching the second insulating film 12, a portion of the upper surface of the semi-insulating substrate 11 is produced.

In this state, atoms such as 81 and 8e, which become n-type impurities, are implanted into the semi-insulating substrate 11 by ion implantation, as shown in FIG. 2).
A normally-off MES-FWT channel 16 is formed.

Next, the resist 14 is removed, the semi-insulating substrate is annealed in an AmHs gas atmosphere, and the normally-on M
k: Activates On-type impurities in channel 15 of 8-FgT and channel 16 of normally-off MEs-FET.

Next, as shown in FIG. 2(c), an alloy of Au and Ge of different types is vapor-deposited on the source electrode 17 and the drain electrode 18, and then the source electrode 17 and the drain electrode 417 are etched by photolithography and etching. Electrodes 18 are formed.

Next, one pole of this 2′ & kind, i.e., the source-pole 17
and channel 15 of MES-FET where drain turtle & 18 is normally on and normally off, 1vlEs
-The channel 16 of the FE'f' and the ohmically sensitive structure are heat-treated, and the source is connected to the pole 17 and the O/drain pole 18 in the same manner as shown in Fig. 1g2 (d). By forming one layer 20 for each gate electrode 19 and wiring, a normally-on MES-FET and a normally-off kiEs-FET can be formed in the same semiconductor wafer.

However, in the above conventional method, the normal M
ES-FET channel 15 and normally-off MBS
- In order to form the channel 16 of the FET, it is necessary to separately perform ion plantation of impurities.

There is also a method of forming a channel of a MES-FET using an epitaxial crystal growth method. However, normally-on MBS-FET and normally-off MBS-FET
In ES-FIT, since channel impurity #11 or channel thickness is different, when trying to form two types of jVIEs-FET channels in the same semiconductor wafer by epitaxial crystal growth method, each This required a very sophisticated manufacturing method called selective epitaxial crystal growth of the channels separately, which was rare.

This invention was made in order to eliminate the above-mentioned conventional drawbacks, and it is possible to form channels of normally-on IT and normally-off 0FET in the same wafer, and it is a monolithic integrated circuit in which normally-on 0FET and normally-off 0FET are mixed. The purpose of this invention is to provide a method for manufacturing a semiconductor device that can be used for.

Embodiments of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. Figure 3 (1) to 3E (
d) is a sectional view for explaining the process of the embodiment. In this jIIa figure (&) to figure 3 (y),
The same parts as in FIGS. 2(a) to 2(d) will be described with the same reference numerals.

This third figure (&) or #! In FIG. 3(d), a first insulating film tZa is formed on the semi-insulating base 1i11, and a resist 13 is applied thereon. This resist 13 is partially removed by a photolinder 2, and then the first insulating film tzat is etched using the resist 13& as a mask, thereby producing a part of the surface of the semi-insulating substrate 11O11.

In this state, nJ
By implanting atoms such as 81 and S, which become impurities of IIf, into the surface of the semi-insulating substrate 1, the structure shown in FIG. 3(a) is obtained.
As shown in K, a normally-on MES-FtT channel 15 and a normally-off MES-FET channel 16m are formed.

Next, the resist 13& is removed, the semi-insulating substrate 11 is annealed in an atmosphere of AIHs gas, and the normally-on residence 5-PKTO channel 15 and the normally-off M
The n-type impurity in the channel 16a of the ES-FET is activated.

Next, as shown in No. 3N-), an alloy of Au and G, which is the electrode material for the source electrode &17 and the drain electrode &18, is deposited, and the photo ring 2 is etched.
A source electrode 17 and a first drain electrode are formed.

Next, heat treatment is applied so that the source electrode 17 and the drain electrode 18 are in ohmic contact with the channel 15 of the normally-on MES-FET and the channel 16a of the normally-off MES-FET. t- administer.

Here, considering nff1OFET, the threshold voltage is lower than the source potential in normally-on MES-FgT,
In a normally-off MES-FNT, the potential is higher than the source potential. In addition, if the positive and negative potentials are defined so that the pinch-off voltage itMEs-FET is higher when it is in the off state than when the MES-FET is in the on state, the normally on M
EN-FETO has a higher pinch-off voltage than normally-off MES-FET.

Normally, the impurity concentration of impurities inserted into a semiconductor wafer by ion implantation in a direction perpendicular to the semiconductor wafer can be approximated by a Gaussian distribution, and when the impurity concentration is a Gaussian distribution, the pinch-off voltage V is expressed as It will be done.

Here, 1 is the 11 electric rate of the semiconductor wafer, and 1 of the semiconductor wafer during R9 ion implantation. A projection tensioner with a full surface, 1j is the standard deviation of the impurity am distribution, 11 is the maximum impurity distribution in the semiconductor wafer, q is the bulk charge, etching of the new bar surface hook after th ion implantation The depth is .

As is clear from the above equation, the normally on MES−
In order to set the pinch-off voltage of the channel formed by ion implantation to the pinch-off voltage of a normally-off MES-FET channel, the surface of the semiconductor in which impurities have been implanted may be etched.

Therefore, as shown in FIG. 3-), the semi-insulating substrate 1
Apply resist 21 to the surface of 1o, normally off ME
Resist 21 in the dirt electrode 19 & part of S-FBT
, and the normally-off MES-FFJ of that part is removed.
The surface of the T channel 16m is partially etched, and then the dart electrode 19a of the normally-off MEB-FET is etched.
By depositing the metal material and removing the renost 21, a normally-off MES-FET can be formed.

Furthermore, as shown in FIG. 3(d), source t4k17
In the same manner as in the case of the drain electrode @18, a normally-on MES-FET and a normally-off MES-FET are formed in the same wafer by forming the portion of the dirt electrode 19b and the first layer 20m. can do.

As explained above, in the silver 10 embodiment described above, a normally-on MgS-FET and a normally-off MBS-FET are formed in a single substrate by performing selective ion implantation once on the same substrate. Therefore, a monolithic integrated circuit including normally-on MES-FETs and normally-off MEB-FETs can be easily manufactured.

Furthermore, although the first embodiment described above describes the case where ion implantation is used to form the channel of the MES-FET, as shown in FIG. How to increase the threshold voltage by etching the entire channel of a normally-off MES-FET, even in the case of normally-on MES-FETs and normally-off MES-FETs.
Facilitates monolithic integrated circuits containing ES-PET.

As shown in Figure 4-), a so-called buffer layer with high specific resistance is formed on the semi-insulating substrate 11a by crystal growth by vapor phase epitaxial method, liquid phase epitaxial method, or molecular beam epitaxial method. 22 and normally on M
An n layer constituting the channel 15m of the ES-FET and the channel 16m of the normally-off MES-FET is grown. Then, channel 1fja of normally-on MBS-FET and normally-off MES-FE
If the n-layer except for the T channel 16b is etched and removed, the result will be as shown in FIG. 4(a).

First, as shown in No. 4N-), the source electrode 17m and the drain/electrode 1
Form 8a.

For a normally-on MES-FET, the pinch-off voltage of a channel formed by epitaxial crystal growth is rounded to the pinch-off voltage of a channel of a normally-on MES-FET. Similarly, it is clear that the surface of the #n layer can be etched to make it thinner and smoother.

Therefore, as in the case of the first embodiment, a resist 21a is applied to the surface of the semiconductor wafer as shown in No. 4E(c).
&19co portion of the resist 21m is removed, a part of the surface of the channel 16b of the normally-off MES-FET is etched, and then the entire island material of the dart electrode 190 of the normally-off MES-FET is evaporated, and the resist 21m is removed.
By removing , the 41st
! 1l(c)K As shown, normally off MEN-
PET can be formed.

Furthermore, as shown in FIG. 4 @), the normally-on MES-FET r
-) By forming 1ml1kl9d and the first wiring layer 20b, a normally-on MES-FET and a normally-off MEN-PET can be formed in the same semiconductor wafer 1 without using the selective epitaxial crystal growth method. can.

As described above, according to the method of manufacturing a semiconductor device of the present invention, a plurality of channels of normally-on and normally-off field effect transistors are formed on the surface of a semi-insulating substrate on which Kjll is selectively exposed by ion plantation or epitaxial growth. After forming a source electrode and a drain electrode in this channel, a part of the surface of the part where the dirt electrode is to be formed in the channel of the normally-off field effect transistor is etched, and a dirt electrode is formed on the upper surface. Since we later formed a dirt electrode for a normally-on field-effect transistor, it was possible to form a normally-on field-effect transistor and a normally-off field-effect transistor in the same semiconductor substrate, making it possible to mix normally-on and normally-off field-effect transistors. Monolithic integrated circuits can be easily fabricated.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the basic inverter circuit of a direct-coupled FFI FET logic circuit using an FWT load.
) to FIG. 2(d) are conventional normally-ioned 0MM5-
Figure 3 (a) is a cross-sectional view showing a method for manufacturing a seven-nolithic integrated circuit in which FETs and normally-off MBS-FETs coexist.
) to 3(d) are cross-sectional views for explaining the steps of an embodiment of the method for manufacturing a semiconductor device of the present invention, respectively;
FIGS. 4-) to 4(tl) are cross-sectional views for explaining the steps of another embodiment of the method for manufacturing a semiconductor device of the present invention. 11, lla... Semi-insulating substrate, lZa... First insulating metal, 13m, 21.211-V cyst, 15° 15
m, 16 m, 16 b-...channel,
17.17m...source tli, 18.18m...
Drain electrode, 19 m -194-... dart electrode,
20 m, 20 b - arrangement 1 JIII layer, 22.
...Buffer layer. Patent applicant: Oki Electric Industry Co., Ltd. 1 Figure 211 +3 O 3 m Procedural amendment dated June q, 1980 Commissioner of the Patent Office Harumari Shima 1, Indication of the case Showa S1 Tatami Application No. 11144 2, 113
91g) 4th name Teijin Tai Gi OII construction method 3, person making the amendment Relationship with the case Bonus: Applicant (I9) Oki Electric Co., Ltd. 4, Agent 5, Date of amendment order Showa year month Date (-1) 6, Subject of amendment 11 documents o**owm* theory - 041 7, Contents of amendment 11 per copy 1 household l) - Record 2 purchase line 14 "Potassium" is corrected as "Ilicum" .

Claims (1)

[Claims] Step 1 of forming a plurality of channels of normally-on and normally-off field effect transistors on the upper surface of an insulating substrate by selectively releasing K11m by ion-in synthesis or high-epitaxial growth; A process of forming a source electrode and a drain t& on the channel of the field effect transistor, and etching a part of the surface of the channel corresponding to the r-) electrode of the normally-off field effect transistor, and then forming the gate on that part. A method of manufacturing a conductor crimp, which is different from the step of forming an r-) electrode on the channel of the normally-on field effect transistor after forming an electrode.