JPS58139458A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58139458A
JPS58139458A JP2115282A JP2115282A JPS58139458A JP S58139458 A JPS58139458 A JP S58139458A JP 2115282 A JP2115282 A JP 2115282A JP 2115282 A JP2115282 A JP 2115282A JP S58139458 A JPS58139458 A JP S58139458A
Authority
JP
Japan
Prior art keywords
package
lead frame
semiconductor device
ceramic
melting point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2115282A
Other languages
Japanese (ja)
Inventor
Kazuo Horiuchi
和雄 堀内
Masayoshi Mochizuki
望月　正良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2115282A priority Critical patent/JPS58139458A/en
Publication of JPS58139458A publication Critical patent/JPS58139458A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent a package from cracking or notching by altering the shape of part of a lead frame, and projecting an impact buffering part except an electrode terminal out of the package. CONSTITUTION:Leads 4 of part of a lead frame are aligned and disposed at the periphery of a ceramic base 2, and supported by a low melting point glass 6. The base 2 is covered with a ceramic cover 3, and secured with the glass 6, thereby forming a package 1. A pin 4 of the body 1 at the short side is deformed, and an impact buffer unit 5 which is projected out of the body 1 is disposed. According to this structure, crack or notch produced due to interference to other parts can be prevented, thereby improving the reliability and holding preferable external appearance.

Description

【発明の詳細な説明】 本発明は、サーディツプパッケージ型の半導体装置に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cerdip package type semiconductor device.

従来のサーディツプパッケージ型の半導体装置は、セラ
ミックベースとセラミックキャップを低融点ガラスにて
接着しかつリードを突出形成した構造であった。ところ
が、この構造の場合、製造および出荷工程において、製
品間の衝撃によりパッケージのセラミック、Ｉ！着用低
融点ガラス部等にクラック、割れおよび欠けが発生し、
半導体装置の信頼度、完成外観に問題が生じる。例えば
、製造工場および顧客受入れ工程でのハンドラにおいて
パッケージが衝突する場合や工程および出荷時のマガジ
ン内においても同じモードの不良が発生する。A conventional cerdip package type semiconductor device has a structure in which a ceramic base and a ceramic cap are bonded together using low-melting glass, and leads are formed to protrude. However, in the case of this structure, during the manufacturing and shipping process, impact between the products causes the ceramic of the package, I! Cracks, breaks, and chips may occur in the worn low melting point glass parts, etc.
Problems arise in the reliability and finished appearance of the semiconductor device. For example, the same mode of failure occurs when packages collide in handlers at manufacturing plants and customer acceptance processes, or in magazines during processes and shipping.

本発明の目的は、外部からの機械的衝撃によりパッケー
ジ等がクラック、Ｉｌれ、欠は等を生じることのない半
導体装置を徒供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which a package or the like will not suffer cracks, cracks, chips, etc. due to external mechanical impact.

この目的を達成するため、本発明は、サーディツプパッ
ケージのリードフレームの一部分の形状ｖ習更し、電極
用端子の他に衝撃緩和を目的とし【パッケージ外より突
出させるように構成したものである。In order to achieve this object, the present invention modified the shape of a part of the lead frame of the surdip package, and in addition to electrode terminals, it was configured to protrude from the outside of the package for the purpose of shock mitigation. be.

以下、本発明の一実施例を第１図および第２図により説
明する。これらの図にお、・て、符号２はパッケージ本
体１のセラミックペースであり、周辺には、リードフレ
ームの一部分をなす外部導出用の複数本のり−ド３を整
列配置して低融点ガラス４にて支持している。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In these figures, reference numeral 2 denotes the ceramic paste of the package body 1, and around the periphery, a plurality of leads 3 for leading out to the outside, which form part of the lead frame, are aligned and arranged, and a low melting point glass 4 is arranged. It is supported by

５は、前記セラミックペース２の上部を橿５ようにして
固着するセラミックキャップであり、周辺において低融
点ガラス４でセラミックベース２に固着し、これにより
パッケージ本体１を構成している。Reference numeral 5 denotes a ceramic cap that fixes the upper part of the ceramic paste 2 like a lever 5, and the periphery is fixed to the ceramic base 2 with low melting point glass 4, thereby forming the package body 1.

６は、衝撃緩和部で、リード３のうち、サイド側すなわ
ちパンケージ本体１の長さ方向両端側（短辺肯）の４ビ
ンを変形し、リード３な整列配置しである側面の他の２
９１面すなわちパッケージ本体１り短辺儒におい℃パッ
ケージ本体ｌの外部に突出するよう配置しである。Reference numeral 6 designates a shock absorbing portion in which 4 bins on the side sides of the lead 3, that is, on both lengthwise end sides (short sides) of the pan cage body 1 are deformed, and the other 2 bins on the side faces are arranged in the same alignment as the leads 3.
91, that is, the shorter side of the package body 1 is arranged so as to protrude outside of the package body 1.

本実施例は、リードフレーム自体の一部に衝撃緩和部６
を設けたことにより、外部からの衝撃を衝撃緩和ｓ６に
て酸相し、セラミックベース２、セラミックキャンプ５
、および低融点ガラス４のクラック、欠けおよび割れを
防止することができ、ｌｌ帳性、外観の向上を図り、歩
城向上をも達成できる。In this embodiment, a shock absorbing portion 6 is provided in a part of the lead frame itself.
By providing this, the impact from the outside is reduced to an acid phase by impact mitigation S6, and Ceramic Base 2, Ceramic Camp 5
It is possible to prevent cracks, chips, and breaks in the low melting point glass 4, improve bookkeeping properties and appearance, and improve walkability.

以上説明したように、本発明の半導体装置によれば、衝
撃緩和部を形成したことにより、他部品と干渉してクラ
ック、欠けおよび割れを防止することができ、外観が良
好でかつ信頼性を向上させることができるという効果が
ある。As explained above, according to the semiconductor device of the present invention, by forming the shock absorbing portion, it is possible to prevent cracks, chips, and breaks caused by interference with other components, and the semiconductor device has a good appearance and reliability. The effect is that it can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明による半導体装置の一実施例の平面図
、嬉２図はその側面図である。 １・・・パッケージ本体、２・・・セラミックペース、
３・・・リードフレーム、４・・・低融点ガラス、５・
・・セラミックキャップ、６・・・衝撃緩和部。 代理人　弁坤士　　薄　１）利　幸FIG. 1 is a plan view of an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a side view thereof. 1...Package body, 2...Ceramic paste,
3... Lead frame, 4... Low melting point glass, 5...
...Ceramic cap, 6...Shock mitigation part. Agent Susuki 1) Toshiyuki

Claims (1)

【特許請求の範囲】 ｌ、セラミックのペースとキャップおよびリードフレー
ムを低融点ガラスにより固着するサーデツプパッケージ
渥の半導体装置において、外部からの機械的衝撃をリー
ドフレームに形成した衝撃緩和部により緩和するよう構
成したことを特徴とする半導体装置。 ２、衝撃緩和部は、パッケージの短辺側において外部に
突出したリードフレームの一部分よりなることＶ％黴と
する特許請求の範囲第１項記載の半導体装置。[Claims] l. In a semiconductor device of a surdeep package in which a ceramic paste, a cap, and a lead frame are fixed with a low melting point glass, mechanical shock from the outside is alleviated by a shock absorbing part formed in the lead frame. A semiconductor device characterized in that it is configured to. 2. The semiconductor device according to claim 1, wherein the shock absorbing portion is formed of a portion of a lead frame protruding outward from the short side of the package.
JP2115282A 1982-02-15 1982-02-15 Semiconductor device Pending JPS58139458A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2115282A JPS58139458A (en) 1982-02-15 1982-02-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2115282A JPS58139458A (en) 1982-02-15 1982-02-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58139458A true JPS58139458A (en) 1983-08-18

Family

ID=12046929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2115282A Pending JPS58139458A (en) 1982-02-15 1982-02-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58139458A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0351602A2 (en) * 1988-07-18 1990-01-24 Motorola, Inc. Ceramic semiconductor package having crack arrestor patterns
JPH04277671A (en) * 1991-03-06 1992-10-02 Nec Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0351602A2 (en) * 1988-07-18 1990-01-24 Motorola, Inc. Ceramic semiconductor package having crack arrestor patterns
JPH04277671A (en) * 1991-03-06 1992-10-02 Nec Corp Semiconductor device

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