JPS58139443A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the reliability of a semiconductor device by superposing a film having preferable covering property on the cavity or low reduction part of the film on an Si substrate and oxidizing it, thereby readily flattening the surface. CONSTITUTION:A thermally oxidized film 12 of a P type Si substrate 11 is etched with a resist mask 13 provided, B ions are implanted into the region 14, thereby reactively ion etching deeply it to form a recess. After B ions are again implanted, a plasma CVD SiO2 film 16 is covered, and the film 16 is selectively allowed to remain, thereby forming a fine groove 15 of substantially constant sectional shape. Then, an SiO2 film 17 and a polysilicon 18 are laminated by a CVD method, and wet oxidized to alter the film 18 into an SiO2 film 20. At this time the volume is increased, and the recess 19 is completely buried. Then, a resist 21 is superposed, the surface is flattened, and the films 21, 20, 17 are uniformly etched. Then, an insulating film can be substantially flatly buried in a field region, thereby largely improving the electric characteristics and the yield of a semiconductor device.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device in which a relatively thick insulating film is embedded in a field region [Technical background of the invention and its problems] Semiconductor equipment.

Particularly in MO811 semiconductor devices, a thick insulating film is formed in so-called field regions between elements in order to eliminate insulation defects due to parasitic channels and to reduce parasitic capacitance.

A selective oxidation method is conventionally well known as such an element isolation method. This is an oxidation-resistant mask for the element formation area.
A typical method is to cover the filled region with a silicon oxide film and perform high-temperature oxidation to selectively form a thick oxide film in the filled region. However, in such a selective oxidation method, during the high-temperature oxidation, the field saponified film digs into the edge of the silicon saponified film in the shape of a bird's beak, which causes dimensional errors in the device formation area and also causes problems in integration. This hinders high integration of circuits.

In addition, in such a conventional selective oxidation method, after forming a field oxide film, a surface step about half the thickness of the field oxide film (approximately 0.7 to 1.0 tone) is formed between the field region and the element formation region. Ru.

This remains as a step until subsequent steps, resulting in a subsequent drop in lithography accuracy and reliability at metal wiring gaps.

On the other hand, the BOX method (Mu
ry1+ag 91de 1nto 8th 1conGr
・0ma・ ).

The BOX method will be briefly explained using Fig. 1).

First, as shown in Fig. 1-), for example, a silicon substrate 1
The device forming region is etched using a mask 2, and the silicon substrate 1 in the field region is etched to a desired amount by filling the field film using a normal photolithography process. Next, I
As shown in FIG. J1 (b), an impurity 1 of the same conductivity type as the silicon substrate 1, for example melon in the case of a P-type substrate, is ion-implanted into the field region using the same mask 2 to prevent field inversion. Thereafter, as shown in FIG. 1(c), a silicon oxide film 4 is buried in the field region using a lift-off process.The lift-off process is performed as follows.
Deposit 840g film.

Next, when ettending with ammonium fluoride for 1 minute, P1asma OVD81 deposited on the narrow surface of the step formed at the boundary between the field region and the element formation region.
Since the etching rate of the 0g film is 3 to 20 times faster than that of the flat part, the Plamma OVD 8 on the side of the M section above
40B film is selectively removed. After that, when the mask 2 on the element formation area is removed, the Pla deposited on the mask 2 is removed.
The SMA OVD 8i01 film is also removed, and Plasma OVD 8i01 film 4 is embedded only in the field area. At this time, a narrow groove 5 having a constant cross-sectional shape is left at the boundary between the field region and the element forming region, as shown by the first factor (@).

Next (;, as shown in FIG.
8i0. On the surface of the membrane 6, a certain recess 1 is formed above the thin groove 5.
01 film 6 so that the etching rate is equal to that of the film 6.
The four parts 7 are buried and the surface is made flat. Thereafter, as shown in FIG.
and 0VD8sho0. The film 6 is uniformly etched away,
When further etching is performed to expose the silicon in the element formation region, the field region becomes almost flat and the OVD
8i0. ! $4 and embedded with Plmsma OVD 8101 film 6. Thereafter, desired elements are formed in the element forming region by a conventional method.

In this way, in the OX method, by using reactive ion etching (RIR) without side etching for etching the silicon substrate, the dimensions of the element area are defined only by the mask dimensions formed by the photolithography process, and the element formation It becomes possible to reduce the dimensional error of the area to zero.

Furthermore, since a structure with a completely flat surface can be obtained, the accuracy of subsequent ring graphing can be improved, and the reliability of wiring can also be significantly improved.

However, in this type of method, O V D 810. as shown in the above @1 figure (d). It is difficult to flatten certain recesses 1 on the surface of the membrane 6. Tapping too, the above OVD
840 Yo After depositing the film 6, a fluid film 8 is formed to flatten the surface, but the fluid liquid 1i! 8 may not be inserted sufficiently and a cavity may be formed.

Therefore, even if uniform etching is performed, the cavity remains and cannot be flattened. Furthermore, in the BOX process, when the size of the recess formed in the isolation region becomes smaller, Ii]I
f[ll! In the formation of the insulating film of iJl, no first insulating film remains in the recessed portion. However, when using Plasma OVD 8 i0□ gland as the first insulating film, in a small recess, Plasma
0VD840, P inside the above recess during lift-off processing
lmsma OVD 8401 II will be completely removed.

Therefore, it is necessary to fill the small-sized concave portion flatly with the second insulating film, for example, 0vI) slow II. However, as the dimensions of the recessed portion of the 8i substrate 1 become smaller, one cavity 9a is formed as shown in FIG.
The density of the area becomes low, and during the subsequent etendering of NH and F, the nip rate becomes faster compared to areas where the density is low, resulting in the formation of grooves.

Therefore, when the dimensions of the concave portion of the 81 substrate 1 become smaller, it is difficult to planarize the concave portion.

[Purpose of invention]

An object of the present invention is to be able to completely flatten the surface of the element forming LW4 castle and the field region, and to be able to reliably perform this flattening even if the dimensions of the recessed portion of the field region are reduced. An object of the present invention is to provide a method for manufacturing a semiconductor device that can contribute to improving the electrical characteristics and manufacturing yield of the semiconductor device.

[Summary of the invention]

In the present invention, when manufacturing a semiconductor device, after forming an IJI film on an element formation region of a semiconductor substrate, the first
Using the film as a mask, a semiconductor substrate is selectively edendered to form a recess in the field region of the substrate, and then a lift-off method is used to embed an insulating second film with a groove formed around the recess. 1. Next, an insulating third film is deposited on the second film and the semiconductor substrate so as to fill the grooves, and a fourth film that becomes an insulating film is coated on the third film by an oxidation process. After the coating is applied, at least a portion of the fourth coating is converted into a metal.

In this method, the fourth film is then planarized, and then the entire surface is etched from the fourth film, so that only the element formation region of the semiconductor substrate is etched.

〔Effect of the invention〕

According to the present invention (2), after the formation of the test material II3, a fourth coating with good coverage is provided in the cavity or low density area of the test material !83, and the test material !i!44 is oxidized. This makes it possible to bury an insulating film in the cavity and to protect the low-density area from etching.Thus, even if the recess in the field area of the substrate is small in size, flattening is possible. It can be done in a duck.

In addition, the etching conditions for the third film are not so strict, and all the recesses can be flatly filled with the insulating film, regardless of the dimensions of the recesses on the old substrate. Since unevenness on the semiconductor surface is eliminated, the reliability of the semiconductor device can be improved.

[Embodiments of the invention]

13(1) to (0) are cross-sectional views showing the moxibustion process of a semiconductor M[ according to an embodiment of the present invention. First, FIG.
As shown in 62 semiconductor substrate 1, for example, the plane orientation (10
0) Prepare a P-type silicon substrate 11 with a specific resistance S~5001, form a thermal oxide film 12 with a thickness of, for example, about 5ooX on this substrate ll, and cover the element formation region with a resist film I.
Cover with s (first coating). Then, as shown in FIG. 7 Use J as a mask.

When ion implantation of -Ron is carried out at, for example, 120 K@V, the projected range is 0.45 .mu.m, the standard deviation is 0.11 .mu.m, the lateral spread is 90, 1.4-.mu., and there is a 42 distribution as shown in 14. Thereafter, using the same resist film 13 as a mask, the silicon in the field portion is etched to a depth of about 0.8 μm deeper than the peak of the impurity distribution introduced by the ion implantation to form a recessed portion using, for example, reactive ion etching technology. Thereafter, as shown in FIG. 3(c), using the same mask, 20 to 30 TN ions were applied to the bottom surface of the recess 1.
A second ion implantation is performed at an acceleration voltage of about KeV.

Next, as shown in FIG.
A VD film is deposited, and by the method described above, a thin groove 15 of approximately constant shape is left at the boundary between the Ij area and the element formation area, and the field area mini-Plasax is formed.
Leave OVD 8 i0 @ JIQ l 6 (jN 2 subjects). Incidentally, instead of this OVD Mlg, 8M 01M which is hot and humid, or an oxide film containing phosphorus, arsenic, and melon may be used.

Next, as shown in Figure 1 (-), 1 μm of 8101$17 (third coating) is deposited on the entire surface by, for example, the OVD method, and then this 8i0. On the membrane 17 (: Po1y-8i
1 J (fourth target ##) is deposited to a thickness of 500X by OVD method. Next, as shown in FIG. 3(f), the above r
Oxidize ely-811Ji by steam oxidation method 84
Transforms into 0@flizo.

At this time, 8i0. Since the volume of M71 is approximately doubled, r
! ! The J section 111 is completely filled with 1's.

Next, as shown in FIG. 3(f),
M2 that can flatten the surface of O,1Ilj4F
1 and flatten the surface. Next, as shown in the third factor ω, the above-mentioned test pieces 11id, 81o8, go, and xv are uniformly etched and buried almost flat in the silicon oxide film in the field region.

Here it is! As a second method, a resist may be applied, or a meltable glass film such as phosphorus silicide glass, phosphorus-dfCI silicide film, etc. may be formed and then melted and flattened. After this, an MO811 semiconductor element is formed on the semiconductor substrate.

Thus, according to the method of this embodiment, the surfaces of the element formation region and field region of the substrate 11 can be almost completely flattened. In addition, Psly as the third coating
-841J has a good coverage and is uniformly formed in all parts of the recess 19, and furthermore, the insulating film 2 is formed by oxidation treatment.
0, and its volume doubles, so the recess 19
The surface becomes pure. For this reason, the planarization film 21
The formation of this area becomes a target area, there is no need to worry about the formation of a cavity in this area, and even a recess with a small width can be easily flattened.

In this embodiment, only the case where a PM substrate is used has been described, but it goes without saying that the present invention can also be applied to a case where a Null substrate is used. Furthermore (2, 0 where N and P exist at the same time)
-MO It is also possible to apply to Mm of O&. Also,
As described in Psly-84 as the coating of I83,
Instead, any material may be used as long as it increases in volume through the oxidation process, becomes an insulator, and has good coverage. moreover.

The third film may be an insulating film from the beginning.

Moreover, if impurities are ion-implanted into rely-8i as the third film, the oxidation time will be shortened and the cavity will be easily filled. Furthermore, Po1y-8e does not necessarily need to be completely oxidized. 1. Other modifications may be made in various ways without departing from the gist of the present invention.

[Brief explanation of the drawing]

The first factor (- to (·) is a cross-sectional view showing the manufacturing process of a semiconductor device by the conventional BOX method. Figure 3 (a
) to (- are cross-sectional views showing the manufacturing process of a semiconductor device according to one embodiment of the present invention (1). 11...Silicon substrate, Jffi...Oxide film, 11
...Mask material (first W!I), 14...Field Iosi 1 injection layer, Jj Kawamizo, I II-Plam
ma 0VDrl'o, 1191F (Second II
), IF-OVD 8jOJ ($3 contribution @)
, 11-Po1i-841F (fourth coating), 1
#...Concave portion, 2a--8 section 01 film, 11... Flattening film. Representative Patent Attorney Takeshi Suzue Figure 1 (a) (b) Figure 2 (a)

Claims (3)

[Claims] (1) Step of forming a film in the element formation region ciJ1 of the semiconductor substrate, and using the film I81 as a mask as a mask.
A step of selectively etching a semiconductor substrate to form a recess in the field region of the substrate, a lift-off method I: a step of atomizing the recess ≦= an insulating second film, and forming the film I82 and the semiconductor. On the substrate 6: A step of depositing an insulating third coating, and an oxidation step 1 on the coating II3 above.
: a step of depositing a fourth test material that becomes a more insulating film, a step of oxidizing at least a portion of the fourth film, a step of planarizing the fourth film, and then a step of planarizing the fourth film. 4. A method for manufacturing a semiconductor device, comprising the step of applying an Imaichi ettender to a depth from the film of step 4 to the semiconductor substrate to expose an element formation region of the semiconductor substrate. (2) When forming a concave portion in the field region, ions of an impurity having the same conductivity type as that of the semiconductor substrate are implanted into the semiconductor substrate using the first test object as a mask. A method for manufacturing a semiconductor device according to section 1. (3) When the second insulating film is assembled into the recess, impurities of the semiconductor substrate and the conductive lid are ion-implanted into the bottom of the recess in advance. A method for manufacturing a semiconductor device.