JPS58137026A - Communication system between processors - Google Patents

Abstract

PURPOSE:To attain the reduction of total cost and to minimize the increase in signal lines, by providing the same input and output interface to a master unit, in a system in which memories and processors are connected on a common bus. CONSTITUTION:In a system in which a main storage device 1 and plural processor units 3-5 are connected on a common bus 2, the processor unit for controlling an IO is defined as the master unit 3, and the same interface 7 as input and output interfaces 8, 9 is provided between the master unit 3 and the other slave units 4, 5, and a channel for the communication between processors is formed via the interface 7, then the communication between the processors does not give hindrance for the data transfer on the common bus.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides a memory shared by a plurality of processors tK, a common memory connected to the plurality of processors and the memory vcfiIe. In a computer system comprising a path, a communication path independent of the common bus is provided, and one of the plurality of processors
When a processor is used as a parent unit and another processor is used as a child unit, and communication is performed between the child units, communication between the child unit that is the communication source and the parent unit is performed via the above communication path. Communication between the child unit and the child unit to which the communication occurred is carried out via the above communication channel! This is related to the communication method between the two.

[Prior art and problems]

In a system in which multiple memories, processors, etc. are connected on a common path, communication between each processor is performed via a common bus, and a special path is established between each pair of processor units that communicates. There was a way to do it. The former has the disadvantage that inter-processor communication interferes with data transfer between other processors and memory, and the latter has the disadvantage of increasing the number of signal lines between each unit and increasing costs.

[Purpose of the invention]

The present invention aims to eliminate the above-mentioned drawbacks, and to provide an inter-processor communication method having characteristics such as being able to reduce the overall cost and minimizing the increase in the number of signal lines. [There is.

[Structure of the invention]

Therefore, the communication method between processors of the present invention is
In a computer system in which a main storage device and a plurality of processors/units are connected to a common bus, and a processor unit for input/output control is provided exclusively for controlling input/output, The processor/equipment of the processor is used as a parent unit for inter-processor communication, and the other plurality of processor units are used as child units for inter-processor communication, and the same input/output interface is provided between the parent unit and the plurality of child units. An interface with the following configuration is provided: [This interface is used as a high-signal path for communication between processors, and communication between the parent unit and the child unit is carried out via the above communication path, and communication between the child units is carried out via the above communication path. And that is what you want to do via the parent unit.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing an overview of one embodiment of the inter-processor communication system of the present invention, and FIG. FIG. 3 shows the configuration of one embodiment of the communication path used for one communication, and FIG. 3 shows the configuration of one embodiment of the IO control adapter.

In FIG. 1, l is a main memory, 2 is a common bus, 3 to 5 are processor units, 6 is a communication path for inter-processor communication, 7 is an observation control adapter, 8 to 1
2 is a child side control adapter, 13 is a direct access device, 1
Reference numeral 4 indicates a display, 15 a keyboard, and 16 a printer.

The main memory l is shared by each of the processor units 3 to 5.The common bus 2 includes the main memory l and the processor units 3 to 5.
is connected. Regarding communication between processors, processor 3 is the parent unit, and processor units 4 and 5 are child units. The processor 3 also has an IO control function and performs input/output control for the direct access device 13, display 14, and line printer 16. Communication path 6 is used only for communication between processors. The control adapter 7 is an adapter for IO control of observation, and the control adapters 8 to 1
2 is an adapter for controlling the slave side machine 0. The parent control adapter and child control adapter control the channel and I
When the child unit 4 or 5, which can be considered to perform a function with the O control device, wants to perform the 0 operation, it requests the parent a, = 3 KIO operation via the communication path 6. ! ! When the unit 3 receives an operation request from the child unit 4 or 5, it performs the IO operation on behalf of the child unit 4 or 5.

Further, when the child unit 4 wants to send a message to the child unit 5, the child unit 4 requests the parent unit 3 to communicate with the child unit 5. lI! 3 reads the data of the child unit 4 and sends it to the child unit 5.

Note that the common bus 2 is mainly used when performing block transfer, and the communication path 6 is used when performing data transfer of several bytes smaller than a block.

FIG. 2 shows the configuration of the communication path 6. The communication path 6 includes a data bus, a register selection signal line, a read/write signal line, a group number selection signal line, and a service request (1).
4! It consists of a line, a service request (2) signal line, an interrupt signal line for each enit, and an intra-group unit selection signal line. The data bus has a 9-bit configuration, the register selection signal line has a 6-bit configuration, and the group number
The selection signal line has a 3-bit band configuration. One group consists of eight units, and it is possible to install eight groups of child units as a whole system. Service Required X (1) The signal line has a 1-bit configuration, and Service II!
X (2) The signal line also has a 1-bit configuration. There are a total of eight interrupt decoding lines for each unit, and eight intra-group unit selection signal lines as a whole.

The third factor is the blocking factor of one embodiment of the control adapter 8. In FIG. 3, 17 is a group number register, 18
19 is a comparison circuit, 19 is a decoder, 20-1 and 20-2 are registers, 23 is a multiplexer, 24 is a service request flag, 25 to 29 are AND circuits, 30 is an inverter, 31 is a receiver, and 32 is a driver. There is. Note that each of the control adapters 9 to 12 has the same configuration as the control adapter 8.

The group number register 17 is set with the group number to which the own unit belongs. The comparison circuit 18 compares the group number sent from the parent unit 3 with the contents of the group number register 17, and if the two match, outputs a match signal of logic "1". do. The AND circuit 25 outputs logic rlJ No. 4 when the group number sent from the parent unit 3 matches its own group number and the parent unit specifies the unit number within the group to which its own unit belongs. Output.

The AND circuit 27 sends a 6-bit register selection signal to the control input terminal of the multiplexer 230 on condition that the AND circuit 25 outputs a logic "1" and the read/write signal specifies read. The AND circuit 26 sends a 6-bit register selection signal to the decoder 19 on the condition that the AND circuit 25 outputs logic "1" and the read/write signal specifies write. The decoder 19 includes corresponding AND circuits 2B-1, 28-2, . . . according to the value of the register selection signal.
Send a logic ``1'' signal to one of the . AND circuit 28-
When a logic "1" signal is applied to the left input terminal of the register 20-!, the data on the data bus is passed through the AND circuit 28-z to the register 20-! is set to Multiplexer 23
The registers 20 1-1, 20-2, . ... and outputs the contents of the selected register. The data output from the multiplexer 23 is sent to the parent unit 3 via the driver 32 and the data bus. The unit sets the service request flag 24 when it requests a service from the parent unit 3. outputs a logic rlJ signal when

The output of the AND circuit 29 becomes a unit-specific interrupt signal.

As mentioned earlier, 5tC, a typical example of communication is IO
Invalidation of correspondence table copy (TLB entry) when there is communication for requesting IO control operation from a child unit that does not have a control function to the parent unit, or when there is a change in the logical address-real address correspondence in the child unit 4. As an example in which there is communication to notify the child unit 5 of the change, we will examine the operation of the present embodiment when data is sent from the child unit 4 to the child unit 5.

f) The child unit 4 sets the service request flag 24 to notify the parent unit 3 that there is a service request.

) The parent unit 3 sequentially sends out the group numbers of the units to which the service requirement X (1) K @ is applied onto the group number selection signal line.

■ When the child unit 4 detects that the group number to which it belongs is placed on the group number selection signal line,
A unit-specific interrupt signal is sent to the parent unit 3.

■ When the parent unit 3 recognizes the unit, it sets the corresponding in-group unit F selection signal to logic rlJ, sets the value of the group No. selection signal to the corresponding value, sets the register selection signal to a predetermined value, and sets the read/write signal to the logic rlJ. The value is used as a read and the request from the child unit 4 is fetched, and the amount of information transferred at one time is 1 byte.

■ After interpreting the request from child unit 4, parent unit 3 places it on the 1-byte command data bus and sends it to group N.
Set the O selection signal to the value of the group to which child 22) 5 belongs,
The in-group unit selection signal corresponding to child unit 5 VC is turned on, the register selection signal is set to a predetermined value, the value of the read/ride signal is set to write, and a command is set in the register of child unit 5.

(2) When a command is set in the register specified by '■, the child unit 5 executes an operation according to its contents.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, in a system in which a main storage device and a plurality of processors/units are connected to a common bus, a processor unit for controlling a process unit 0 is connected to a processor unit for inter-processor communication. The parent unit and other processors and child units.
An interface with the same configuration as the input/output interface is provided between the unit and the unit, and this interface is used as a communication path for communication between processors. It is possible to achieve remarkable effects such as being able to minimize the increase in the number of signal lines for intercommunication.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an overview of one embodiment of the inter-processor communication system of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the communication path used for inter-processor communication, and FIG. FIG. 2 is a diagram showing the configuration of one embodiment of an IO control adapter. l...Main storage device, 2...Common bus, 3 to 5.
... Processor unit, 6... Communication path for inter-processor communication %7... Part-side control adapter, 8 to 12... Child-side control adapter, 13... Direct access device, 14. -Display, 15...Keyboard, 16...Printer. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Kyotani Yobu Ya 2 Dia 3

Claims (1)

[Claims] In a computer system in which a main storage device and a plurality of processor units are connected to a common bus & C, and a processor unit for input/output control is also provided, the processor unit for input/output control is also provided.
unit as a parent unit for inter-processor communication, and other multiple processor units as child units for processor-related communication, with the same input/output interface as the parent unit and multiple (D child IF) lQl&c An interface with a configuration is provided, and the interface is used as a communication path for inter-processor communication, and communication between the parent unit and child units is performed via the above communication path, and communication between the child units is performed via the above communication path. and a parent unit.