GB2222283A - Data transfer between modules in a processing system - Google Patents

Abstract

A data processing system has a number of input/output controller modules connected to an I/O bus 14. Each module contains a dual-port memory 25, accessible either from the bus or from a processor 20 in that module. Each dual-port memory contains a number of controller registers, one for each other module. When module X wishes to send a command to module Y it writes the command into controller register X of module Y and then interrupts module Y. This permits fully symmetric message passing between the modules, for messages of arbitrary length, and allows any module to have messages outstanding simultaneously from more than one of the other modules. <IMAGE>

Description

DATA PROCESSING SYSTEM.

Background of the invention This invention relates to data processing systems of the kind having a plurality of modules connected together by means of a bus. The invention is particularly, although not exclusively, concerned with a system in which a plurality of input/output (I/O) controller modules are connected together by means of an I/O bus.

One problem in such a system is that of organising the transfer of messages between the modules.

This problem is complicated by the requirements that the messages may be of arbitrary length, that the message passing scheme should be symmetrical between the modules, and that it should be possible for any module to have messages outstanding simultaneously from more than one of the other modules.

The object of the present invention is to provide a data processing system which meets these requirements.

Summary of the invention According to the invention there is proxZided a data processing system comprising: (a) a plurality of modules, and (b) a bus interconnecting the modules, wherein each module comprises (i) a processing unit, and (ii) a dual-port memory accessible both from the bus and from the processing unit, the memory containing a plurality of controller registers, one for each other module in the system, and wherein, in operation, when any one module (X) requires to send a command to another module (Y), it places the command in controller register X of module Y and then interrupts module Y, and when module Y receives this interrupt, it reads the command from the controller register.

Brief description of the drawings.

One embodiment of the invention will now be described by way of example with reference to the accompanying drawings.

Figure 1 is an overall block diagram of a data processing system.

Figure 2 is a block diagram showing an I/O controller module in nore detail.

Description of an embodiemtn of the invention.

Referring to Figure 1, the data processing system comprises a plurality c data processing modules 10. The processing modules are connected to a plurality of memory modules 11, by way of a memory bus 12. The memory modules 11 form the main memory of the system.

The processing modules 10 are also connected to a plurality of input/output (I/O) controller modules 13, by way of an I/O bus 14. The I/O bus 14 includes data and address lines, for transferring data between the processing modules and the I/O controller modules. The system also includes a central services module (CSM) 15, connected between the memory bus 12 and the I/O bus 14.

Referring now to Figure 2, this shows one of the I/O controller modules 13 in more detail.

The I/O controller module includes a data processor 20, which may be a known microprocessor chip.

The module also includes a random-access memory 21 which acts as a local memory for the processor 20.

The processor 20 communicates with this memory by way of an internal bus 22, consisting of data lines 23 and address lines 24.

The module also includes a further random-access memory 25, referred to herein as the controller interface table (CIT). This has a data input/output port 26, which is connected to the data lines 23 of the internal bus 22 by way of a two-way buffer 27, and is connected to the data lines of the I/O bus 14 by way of a two-way buffer 28. The CIT also has an address input 29 which can receive an address either from the internal bus 22 by way of the buffer 27, or from the I/O bus 14 by way of the buffer 28. Thus, it can be seen that the CIT is operable as a dual-port memory, being accessible either from the I/O bus or the internal bus.

Each I/O controller module also includes a decoder 30, connected to the address lines of the I/O bus 14. This decoder 30 produces a signal ENABLE CIT 1 when it recognises a system-unique base address allocated to this module. Similarly, the decoder 30 produces a signal INTERRUPT when it recognises a system-unique interrupt address allocated to this module.

A further decoder 31 is connected to the address lines of the internal bus 22. This produces a signal ENABLE CIT 2 when it recognises the unique base address on the internal bus.

The INTERRUPT signal is fed to the interrupt input of the processor 20, so as to cause it to interrupt its current operation.

The signal ENABLE CIT 1 and ENABLE CIT 2 are fed to an arbitration circuit 32. If either of these two signals is true, the circuit 32 produces a signal CIT ENABLE, which enables the CIT 25 for reading or writing.

If ENABLE CIT 1 is true, and ENABLE CIT 2 is false, then the arbitration circuit produces a signal SYSTEM SEL, which enables the buffer 28, allowing the CIT to be accessed from the I/O bus. If ENABLE CIT 2 is true, and ENABLE CIT 1 is false, then the arbitration circuit produces a signal BOARD SEL, which enables the buffer 27, allowing the CIT to be accessed from the internal bus 22. If both the enable signals are true, then ENABLE CIT 1 takes precedence.

The CIT 25 in each I/O controller module holds a data structure comprising a plurality of controller registers, one for each I/O controller module in the system. Each controller is allocated exclusive use of the correspondingly numbered controller register in every other controller module in the system. Thus, module N has exclusive use of control register N in every other module. (Register N in module N is unused).

Each controller register holds eight bytes of information. The first byte represents a command, defining an operation to be performed. The most significant bit of this byte is used as a BUSY flag. The meaning of the other seven bytes depends on the particular command.

It can be seen that the above arrangement allows any I/O controller module X to send a command to another I/O controller module Y, as follows.

(1) Module X writes a command into controller register X of module Y, setting its BUSY flag.

(2) Module X writes to the interrupt address of module Y, so as to interrupt the processor in that module.

(3) In response to the interrupt, the processor in module Y examines the BUSY flag in the CIT, and copies those controller registers for which the BUSY flags are set. The BUSY flags are cleared.

In the present example, the following commands are defined.

(1). Initiate.

This is sent from module X to module Y to indicate that module X has placed a block of control information in the main memory 11, to be accessed by module Y. The last seven bytes of the controller register are used to hold a pointer to this bloc.

(2). I/O terminate.

This is sent from module X to module Y to inform it that module X has terminated some I/O operation initiated by module Y. The last seven bytes of the controller register are used to identify which I/O operation this command refers to.

(3). Service request.

This command is sent from one module to another to signal some event, such as for example, that data has been received from an attached peripheral device.

In this case, the last seven bytes of the controller register are used to specify the nature of the service request, and could comprise a pointer to a control block as in the case of the Initiate command.

(4). Acknowledge.

This is sent from the module X to module Y to indicate that module Y has removed data placed in its CIT by module X.

Operation.

As an example of the operation of the system, a data output operation from I/O controller module X to module Y will now be described.

(1). Module X composes a control block, and writes it into the main memory 11 (by way of the CSM 15). This control block defines an I/O data buffer area within the main memory, the length of the data, and a pointer to an area to which status information is to be returned.

(2). Module X writes the data to be transferred into the defined buffer area.

(3) Module X writes an Initiate command into the controller register X in the CIT of module Y.

This command includes a pointer to the control block in the main memory.

(4) Module X writes to the interrupt location of module Y, so as to interrupt the processor in that module.

(5) Module Y reads the controller registers in its CIT.

(6) Module Y returns an Acknowledge command to controller register Y in the CIT of module X.

(7) Module Y interrupts the processor in module X.

(8) When it receives the interrupt module X reads the Acknowledge command, informing it that the message has been received.

(9) Module Y now accesses the main memory 11, so as to read the control block specified in the Initiate command. The control block is then decoded.

(10) Module Y then fetches the data from the buffer and outputs it to the attached peripheral device.

(11) Module Y determines the status of the attached peripheral, and writes it into the status area defined by the control block.

(12) Module Y writes an I/O Terminate command into the controller register Y of module X.

(13) Module Y interrupts module X.

(14) When interrupted, module X reads the controller register, so as to receive the Terminate command.

(15) Finally, module X interrupts the processor in module Y, so as to acknowledge that it has received the Terminate command.

The above description assumed that each module has a separate interrupt location which, when written to, causes an interrupt to the processor in that module, The interrupted processor must then scan all the command bytes in its CIT to determine which are busy.

In an alternative form of the invention, the processor in each module is interupted whenever any of the command registers is written to. The identity of each command byte written to is stored in a first-in-first-out buffer, to allow a plurality of commands to be queued.

It should be noted that the CIT in each module effectively occupies part of the same address space as the local memory 21 within that module, although it is a physically separate memory. In an alternative form of the invention, both the CIT and local memory 21 could be implemented by means of the same dual-port RAM.

In the embodiment described above, communication between the I/O controllers takes place by way of the main memory 11. However, this is not an essential feature of the invention, and in other embodiments of the invention the control block and the data buffer area may reside, for example, in a memory on the I/O bus 14.

Claims (5)

CLAIMS.

1. A data processing system comprising: (a) a plurality of modules, and (b) a bus interconnecting the modules, wherein each module comprises (i) a processing unit, and (ii) a dual-port memory accessible both from the bus and from the processing unit, the memory containig a plurality of controller registers, one for each other module in the system, and wherein, in operation, when any one module (X) requires to send a command to another module (y), it places the command in controller register X of module Y and then interrupts module Y, and when module Y receives this interrupt, it reads the command from the controller register.

2. A system according to claim 1, further including a main memory connected to the bus, wherein at least some of the commands include pointers to blocks of control information in the main memory.

3. A system according to claim 1 or 2 wherein when any one module (X) requires to interrupt another module (Y), it writes to an interrupt location unique to that other module.

4. A system according to any preceding claim, wherein said modules are input/output controller modules.

5. A data processing system substantially as hereinbefore described with reference to the accompanying drawings.