JPS58135115U - negative impedance circuit - Google Patents
negative impedance circuitInfo
- Publication number
- JPS58135115U JPS58135115U JP15955582U JP15955582U JPS58135115U JP S58135115 U JPS58135115 U JP S58135115U JP 15955582 U JP15955582 U JP 15955582U JP 15955582 U JP15955582 U JP 15955582U JP S58135115 U JPS58135115 U JP S58135115U
- Authority
- JP
- Japan
- Prior art keywords
- operational amplifier
- differential operational
- impedance circuit
- resistor
- negative impedance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Networks Using Active Elements (AREA)
- Amplifiers (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例の負性インピーダンス回路を用いた双方
向中継器の回路構成図。第２図は本考案実施例の回路構
成図。第３図は第２図に示す実施例の短絡安定形負性イ
ンピーダンス回路の等価回路図。第４図は本考案実施例
の回路構成図。第５図は第４図に示す実施例の短絡安定
形負性インピーダンス回路の等価回路図。
Ａ・・・差動演算増幅器、Ｔ、、 Ｔ、・・・トランス
、Ｔｒ・・・インピーダンス変榛回路、ノ１．ノ、・・
・線路。
ＪＰ１５ 図FIG. 1 is a circuit configuration diagram of a bidirectional repeater using a conventional negative impedance circuit. FIG. 2 is a circuit configuration diagram of an embodiment of the present invention. FIG. 3 is an equivalent circuit diagram of the short-circuit stable negative impedance circuit of the embodiment shown in FIG. 2. FIG. 4 is a circuit diagram of an embodiment of the present invention. FIG. 5 is an equivalent circuit diagram of the short-circuit stable negative impedance circuit of the embodiment shown in FIG. 4. A...Differential operational amplifier, T...Transformer, Tr...Impedance changing circuit, No.1. of,··
·line. JP15 diagram
Claims (1)
負入力に帰還する抵抗器Ｒ工およびコンデンサＣ１の並
列回路と、上記差動演算増幅器の出力をその正入力に帰
還する抵抗器Ｒ２およびコンデンサＣ２の直列回路と、
上記差動演算増幅器の負入力と共通電位点との間に接続
された抵抗器Ｒとを備え、上記差動演算増幅器の正入力
と共通電位点との間に現われる二端子インピーダンスを
利用する負性インピーダンス回路。A parallel circuit of a differential operational amplifier A, a resistor R and a capacitor C1 that feeds back the output of the differential operational amplifier to its negative input, and a resistor R2 that feeds back the output of the differential operational amplifier to its positive input. and a series circuit of capacitor C2,
a resistor R connected between the negative input of the differential operational amplifier and a common potential point, and a negative sexual impedance circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15955582U JPS58135115U (en) | 1982-10-21 | 1982-10-21 | negative impedance circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15955582U JPS58135115U (en) | 1982-10-21 | 1982-10-21 | negative impedance circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58135115U true JPS58135115U (en) | 1983-09-10 |
Family
ID=30101912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15955582U Pending JPS58135115U (en) | 1982-10-21 | 1982-10-21 | negative impedance circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58135115U (en) |
-
1982
- 1982-10-21 JP JP15955582U patent/JPS58135115U/en active Pending
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