JPS58134582A - Solid-state image pickup device - Google Patents

Solid-state image pickup device

Info

Publication number
JPS58134582A
JPS58134582A JP57017263A JP1726382A JPS58134582A JP S58134582 A JPS58134582 A JP S58134582A JP 57017263 A JP57017263 A JP 57017263A JP 1726382 A JP1726382 A JP 1726382A JP S58134582 A JPS58134582 A JP S58134582A
Authority
JP
Japan
Prior art keywords
substrate
overflow drain
charge
well
picture element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57017263A
Other languages
Japanese (ja)
Inventor
Kunihiro Tanigawa
谷川 邦広
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57017263A priority Critical patent/JPS58134582A/en
Publication of JPS58134582A publication Critical patent/JPS58134582A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/148Charge coupled imagers
    • H01L27/14887Blooming suppression

Abstract

PURPOSE:To avoid blooming due to overflow of charges with a simple construction, by forming an overflow drain consisting of an impurity dope layer as a semiconductor substrate so as to surround each unit picture element. CONSTITUTION:The overflow drain 16 is formed on the surface of a p type substrate 5b, for example, so that the width is narrower than a width L of a picture element separation region 17 and the impurity doped layer having opposite conduction type (n type) as the substrate 5b with W in width around its center is formed. The layer is formed so as to surround a unit picture element 1 and an inverted voltage is applied to the substrate 5b. Thus, a well is formed beneath the overflow drain 16 and the charge plane in it is lowered for the potential, even if charge in the well beneath the picture element overflows, the charge flows in the well beneath the overflow drain, and is not invaded to the well beneath the adjacent picture elements, then no blooming takes place.

Description

【発明の詳細な説明】 f3−)発明の技術分野 本発明は固体撮像装置としての電荷注入装置(以下Cよ
りと略称する)、特にプルーミングを生じないCよりに
関するものである。
Detailed Description of the Invention f3-) Technical Field of the Invention The present invention relates to a charge injection device (hereinafter abbreviated as "C") as a solid-state imaging device, particularly to "C" which does not cause pluming.

(至)技術の背景 近年、半導体製造技術の著しい進歩に伴なって、−次元
あるいは二次元のCよりがごく容易に製作されるように
慶って来ているう Cよりは第1図のようにそれぞれ数■、十数V程度の電
圧が印加される一対の電極gX、2Yからなる画素1を
、絶縁膜で覆われ死生導体基板上に二次元的に配設した
ものである。その受光面60上に投影された結像光の光
励起から生じる半導体基板内電荷4は、まず電極2Y直
下の電位の井戸(以下単に井戸と略記する)811中に
蓄積される。
(To) Technical background In recent years, with the remarkable progress in semiconductor manufacturing technology, it has become easier to manufacture -dimensional or two-dimensional C. A pixel 1 consisting of a pair of electrodes gX and 2Y, to which voltages of about several volts and about ten-odd volts are applied, respectively, is two-dimensionally arranged on a dead and dead conductive substrate covered with an insulating film. Charges 4 within the semiconductor substrate generated from optical excitation of the imaging light projected onto the light receiving surface 60 are first accumulated in a potential well (hereinafter simply abbreviated as well) 811 directly below the electrode 2Y.

しかるのちに垂直方向のシフトレジスタ20からの電圧
操作によってY母線に接続された電極2Y直下の井戸を
いっせいに消滅せしめるならば、該電荷4は電極2x直
下の井戸3aへ一挙に移されるのであるが、この時の状
頗は第1図中の8段目の画素群に見ることができる。こ
の電荷4が移された瞬間に電極2x上にはイメージ電荷
が発生し。
If the wells directly below the electrode 2Y connected to the Y bus are then erased all at once by voltage manipulation from the vertical shift register 20, the charge 4 will be transferred all at once to the well 3a directly below the electrode 2X. , the state at this time can be seen in the pixel group in the 8th row in FIG. At the moment this charge 4 is transferred, an image charge is generated on the electrode 2x.

該イメージ電橋はX母線Xと電子スイッチ11゜111
8、i4を介して電荷増幅器7の出力端子に続出される
。ここで10は水平方向のシフトレジスタ、9はリセッ
トスイッチ、x1〜X4.Yl〜Y4 はそれぞれX母
線X群およびY母線Y群を示す。
The image electric bridge is X bus line X and electronic switch 11°111
8 and i4 to the output terminal of the charge amplifier 7. Here, 10 is a horizontal shift register, 9 is a reset switch, x1 to X4 . Yl to Y4 indicate the X bus line X group and the Y bus line Y group, respectively.

該Cよりの1フレームの撮像が終れば、電子スイツチ8
1〜S4を閉じることにより前記した光励起によって生
じた電荷が移し替えられた井戸8aを消滅せしめる、か
くすれば該電荷は基板中に注入されて消滅するから、次
の1フレームの撮像に備えて作られる新たな井戸の中に
は、改めて光励起による電荷が蓄積される。
When the imaging of one frame from C is completed, the electronic switch 8
By closing 1 to S4, the well 8a to which the charge generated by the photoexcitation has been transferred is made to disappear.In this way, the charge is injected into the substrate and disappears, so that it is ready for the next frame of imaging. In the newly created well, charges are again accumulated due to photoexcitation.

(C)従来技術と問題点 CHDの構造と動作のあらましは以上のとおりであるが
、従来のこのような構造の固体撮像装置つまりCIDで
は、受光面のある1個所に強い光が集中すればその場所
の画素における電極2X、 2Y直下の井戸には電荷が
あふれ、その井戸から流出した電荷が消滅してしまわな
いうちにまわりの画素直下の井戸中に流入してしまうた
めに、いわゆるプルーミングを生ずるという欠点があっ
た。
(C) Prior art and problems The structure and operation of the CHD are summarized above. In the conventional solid-state imaging device, or CID, with this structure, if strong light is concentrated on one spot on the light-receiving surface, The wells directly under the electrodes 2X and 2Y in the pixel at that location are overflowing with charge, and before the charges flowing out of that well are completely eliminated, they flow into the wells directly below the surrounding pixels, causing so-called pluming. There was a drawback that it occurred.

これを避けるため(第2図(a)に見られるように、エ
ビタキシャ〜ウエベを用いて、例えばp型のエビタキシ
ャμ層5aと−えばn型の基板6との間にEとして示し
た逆方向電圧をかけるとか、あるいは第2図(至)に見
られるようK、例えばp型基板bb中に埋込まれたn型
不純物ドー1層(埋込み層)8との間にやはり逆方向電
圧Eを印加するとかいった方法がとられていた。このよ
うにすれば、□たとえ1つの画素直下の井戸に電荷があ
ふれるような現象が起こっても、あふれ九電荷は電圧E
によって生じた電界によって、第8図(へ)の側力らば
、基板1方向に吸引されることに危り、隣接する画素の
、To壕り強く光が当たっておらず、そのために電荷の
あぶれを生じていない他の井戸中に流入することがなく
なり、したがってプμmミングを生じることは危くなる
。ただし第8図(へ)、(至)において17は画素分離
領域である。
In order to avoid this (as shown in FIG. 2(a), by using an epitaxy layer 5a and a substrate 6 of an n type, for example, a p-type epitaxia μ layer 5a and an n-type substrate 6 are separated in the opposite direction shown as E). Alternatively, as shown in Fig. 2 (to), a reverse voltage E is also applied between K and, for example, the n-type impurity dope 1 layer (buried layer) 8 buried in the p-type substrate bb. In this way, even if a phenomenon occurs where charges overflow into the well directly below one pixel, the overflowing charges will be reduced to the voltage E.
Due to the electric field generated by the lateral force shown in FIG. There will be no flow into other wells that are not flailed, and therefore there is a risk of micro-pming occurring. However, in FIGS. 8(f) and (to), 17 is a pixel separation region.

第8図は前記エビタキVヤ!基板を用いた場合の、光が
強く入射した画素a直下における井戸Uにおいて電荷の
溢出が起こっても隣接画素す直下の井戸Zl)Kは電−
が流入しない様子を示したもi″1 のであるが、これ、、:主同じことは埋込み層8を備え
″ま た第2図(6)のCよりKついても同様のことが言え□
 る、ただし第2図(へ)、@および第8図中の15a
は電極1!X、 2Y直下の絶縁膜、15bはフィーμ
ド絶縁膜である。
Figure 8 shows the above-mentioned Ebitaki Vya! When a substrate is used, even if charge overflow occurs in the well U directly below the pixel a where light is strongly incident, the well Zl)K directly below the adjacent pixel will not be charged.
The same thing can be said for K from C in Fig. 2 (6), which has a buried layer 8.
However, Figure 2 (to), @ and 15a in Figure 8
is electrode 1! Insulating film directly under X, 2Y, 15b is fee μ
It is a hard insulating film.

ところが上記のような方、法は大変有効ではあるが、第
1にエビタキシャ/I/りエバが高価であり。
However, although the above-mentioned methods are very effective, the first problem is that the Ebitaxia/I/Rieva is expensive.

第2には埋込み層を形成することには簾中上の複雑さが
伴なうという欠点がある。
A second drawback is that forming the buried layer is extremely complicated.

口)本発明の目的 本発明は上記従来の欠点に鑑みてなされたもので、エピ
タキシャルウェハや埋込み層基板を用いずとも簡単な方
法で電荷の溢出によるプμmミングをなくすることので
きるCよりす危わち固体撮像装置の構造を提供すゐもの
である。
A) Purpose of the present invention The present invention has been made in view of the above-mentioned conventional drawbacks, and is based on C, which can eliminate μm leakage due to charge overflow by a simple method without using an epitaxial wafer or a buried layer substrate. It is intended to provide the structure of a solid-state imaging device.

(e)  発明の構成 そしてこの目的は本発明によれば、半導体基板の一生面
上に受光面を形成し、該受光面上に複数個からなる単位
画素を作シつけた構成において。
(e) Structure and object of the invention According to the present invention, a light-receiving surface is formed on the entire surface of a semiconductor substrate, and a plurality of unit pixels are formed on the light-receiving surface.

プルーミング防止用としての、前記基板と逆導電型の不
純物ドープ層からなるオーバーフロードレイ−ンを舞単
位画素の周囲を囲む形で形成したことを特徴とする固体
撮像装置を提供することによって達成される。
This is achieved by providing a solid-state imaging device characterized in that an overflow drain made of an impurity-doped layer of a conductivity type opposite to that of the substrate is formed to surround each unit pixel to prevent pluming. .

(f)  発明の実施例 以下本発明の実施例を図面によって詳述する、第4図(
6)は本発明による固体撮像装置す力わちCIDの平面
図、また第4図(a)は当該平面図におけZC〜σ断面
図アあって、基板6bの、電極2x。
(f) Embodiments of the Invention Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, as shown in FIG.
6) is a plan view of the solid-state imaging device, that is, CID, according to the present invention, and FIG.

2Yが配設されて、いる側の主面が受光面である。The main surface on the side where 2Y is disposed is the light-receiving surface.

この第4図し)、(至)において、16は例えばp型基
板5bの表面に画素分離領域17の輻りより狭くかつそ
の中心附近にWなる幅(W<L)をもって基板5bと逆
導電型(n型)の不純物ドープ層を構成するように作ら
れたオーバーフロードレインであって、これは第4図@
に見られるように各単位画素lを取囲むように形成され
ていて、しかも第4図イ、)に図示したように基板51
)K対して逆方向電圧が印加されている。
In FIG. 4) and (to), 16 has a width W (W<L) on the surface of the p-type substrate 5b, which is narrower than the radius of the pixel isolation region 17 and near the center thereof, and has conductivity opposite to that of the substrate 5b. This is an overflow drain made to constitute an n-type (n-type) impurity doped layer, and this is shown in Figure 4 @
It is formed so as to surround each unit pixel l as shown in FIG.
) A reverse voltage is applied to K.

このようにしておけばオーバーフロードレイン16直下
には第4図(C)の21a、、21bのような井戸がで
き、その中の電荷面2ga、inは引き下げられるので
、例えば第8図に描いたような画素a直下の井戸Za中
の電荷が溢れるようなことがあっても、この溢れた電荷
、は該画素aを第4図(至)のように取囲む上記オーバ
ーフロードレイン直下の井戸21a、 21b 内に流
れ込むのみであるし、またその流入した電荷は賽易に排
出されるので、右側に隣接する画素すあるいは左側に隣
接する図示しない画素それぞれの直下にできる井戸中に
まぎれ込むことはなく、したがってプルーミングを生じ
る恐れもなくなる。
If this is done, wells like 21a and 21b in FIG. 4(C) will be created directly below the overflow drain 16, and the charge surface 2ga, in therein will be pulled down, so for example, the wells shown in FIG. 8 will be created. Even if the charge in the well Za directly under the pixel a overflows, the overflow charge will be transferred to the well 21a immediately below the overflow drain surrounding the pixel a as shown in FIG. 21b, and the inflowing charge is easily discharged, so it does not get mixed up in the well formed directly under the pixel adjacent to the right side or the pixel (not shown) adjacent to the left side. , thus eliminating the risk of pluming.

ちなみに前記のW(Lなる条件が設定しである理由は、
仮に上記オーバーフロードレイン16の幅がフィールド
絶縁膜151)の輻(tたは素子分離領域17の幅)と
ほとんど等しく作られていると、隣り合う各画素直下の
各井戸がかえってオーバーフロードレイン16直下の井
戸21a、 21N)によってつながれてしまって、こ
れはオーバーフロードレインを設ける以前の一層よりも
一層不都合となるためである。
By the way, the reason for setting the condition W(L) is as follows.
If the width of the overflow drain 16 is made almost equal to the radius (t or the width of the element isolation region 17) of the field insulating film 151), each well directly under each adjacent pixel will instead be made to have a width directly under the overflow drain 16. This is because the wells 21a, 21N) are connected to each other, which is even more inconvenient than the layer before the overflow drain was provided.

なお第4図(至)の平面図中に描かれているX母線Xお
よびY母線Yのそれぞれは上記の台形状を外した厚いフ
ィールド絶縁膜頂上の平坦部に配設されているので、こ
れら母線にシフトレジスタから供給される電圧がオーバ
ーフロードレイン16の効果に影響を与えるという不都
合は起こらない、そしてこのオーバーフロードレイン1
6はイオン注入法あるいは不純物拡散法によって簡単に
形成できるものであるから、このような構造のCHDの
製作はきわめて容易であり、従来のCよりのように高価
なエビタキンヤルウエハを用いる必要もなければ、埋込
み層を形成するような複雑な工程を経る必要もなく、そ
のために安価に素子を製作できる、 第6図は本発明の変形実施例になるCIDの構造を示す
断面図であるが、画素分離領域17の絶縁膜中には素子
分離領域@26が埋込まれておし。
Note that each of the X bus line X and the Y bus line Y drawn in the plan view of FIG. The disadvantage that the voltage supplied from the shift register to the busbar does not affect the effectiveness of the overflow drain 16 does not occur, and this overflow drain 1
6 can be easily formed by ion implantation or impurity diffusion, so manufacturing a CHD with such a structure is extremely easy, and there is no need to use an expensive Evita core wafer like the conventional CHD. Otherwise, there is no need to go through a complicated process such as forming a buried layer, and therefore the device can be manufactured at low cost. FIG. 6 is a cross-sectional view showing the structure of a CID that is a modified embodiment of the present invention. , an element isolation region @26 is embedded in the insulating film of the pixel isolation region 17.

これら電極は互いKW−的に接続された上で基板、:1 5bとの間に所定の電圧VFが印加できるように圧Eの
極性は第4図の場合と逆の−Eとなる。
These electrodes are connected to each other in a KW- manner, and the polarity of the pressure E is -E, which is the opposite of that in FIG. 4, so that a predetermined voltage VF can be applied between these electrodes and the substrate 15b.

こうした構造を採る理由は第5図中和おける画二二ノ 素分離領域17中のオーバーフロードレインを除くGと
して示した部分にチャンネルが形成されることをさける
ためである。
The reason for adopting such a structure is to avoid forming a channel in the portion shown as G excluding the overflow drain in the pixel isolation region 17 in the neutralization shown in FIG.

しかし一般に上記電極25〜絶縁膜15a〜基板5bで
構成されるいわゆるMIS構成体ではいわゆるフラット
バンド電圧VFRは亀となる丸めに、前記所定の電圧V
’Fは零近辺の値てよい場合も多い。
However, in general, in a so-called MIS structure composed of the electrode 25, the insulating film 15a, and the substrate 5b, the so-called flat band voltage VFR is rounded to the predetermined voltage V.
'F may often be a value near zero.

そしてこの画素分離用電極は見方を変えれば遮光の目的
をも果すことになる。
If you look at it from another perspective, this pixel separation electrode also serves the purpose of shielding light.

(2)発明の効果 以上、詳細に説明したように、本発明の固体撮像装置は
その構造が簡単であり、その割には確実麦プy−ミング
防止効果管有するために、5j!用上多大の効果が期待
できる。
(2) Effects of the Invention As described above in detail, the solid-state imaging device of the present invention has a simple structure, and has a relatively reliable puking prevention effect. It can be expected to have many useful effects.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は固体撮像装置すなわちCよりの一般的構成を説
明するための図、第2図(a)、(b)は従来のCID
の構造を示す断面図、第8図は第2図(a)の構造のC
より1に例にとって、溢れた電荷が基板方向へ流されて
行く様子を示す図、第4図(至)、軽)は本発明に係る
Cよりの平面図ならびに該平面図中のC〜σ断面を示し
た図、第4図(Q)は第4図(へ)に描いた各部に生じ
る電位の井戸を示した図、さらに第す図は本発明の変形
実施例を示した図である。 図面において、1 ハlll素、2X、2’lK極、6
bは基板、15bは素子分離領域17を画定するフィー
ルド絶縁膜、16はオーバーフロードレインをそれぞれ
示す、
Figure 1 is a diagram for explaining the general configuration of a solid-state imaging device, that is, C, and Figures 2 (a) and (b) are conventional CID
Figure 8 is a cross-sectional view showing the structure of Figure 2(a).
Taking 1 as an example, a diagram showing how overflowing charges flow toward the substrate, FIG. A diagram showing a cross section, FIG. 4 (Q) is a diagram showing potential wells generated in each part drawn in FIG. 4 (F), and FIG. . In the drawings, 1 Halll element, 2X, 2'lK pole, 6
b indicates a substrate, 15b indicates a field insulating film defining the element isolation region 17, and 16 indicates an overflow drain.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の一生面上に受光面を形成し、該受光面上に
複数個からなる単位画素を作シつけた構成において、プ
ルーミング防止用と□しての、前記基板と逆導電型の不
純物トープ層からなるオーバーフロードレインを各単位
画素の周囲を謹む形で形成したことを特徴とする固体撮
像装置。
In a configuration in which a light-receiving surface is formed on the entire surface of a semiconductor substrate, and a plurality of unit pixels are formed on the light-receiving surface, an impurity tope of a conductivity type opposite to that of the substrate is used to prevent pluming. A solid-state imaging device characterized in that an overflow drain consisting of layers is formed in a respectful manner around each unit pixel.
JP57017263A 1982-02-04 1982-02-04 Solid-state image pickup device Pending JPS58134582A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57017263A JPS58134582A (en) 1982-02-04 1982-02-04 Solid-state image pickup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57017263A JPS58134582A (en) 1982-02-04 1982-02-04 Solid-state image pickup device

Publications (1)

Publication Number Publication Date
JPS58134582A true JPS58134582A (en) 1983-08-10

Family

ID=11939076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57017263A Pending JPS58134582A (en) 1982-02-04 1982-02-04 Solid-state image pickup device

Country Status (1)

Country Link
JP (1) JPS58134582A (en)

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