JPS58134451A - Multiple connection frames - Google Patents

Multiple connection frames

Info

Publication number
JPS58134451A
JPS58134451A JP57016231A JP1623182A JPS58134451A JP S58134451 A JPS58134451 A JP S58134451A JP 57016231 A JP57016231 A JP 57016231A JP 1623182 A JP1623182 A JP 1623182A JP S58134451 A JPS58134451 A JP S58134451A
Authority
JP
Japan
Prior art keywords
leads
base
package
frame
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57016231A
Other languages
Japanese (ja)
Inventor
Hajime Murakami
元 村上
Takeshi Kotaba
甲把　健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP57016231A priority Critical patent/JPS58134451A/en
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to FR8221110A priority patent/FR2521350B1/en
Priority to DE19833300693 priority patent/DE3300693A1/en
Priority to KR1019830000264A priority patent/KR910002035B1/en
Priority to US06/462,060 priority patent/US4691225A/en
Priority to GB08302769A priority patent/GB2115607B/en
Priority to IT19413/83A priority patent/IT1161868B/en
Publication of JPS58134451A publication Critical patent/JPS58134451A/en
Priority to GB08411298A priority patent/GB2138210B/en
Priority to SG361/87A priority patent/SG36187G/en
Priority to SG37587A priority patent/SG37587G/en
Priority to HK708/87A priority patent/HK70887A/en
Priority to HK713/87A priority patent/HK71387A/en
Priority to MY602/87A priority patent/MY8700602A/en
Priority to MY603/87A priority patent/MY8700603A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Abstract

PURPOSE:To obtain multiple connection frames of low cost for a thin package by providing a plurality of separable package bases on a rectangular substrate made of glass epoxy or the like, and froming leads at the base in such a manner capable of connecting to a semiconductor pellet. CONSTITUTION:A through hole 13 is selectively formed on a rectangular substrate 2 made of a glass epoxy plate, on both side surfaces of which copper foils are bonded, the inner wall of the hole is copper plated to connect the plated coppers, independent inner leads 6, outer leads 8 and a connecting part 8A of the leads 6, 8 are then formed, thereby completing the independent leads 5, and connecting the leads with connecting wirings 15. The leads 6 are covered with strip- shaped resin film 16, and Ni-base Au plating is performed on the exposed part. A recess 4 for a pellet is formed at the center, grooves 17 are punched at four peripheral sides along the hole 27, a base 3 is supported at the part 18 to the outer periphery 19, the leads 8 are isolated, and the wirings 15 are cut. When multiple connection frames of this structure are employed, a plurality of packages can be automatically assembled on one substrate, the thickness of the packages can be reduced equivalently to the substrate, the number of steps is reduced, thereby reducing the cost due to high efficiency.

Description

【発明の詳細な説明】 本□発明はキャリアパッケージ履の半導体装置に好運な
多連フレームに関し、４１にパッケージの薄層化、低コ
スト化を実現しかつ半導体装置の自動組立を可能にした
多連フレームに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-frame frame that is suitable for semiconductor devices in carrier packages. This is related to continuous frames.

一般にチップキャリアと称せられるキャリアパッケージ
履の半導体装置は、回路基板上に直接載置してｌ１回路
基板の配一端子と上記半導体装置の外部接続端子とを接
続するだけで実装を完成し得るため、実輪作業の容易化
や上記半導体装置が実装される装置全体の薄型化に有効
であり、その需費は増々増大する傾向にある。しかしな
がら、従来のこの種のパッケージはセラミックな材料と
しかつその製造に際してはグリーンプロセスを使用して
いるため、パッケージ全体の厚さの低減に限界が生じて
薄型化の障害になっている。また、前述のグリーンプロ
セスは多１１ｍにわたるためセラミックの材料価格と合
わせてパッケージ全体が高価格罠なるり更に、セラミッ
クは実装用基板として一般に使用されているガラスエポ
キシ等のプリント回路基板とは熱膨張率が大幅に相違し
ているため、セラミックのパッケージをこの糧のプリン
ト回路基板に直接固着接続したときには温度変化に伴な
ってパッケージとプリント回路基板との間に熱膨張差に
基づく応力が発生し、接続が破損さｒすることかある。A semiconductor device in a carrier package, generally referred to as a chip carrier, can be mounted directly on a circuit board and the mounting can be completed by simply connecting the wiring terminals of the L1 circuit board and the external connection terminals of the semiconductor device. , which is effective in making the actual wheel work easier and making the entire device in which the semiconductor device is mounted thinner, and the demand and cost thereof tends to increase more and more. However, since this type of conventional package is made of ceramic material and uses a green process in its manufacture, there is a limit to the reduction in the overall thickness of the package, which is an obstacle to making it thinner. In addition, since the green process described above involves a length of 11 meters, the entire package becomes expensive when combined with the ceramic material cost.Furthermore, ceramics are different from the thermal expansion of printed circuit boards such as glass epoxy, which are commonly used as mounting substrates. Due to the large difference in thermal expansion coefficients, when a ceramic package is directly bonded to a printed circuit board, thermal expansion stresses will be generated between the package and the printed circuit board as the temperature changes. , the connection may become corrupted.

更に、従来のこの糧のパッケージで間離となる点は、各
パッケージは１個づつ単独にしか製造できないことであ
り、リードフレームのように多連化できないことである
。このため、このパッケージの組立を自動化する際の障
害になり、かつ製造効率の向上に限界が生する等の原因
となっている。A further disadvantage of conventional food packages is that each package can only be manufactured individually, and cannot be made into multiples like lead frames. This poses an obstacle when automating the assembly of this package, and limits the improvement of manufacturing efficiency.

したがって本発明の第厚の目的は、上記したパッケージ
の薄型化、低コスト化を達成ｊることが・：・１：。Therefore, the first object of the present invention is to achieve the above-mentioned thinner package and lower cost.

↑きる多連フレームを提供することにある。本発明の第
２の目的は、上記パッケージのプリント回路基板への実
ｆ＆を容易にすることができる多連フレームＶ提供する
ことにある。更に本発明の第３の目的は、パッケージ組
立の全自動化を可能にすると共に組立効率の向上を図る
ことができる多連フレームな提供することにある。↑The purpose is to provide a multi-frame frame that can be used. A second object of the present invention is to provide a multi-frame frame V that can facilitate the mounting of the above-mentioned package onto a printed circuit board. Furthermore, a third object of the present invention is to provide a multiple frame that enables full automation of package assembly and improves assembly efficiency.

以下、本発明を図示の実施例により説明する。Hereinafter, the present invention will be explained with reference to illustrated embodiments.

凧１図は本発明の多連フレームＩＹ示しており、この多
連フレームｌは短冊状に形成したカラスエポキシ等の板
材からなる基板２と一体ＫＩＩｌｌａ個（本例ｆは５個
）のペース３を多連に形成している。Kite 1 Figure 1 shows a multi-frame IY of the present invention, and this multi-frame I is integrated with a substrate 2 made of a board material such as crow epoxy formed into a rectangular shape, and KIIlla pieces (5 pieces in this example f) of paces 3. are formed in multiple series.

各ペース３は表面中央に半導体素子ベレット取着用の凹
部４を有すると共に、その８曲にはインナリード６を有
し、かつ裏面には前記インナリード６に連絡部７を介し
て接続されたアウタリード８を有しており、これらイン
ナリード、連絡部、アウタリードと↑リード５を構成し
ている。また、前記ベース基板２の両側には適宜ピッチ
（ペース、１へ ３のピッチに等しい）をおいてガイド孔９を連設、′１
・。Each pace 3 has a recess 4 in the center of its surface for attaching a semiconductor element pellet, and has an inner lead 6 in its eight grooves, and an outer lead connected to the inner lead 6 via a connecting part 7 on the back surface. 8, and these inner leads, communication parts, outer leads, and ↑ leads 5 are configured. Further, guide holes 9 are successively provided on both sides of the base substrate 2 at an appropriate pitch (a pitch equal to a pitch of 1 to 3).
・.

している。　　　　□ 次ＫＩＩＪ配多連フレームｌの評細を、第２図人）〜山
に示す製造■柳に従って綬明する。are doing. □ Next, the details of the KIIJ distribution frame 1 will be explained according to the manufacturing process shown in Figure 2.

先ず、内因に示すように、短冊状をしたガラスエポキシ
板ｌＯの表層面（上下面）に夫々導電層としての銅箔１
１，１２を形成した基板２を用意する１次に、（Ｂ）図
に示すように形成されるべきパッケージＰの外縁に沿う
ようにしてかつ形成されるべきリード５に接続され得る
基板２上の位置に上下に貫通するスルーホール１３をリ
ード相嶺数だけ形成する。そして、（Ｃ）図に示すよう
にこのスルーホール１３の内周面に無電解めっきを行な
って前記連絡部７としての鋼めつき層１４を形成し。First, as shown in the internal explanation, a copper foil 1 is placed as a conductive layer on the surface layer surface (upper and lower surfaces) of a rectangular glass epoxy plate IO.
1 and 12 are prepared. 1. Next, as shown in FIG. Through holes 13 penetrating vertically are formed at positions corresponding to the number of lead phases. Then, as shown in Figure (C), electroless plating is performed on the inner circumferential surface of this through hole 13 to form a steel plating layer 14 as the connecting portion 7.

この銅めっき層１４にて上下面の各銅箔１１，１２を導
通し得るようにする。その後、ρ）図、（Ｅ）図に示す
ように基板２の上、下面の各銅箔１１．．１２をホトエ
ツチングし、夫々論文した１数本のインナリード６とア
ウタリード８を形成する。ホトエツチングは、ホトレジ
スト膜形成、パターン露光。This copper plating layer 14 enables conduction between the copper foils 11 and 12 on the upper and lower surfaces. After that, as shown in Figure ρ) and Figure 1E, each copper foil 11. ．． 12 to form several inner leads 6 and outer leads 8, respectively. Photoetching involves forming a photoresist film and exposing the pattern.

埃儂により形成したホトレジストパターン膜を利用して
銅エツチングするものであることは１つまでもない。ま
た、このエツチングに際し、表面のインナリード６は夫
々独立した形状としているが、アウタリード８はパッケ
ージの外縁に沿うよりも外側の部分８Ａにおいて各リー
ドが導通するように形成しており、また各パッケージの
アウタリードを連絡＠１５にて接続させることも行なわ
れる。In many cases, copper etching is performed using a photoresist pattern film formed using dust. In addition, during this etching, the inner leads 6 on the surface are formed into independent shapes, but the outer leads 8 are formed so that each lead is electrically conductive at the outer part 8A rather than along the outer edge of the package. It is also done to connect the outer leads of the terminals at contact@15.

この結果、各インナリーｔ゛６はスルーホール１３内の
鋼めっき層１４を介して各７ウタリーＦ８に接続され、
夫々はインナリード６、スルーホール７、アウタリード
８で独立したリード５を構成するが、前述したアウタリ
ード形状や連絡＠Ｉｓによってこの状ｌＩ′ｒ″は全て
のり−ド５は導通状態にある。As a result, each inner t6 is connected to each of the seven inners F8 via the steel plating layer 14 in the through hole 13,
The inner lead 6, the through hole 7, and the outer lead 8 constitute an independent lead 5, but in this state lI'r'', all the leads 5 are in a conductive state due to the shape of the outer lead and the connection @Is described above.

以上のようにしてリード５を形成した上で、（Ｆ）図の
よう、に基板２の上面のインナリード６の中希部分ニ保
■レジン１６を帯状にスクリーン印刷尋によって形成す
る。この保饅レジン１６は必要に応じて行なえばよ（、
不必要ならば形成しなくても良い。この帯状保膜レジン
１６が塗布されない部分は次ＩＩＩにおいてＮｉ下地め
っきとＡｕめつきを行なう。このめっきは電気めっきで
トリ、前記連結線１５とアウタリード８の導通作事によ
って一本のリードへの電源接続だけで全リードへのめっ
きを行なうことができる。After the leads 5 are formed as described above, a resin 16 is formed in the form of a band by screen printing on the middle rare portions of the inner leads 6 on the upper surface of the substrate 2, as shown in FIG. This Homan Resin 16 can be applied as needed (,
There is no need to form it if it is unnecessary. In the next step III, Ni underplating and Au plating are applied to the areas where the band-shaped film-retaining resin 16 is not applied. This plating is done by electroplating, and by electrically connecting the connecting wire 15 and the outer lead 8, all the leads can be plated by just connecting the power to one lead.

次に０図に示すように基板２の上面、つまりバ・ッケー
ジの中央部分を半導体素子（ペレット）よりも若干大寸
法の方形に座ぐり加工して凹部４を形成し、かつ１図に
示すようにパッケージの外縁に沿って四辺を打抜いて溝
１７を形成する。この溝１７により、形成されるべきパ
ッケージベース３は溝１７間に形成された４本の橋絡部
１８によって外周部（フレーム部）１９に懸吊支持され
た状態とされる。したがって、その後において細巾の橋
絡部１８を切断すればパッケージベース３を簡単に得る
ことができる。また、前記溝１７はその内縁をスルーホ
ール１３に沿わせているため、溝によってスルーホール
１３内部（金めつきされた銅めっき層１４）はベース３
の外縁に露呈される。これと同時に溝１７はアゆタリー
ド８の外儒部位８Ａを打ち抜くので、（１１−に示すよ
うに各アウタリード８は夫々切離されて絶縁状態とされ
、かつ連絡４９１５も切断されて各ベース間て゛の導通
もなくなる。なお、この溝１７の打抜きと同時に基板２
０両側に？８ってｌｌ１Ｉｌ１１ａｌのガイド孔９を形
成するＯ 以上のようにして形成された多連フレームｌは、したが
って従来から存在している金属板からなる多連リードフ
レームと同様にして自動組立工程に供され、半導体素子
（ペレット）の刺止が行なわれる。つ１す、ガイド孔９
を利用して多連フレームｌを長平方向に順送りしながら
ペレットボンダやワイヤボンダに供給し、一方のベース
３ａから他方のベース３Ｃへと組立てを行なう。因みに
、この多連フレームｌへの組立工程は、第３図に断面図
を示すように、ベース３の凹部４内底面に適宜の接着剤
にて半導体素子ペレット２０を固着し、その上で前記イ
ンナリード６め各内―先端とペレット２０の電極パッド
の間をワイヤ２１にて接続する。しかる後、刺止用のレ
ジン２２をパッケージベース３上にボッ”ｆ”（インク
等によって滴下してペレット２０．ワイヤ２１およびイ
ンナリード６を隠蔽刺止することにより完成される。し
たがって、セラミックベースのように１個づつ独立した
ものと異な’ｌ］立ての自動化を可能にしかつ製造効率
の向上を図ることができるの１ある。Next, as shown in Fig. 0, the upper surface of the substrate 2, that is, the center part of the package, is counterbored into a rectangular shape slightly larger than the semiconductor element (pellet) to form a recess 4, and as shown in Fig. 1. A groove 17 is formed by punching out four sides along the outer edge of the package. Due to the grooves 17, the package base 3 to be formed is suspended and supported by the outer circumferential portion (frame portion) 19 by the four bridge portions 18 formed between the grooves 17. Therefore, the package base 3 can be easily obtained by cutting the narrow bridging portion 18 afterwards. Further, since the inner edge of the groove 17 is along the through hole 13, the inside of the through hole 13 (gold-plated copper plating layer 14) is connected to the base 3 by the groove.
exposed at the outer edge of the At the same time, the groove 17 punches out the outer part 8A of the outer lead 8, so that each outer lead 8 is separated and insulated, and the connection 4915 is also cut to connect the bases. There will be no electrical conduction between the substrate 2 and the groove 17.
0 on both sides? 8 forms the guide hole 9 of ll1Il11al. Therefore, the multi-frame frame l formed as described above is subjected to an automatic assembly process in the same way as the conventional multi-lead frame made of metal plates. Then, the semiconductor element (pellet) is punctured. 1, guide hole 9
The multiple frame l is fed to a pellet bonder or a wire bonder while being fed sequentially in the longitudinal direction using a screwdriver, and is assembled from one base 3a to the other base 3C. Incidentally, in the process of assembling this multi-frame frame l, as shown in the cross-sectional view in FIG. The inner tip of each inner lead 6 and the electrode pad of the pellet 20 are connected with a wire 21. After that, the resin 22 for pricking is dropped onto the package base 3 using ink, etc., and the pellets 20, wires 21 and inner leads 6 are hidden and pricked.Therefore, the ceramic base is completed. It is possible to automate the process in a single-by-one manner, as opposed to one by one, and to improve manufacturing efficiency.

そして、以上のように多連フレームｌに組立てを完了し
た後は、橋絡部１８を適宜に切断すれば完成されたパッ
ケージはフレーム部１９から切離され、第４図囚、（Ｂ
）に示すように夫々独立したパッケージとして形成され
るのｒ′ある。図中、２３は実装用基板、２４はプリン
ト回路である。After completing the assembly to the multiple frame l as described above, the completed package can be separated from the frame part 19 by cutting the bridging part 18 as appropriate, as shown in Figure 4 (B).
), each package r' is formed as an independent package. In the figure, 23 is a mounting board, and 24 is a printed circuit.

なお、多連フレームとしては各パッケージの電力供給部
を互に共通線にて導通させた状態で完成させてもよい。Note that the multiple frame may be completed in a state in which the power supply parts of each package are electrically connected to each other through a common line.

ごのようにすれは、パッケージの完成後に前記共通線の
一部に通電するだけで全部のパッケージに同時に通電を
行なうことができ、エージング作業を容易にかつ高能率
に行なうことができる。所定の温度、電圧１時間ｆのエ
ージングの完了後は前記共通線を切断する第２の打抜き
を行なえば、各パッケージを電気的に独立したものとし
て構成ｆきる。In this case, all the packages can be energized at the same time by simply energizing a part of the common line after the package is completed, and aging work can be performed easily and efficiently. After aging for 1 hour at a predetermined temperature and voltage is completed, a second punching process is performed to cut the common line, thereby making each package electrically independent.

ここマ、ベース基板の材料として前Ｐ実施例ではガラス
エポキシを使用しているが、その外にポリエステル、ポ
リイミド、紙フェノール、トリアジン郷を利用してもよ
い。ｆたリードにはワイヤのボンダビリティや半田付は
性を考慮して金めつきを施しているが、場合によっては
ＡＪ＃　ＡＬＮｌめっきを施すようにしてもよい。更に
、パワーＩＣのように放熱性を１視する場合には、ベー
ス３のアウタリード８が形成される面（ベレット付は用
の凹部４形成面とは反対面）にヒートシンクとしての銅
箔を形成すれば良い。この銅箔の形成は、上紀第２図（
Ｅｌにおいて銅箔１２をホトエツチングする時に、アウ
タリード８で囲まれる基板２の領域に上記アウタリード
８とは分離して銅箔が残るようにホトエツチングすれば
艮い。このようにして、ヒートシンクとなる鋼箔を形成
した場合を、第５図に示す。同図において、２５がヒー
トシンクとなる銅箔てトる。他の番号は、上記第２図□
□□）の場合と同じである。Although glass epoxy is used as the material for the base substrate in the previous embodiment, polyester, polyimide, paper phenol, and triazine may also be used. The f leads are gold plated in consideration of wire bondability and solderability, but AJ# ALNl plating may be applied depending on the case. Furthermore, when heat dissipation is taken into account as in a power IC, a copper foil is formed as a heat sink on the surface of the base 3 where the outer leads 8 are formed (the surface opposite to the surface where the recess 4 is formed for the case with a bullet). Just do it. The formation of this copper foil is shown in Figure 2 of the Joki
When photo-etching the copper foil 12 at El, it is possible to do so by photo-etching so that the copper foil remains in the region of the substrate 2 surrounded by the outer leads 8, separate from the outer leads 8. FIG. 5 shows a case in which a steel foil serving as a heat sink is formed in this manner. In the figure, 25 is a copper foil serving as a heat sink. For other numbers, see Figure 2 above □
□□).

又、他の方法として、上記のような銅箔２５形成後ベー
ス３の中央を貫通する穴を形成し、上１銅箔２５がベー
ス表面１１に露出するようにしても良い。この場合半導
体ペレットは上記穴部において、銅箔２５に直接接続さ
れるため放熱特性が一段と良好になる。このようなフレ
ームを用いて、半導体装置を形成した場合を第６図に示
す。同図において、２５はヒートシンクとなる銅箔、２
０は貫通孔内に配置されかつ上記ヒートシンクに固着さ
れた半導体ペレットである。上記ペレット２０はレジン
２２によって橙わｎている。Alternatively, after forming the copper foil 25 as described above, a hole passing through the center of the base 3 may be formed so that the upper copper foil 25 is exposed on the base surface 11. In this case, since the semiconductor pellet is directly connected to the copper foil 25 in the hole, the heat dissipation characteristics are further improved. FIG. 6 shows a case where a semiconductor device is formed using such a frame. In the figure, 25 is a copper foil serving as a heat sink;
0 is a semiconductor pellet placed in the through hole and fixed to the heat sink. The pellet 20 is colored with resin 22.

上記ヒートシンク２５形成において、その厚さが不充分
と思われる場合はめつき或いは他の銅箔を１ねて増摩し
てもよい。又、銅箔の代りに鋼板を使用しても良い。In forming the heat sink 25, if the thickness is deemed insufficient, it may be plated or coated with another copper foil to increase the thickness. Also, a steel plate may be used instead of copper foil.

以上のように本発明の多連フレームによれば、ガラスエ
ポキシ等を材料とする基板に書数個のベースを多連に形
成すると、共に、各ペースにはリードを形成して半導体
装±１（ベレイト）のバツケーー。As described above, according to the multiple frame of the present invention, when a plurality of bases are formed in multiple series on a substrate made of glass epoxy or the like, a lead is formed on each base to form a semiconductor device ±1. (Bereit)'s battle.

ジを可能にしているので、・１．禎畿個のノ・ツケージ
を一枚の基板に組立てることが′ｒ′き、しかもこの組
立ては従来のリードフレームと同様に自動組立機にて行
なうことができるので、パッケージの組立の自動化を図
って船室効率の向上を達成て・きる。・1. Since it is possible to assemble a large number of packages onto a single board, and this assembly can be performed using an automatic assembly machine in the same way as conventional lead frames, it is possible to automate package assembly. Improved cabin efficiency can be achieved.

また、このようにして組立てられた半導体装置によれば
、パッケージ全体の厚さは略基板と同等の厚さで済み薄
型化を図ると共に、製造工程数が少なくかつ効率がよい
ので低コストに製作できる。In addition, with the semiconductor device assembled in this way, the overall thickness of the package is approximately the same as that of the substrate, making it thinner, and the number of manufacturing steps is small and efficient, so it can be manufactured at low cost. can.

更に、ベースは通常０実装用基板と熱膨張率が略等しい
ので実装用基板へ直接パッケージを実装しても接続破損
が生ずることはない等の効果な奏する。Furthermore, since the base has approximately the same coefficient of thermal expansion as that of the mounting board, there is no damage to the connection even if the package is directly mounted on the mounting board.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の多連フレームの概略斜視図、第２図＾
）〜山はその製造工程を示す図で囚、　（Ｂｌ。 （坊、　（Ｆｌ、　ｌｏｔ、　（）Ｉは表斜視図、（Ｑ
は断面図、（Ｅ）、山は皇斜視図、第３図は組立状態の
断面図、第４図囚、（Ｂ）は完成パ、１コケージの斜視
図、第５図は他の実施例による多−フ・−・形成の一工
程を示す農斜視図、第６図台−さらに他の実施例による
多連フレームを用いて、半導体装置を形成したところを
示す断面図である。 ｌ・・・多連フレーム、２・・・基板、３・・・ペース
、４・・・凹部、５・・・リード、６・・・インナリー
ド、７・・・連絡部、８・・・アウタリード、９・・・
ガイド孔、１３・・・スルーホール、１４・・・銅めつ
き層、１５・・・連絡線、１６・・・保論レジン、１７
・・・溝、１８・・・橋絡部、１９・・・フレームＩＳ
、２０・・・ペレット、２１・・・ワイヤ、２２・・・
レジン。 第　　１　　図 第　　３　　図 第　　２　　図 竿２図 （Ｄ） （ξう 第　　２　　図 （Ｆ） 第　　２　図 （Ｈ） 第　　４　　図 （Ａ＞ （７５） 第　　５　　図 第　　６ｒ′ ′、″Figure 1 is a schematic perspective view of the multiple frame of the present invention, Figure 2
) ~ Mountain is a diagram showing the manufacturing process, (Bl. (Bo, (Fl, lot, ) I is a front perspective view, (Q
3 is a sectional view of the assembled state, 4 is a sectional view, (B) is a completed package, a perspective view of 1 cage, and 5 is another embodiment. FIG. 6 is an agricultural perspective view showing one step of forming a multi-frame according to FIG. l...Multiple frame, 2... Board, 3... Pace, 4... Recess, 5... Lead, 6... Inner lead, 7... Connection part, 8... Outer lead, 9...
Guide hole, 13...Through hole, 14...Copper plating layer, 15...Connection line, 16...Horon resin, 17
...Groove, 18...Bridge part, 19...Frame IS
, 20... pellet, 21... wire, 22...
resin. Figure 1 Figure 3 Figure 2 Figure Rod 2 (D) (ξ Figure 2 (F) Figure 2 (H) Figure 4 (A> (75) Figure 5 Figure 6r'',''

Claims (1)

【特許請求の範囲】 １、ガラスエポキシ勢を材料とする長方形状の基板に複
数儒のパッケージベースを一体にか□つ切離可能に設け
ると共に、前記パッケージベースにはインナーリードや
アウタリード等のリードを形成し、半導体素子ペレット
の接続な可能に構成したことｔ４１像とする多連フレー
ム。 ２、パッケージベースは、よ−ス胸辺に打抜いた溝間に
形成した橋絡部にてフレーム部に支持されてなる特許請
求の範囲第１塙記載の多連フレームウイ、ベース中央に
はペレット固着雨の一部を形成してなる特許請求の範囲
第１項または第２項記載の多連フレーム。 ４、　リードはベース表面に形成したインナリードと、
ペースＪ１面に形成したアウタリードと、ベースｖｊＩ
通して前記インナリードとアウタリードとを導通させる
スルーホールとからなる特許請求の範囲第１項ないし第
３項のいすｔかに記載の多連フレーム。[Scope of Claims] 1. A rectangular substrate made of glass epoxy material is provided with a plurality of package bases integrally and separably, and the package base is provided with leads such as inner leads and outer leads. A multi-frame frame that forms a T41 image and is configured to allow connection of semiconductor element pellets. 2. The package base is supported by the frame part at the bridge part formed between the grooves punched out on the chest side of the side. The multiple frame according to claim 1 or 2, which forms a part of pellet-fixed rain. 4. The lead is an inner lead formed on the base surface,
Outer lead formed on the first side of Pace J and base vjI
The multi-frame frame according to any one of claims 1 to 3, comprising a through hole through which the inner lead and the outer lead are electrically connected.
JP57016231A 1982-02-05 1982-02-05 Multiple connection frames Pending JPS58134451A (en)

Priority Applications (14)

Application Number Priority Date Filing Date Title
JP57016231A JPS58134451A (en) 1982-02-05 1982-02-05 Multiple connection frames
FR8221110A FR2521350B1 (en) 1982-02-05 1982-12-16 SEMICONDUCTOR CHIP HOLDER
DE19833300693 DE3300693A1 (en) 1982-02-05 1983-01-11 SEMICONDUCTOR ARRANGEMENT AND METHOD FOR THEIR PRODUCTION
KR1019830000264A KR910002035B1 (en) 1982-02-05 1983-01-24 Semiconductor device and manufacture thereof
US06/462,060 US4691225A (en) 1982-02-05 1983-01-28 Semiconductor device and a method of producing the same
GB08302769A GB2115607B (en) 1982-02-05 1983-02-01 Semiconductor device and a method of producing the same
IT19413/83A IT1161868B (en) 1982-02-05 1983-02-03 SEMICONDUCTIVE DEVICE AND PROCEDURE FOR ITS MANUFACTURE
GB08411298A GB2138210B (en) 1982-02-05 1984-05-02 A multiple frame
SG37587A SG37587G (en) 1982-02-05 1987-04-23 A multiple frame
SG361/87A SG36187G (en) 1982-02-05 1987-04-23 Semiconductor device and a method of producing the same
HK708/87A HK70887A (en) 1982-02-05 1987-10-01 Semiconductor device and a method of producing the same
HK713/87A HK71387A (en) 1982-02-05 1987-10-01 A multiple frame
MY602/87A MY8700602A (en) 1982-02-05 1987-12-30 Semiconductor device and a method of producing the same
MY603/87A MY8700603A (en) 1982-02-05 1987-12-30 A multiple frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57016231A JPS58134451A (en) 1982-02-05 1982-02-05 Multiple connection frames

Publications (1)

Publication Number Publication Date
JPS58134451A true JPS58134451A (en) 1983-08-10

Family

ID=11910770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57016231A Pending JPS58134451A (en) 1982-02-05 1982-02-05 Multiple connection frames

Country Status (1)

Country Link
JP (1) JPS58134451A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05183067A (en) * 1991-06-20 1993-07-23 Iwaki Electron Corp Ltd External electrode structure of leadless package and manufacturing method thereof
KR100264644B1 (en) * 1992-09-15 2000-09-01 윤종용 Module package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05183067A (en) * 1991-06-20 1993-07-23 Iwaki Electron Corp Ltd External electrode structure of leadless package and manufacturing method thereof
KR100264644B1 (en) * 1992-09-15 2000-09-01 윤종용 Module package

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