JPS58134409A - Circuit element - Google Patents
Circuit elementInfo
- Publication number
- JPS58134409A JPS58134409A JP1670482A JP1670482A JPS58134409A JP S58134409 A JPS58134409 A JP S58134409A JP 1670482 A JP1670482 A JP 1670482A JP 1670482 A JP1670482 A JP 1670482A JP S58134409 A JPS58134409 A JP S58134409A
- Authority
- JP
- Japan
- Prior art keywords
- metallized layer
- circuit element
- ferrite chip
- shape
- ferrite
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000859 α-Fe Inorganic materials 0.000 claims abstract description 14
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 235000009508 confectionery Nutrition 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 210000000988 bone and bone Anatomy 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F2017/0066—Printed inductances with a magnetic layer
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Coils Or Transformers For Communication (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、高周波混成集積回路において、チョークコ
イル素子として用いられる回路素子の改良に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in circuit elements used as choke coil elements in high frequency hybrid integrated circuits.
従来より、高周波場−用の混成集積回路においては、信
号増幅能動素子にＩＩｔｌＬ電源な供給するためには、
それらの間に例えば第１凶に示すように、フェライトコ
ア１１に導線１２’に逃したチョークフィルすなわちフ
ェライト菓子１ｏが不可欠なものであった。この場合、
取り付ける基板１がセラミックで形成されている時はこ
のフェライト素子１００落状かられかるように、その取
り付は方法トシては、基板１に形成したメタライズ層２
に形状の不安定さからリフ２−炉などでははんだ付けで
きないので、はんだゴテではんだ３により作業せざるｔ
得ないため、作業時間上大きな間離があった。また、こ
のフェライト菓子１０の成形も数量が多くなった場合、
形状のバラツキが大きくなり、特性上や、信幀性上から
多くの間離があった。Conventionally, in hybrid integrated circuits for high frequency fields, in order to supply IItlL power to signal amplification active elements,
Between them, for example, as shown in the first example, a chalk fill, that is, a ferrite confectionery 1o, which is passed through the ferrite core 11 and the conducting wire 12' is essential. in this case,
When the substrate 1 to be attached is made of ceramic, the method for attaching the ferrite element 100 is to remove the metallized layer 2 formed on the substrate 1.
Due to the instability of the shape, soldering cannot be done in a rift 2-furnace, so it is necessary to solder 3 with a soldering iron.
As a result, there was a large gap in working hours. Moreover, when the quantity of molding of this ferrite confectionery 10 increases,
The variations in shape became large, and there were many gaps in terms of characteristics and reliability.
この発明は、以上の点にかんがみてなされたものである
。以下この発明についてａＩｊｌする。This invention has been made in view of the above points. This invention will be described below.
８８２図はこの発明の一実施例な示すもので、第３図に
第２図のＡ−Ａ’−による断函図を示す。纂２ａ！ＩＩ
、ＪＩｇ３図において、２１は矩形状のフェライトチッ
プ、このフェライトチップ２１０表面はメタライズ層２
２が施され回路素子２０ｔ−構成している。このメタラ
イズ層２２４片面でもよいが、作業上、フェライトチッ
プ２１に最表の方向性な持たさないためには全面メタラ
イズ層を設けてもよい。また、このフェライトチップ２
１の形状およびメタライズの形状と厚みは、所望する電
気骨性を得られるように設計すれはよい。FIG. 882 shows an embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along line AA'- in FIG. 2.纂2a! II
In the JIg3 diagram, 21 is a rectangular ferrite chip, and the surface of this ferrite chip 210 is covered with the metallized layer 2.
2 is applied to constitute the circuit element 20t. This metallized layer 224 may be provided on one side, but in order to prevent the ferrite chip 21 from having directionality on the outermost surface, a metalized layer may be provided on the entire surface. Also, this ferrite chip 2
1 and the shape and thickness of the metallization may be designed so as to obtain the desired electrical bone properties.
以上説明したように、この発明は矩形状のフェライトチ
ップの表面にメタライズ層ン施して−路素子ヶ構成した
ので、チョークコイル素子用部品の供給が安定化し、取
り付は作業の合理化が計すれ、大幅なコストダウンが実
現できる利点がある。As explained above, in this invention, a metallized layer is applied to the surface of a rectangular ferrite chip to form a circuit element, which stabilizes the supply of parts for choke coil elements and streamlines the installation process. , which has the advantage of significantly reducing costs.
第１図は従来リフエライト素子での取付は状態を示す斜
視図、第２図はこの発明の一実施ｇ４Ｙ示イ斜視図、第
３図を工＃！２図のＡ−Ａ’線による断面図である。
図中、１は基板、２＆！メタライズ層、３ははんだ、２
０１工回路素子、２１はフェライトチップ、２２はメタ
ライズ層である。なお、図中の同一符号は同一または相
当部分を示す。
代理人 為野信−（外１名）
□□１′：１．。
第１図
第２図
°□、第３図
１１゜Fig. 1 is a perspective view showing how a conventional refurite element is installed, Fig. 2 is a perspective view showing an embodiment of the present invention g4Y, and Fig. 3 is a perspective view showing how it is installed. FIG. 3 is a sectional view taken along line AA' in FIG. 2; In the figure, 1 is the board, 2&! Metallized layer, 3 is solder, 2
01 is a circuit element, 21 is a ferrite chip, and 22 is a metallized layer. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Shin Tameno (1 other person) □□1': 1. . Figure 1 Figure 2°□, Figure 3 11°
Claims (1)
したことｔｔ＃黴とする＠踏素子。@Tread element with a metallized layer applied to the surface of a rectangular ferrite chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1670482A JPS58134409A (en) | 1982-02-03 | 1982-02-03 | Circuit element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1670482A JPS58134409A (en) | 1982-02-03 | 1982-02-03 | Circuit element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58134409A true JPS58134409A (en) | 1983-08-10 |
Family
ID=11923661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1670482A Pending JPS58134409A (en) | 1982-02-03 | 1982-02-03 | Circuit element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58134409A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0690460A1 (en) * | 1994-06-30 | 1996-01-03 | Plessey Semiconductors Limited | Multi-chip module inductor structures |
-
1982
- 1982-02-03 JP JP1670482A patent/JPS58134409A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0690460A1 (en) * | 1994-06-30 | 1996-01-03 | Plessey Semiconductors Limited | Multi-chip module inductor structures |
| US5747870A (en) * | 1994-06-30 | 1998-05-05 | Plessey Semiconductors Limited | Multi-chip module inductor structure |
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