JPS58130561A - Active matrix substrate - Google Patents

Active matrix substrate

Info

Publication number
JPS58130561A
JPS58130561A JP1272582A JP1272582A JPS58130561A JP S58130561 A JPS58130561 A JP S58130561A JP 1272582 A JP1272582 A JP 1272582A JP 1272582 A JP1272582 A JP 1272582A JP S58130561 A JPS58130561 A JP S58130561A
Authority
JP
Japan
Prior art keywords
film
sio2
polycrystalline silicon
substrate
polycrystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1272582A
Other languages
Japanese (ja)
Inventor
Yasuo Katsuyama
勝山 恭雄
Toshiyuki Misawa
三沢 利之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP1272582A priority Critical patent/JPS58130561A/en
Publication of JPS58130561A publication Critical patent/JPS58130561A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00Materials and properties
    • G02F2202/10Materials and properties semiconductor
    • G02F2202/104Materials and properties semiconductor poly-Si

Abstract

PURPOSE:To obtain the substrate which can keep a charge of one digit or more, by using a transparent substrate for the substrate when the active matrix substrate for driving a liquid crystal display body is formed, coating most part of the surface by the laminated film of an SiO2 film and a conductive transparent film, and providing an element comprising polycrystal Si on the other part. CONSTITUTION:On the transparent substrate 401 made of quartz glass and the like, the SiO2 film 402 and an ITO film 403 which is the conductive transparent film are laminated and formed. A specified pattern is formed by photoetching. Then the entire surface is coated by an SiO2 film 404. Then an island shaped polycrystal film 405 is formed on the part of the film 404 where the films 403 and 402 are not present. Then heat treatment is performed, and only the exposed part is transformed into an SiO2 film 406, which is to become a gate oxide film. A polycrystal Si film 407, which is to become a mask, is provided on the film 406. Impurity introduced regions 408 and 409 are formed in the island shaped polycrystal Si film 405 by ion implantation and the like. Thereafter, an SiO2 interlayer insulating film 410 is deposited on the entire surface, an opening 411 is provided, and Al wiring metals 412 are attached to the regions 408 and 409, respectively.

Description

【発明の詳細な説明】 本発明は、薄膜素子により形成された、液晶表示体駆動
用アクティブマトリクス基枡に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an active matrix substrate for driving a liquid crystal display formed of thin film elements.

最近、m儂表示を目的とした液晶表示体駆動用アクティ
ブマ) IIクス基飯め開発が各所で行なわれている・
特に、透明基管(石英ガラス等)上に薄膜トランジスタ
(以下、〒IFTと略記)を形成してこれをスイッチン
グトランジスタとして用いる方式のものが注目されてい
る・アク子イブマトリクス方式による画**示の一画素
に相当する基本構成単位を第1図に示す・同図に於いて
101゜1011はそれぞれ、1行目、1+1行目のX
儒配線(ゲート配線)1−1102Uj列目のY儒配線
(データ線)を示す・また・103は1行j列のスイッ
チング用TFTを、104はアク子イブマトリ々ス基板
内に作り込まれた電荷保ハ用キャパシタを、105は液
晶費示体に相等するキャパシタを示す・同図に示すアク
ティブマド11タス基板は、従来、/第2図の(a)〜
(e)に示すごとき工程で製造されており、最終的に同
ν1(e)のような構造となっていた。
Recently, the development of active materials for driving liquid crystal displays for the purpose of displaying images is being carried out in various places.
In particular, a method in which a thin film transistor (hereinafter abbreviated as IFT) is formed on a transparent base tube (such as quartz glass) and used as a switching transistor is attracting attention. The basic structural unit corresponding to one pixel is shown in Figure 1. In the figure, 101° and 1011 are
Confucian wiring (gate wiring) 1-1102 Uj column Y Y-confucian wiring (data line) is shown. Also, 103 is the switching TFT in the 1st row and j column, and 104 is built in the Akuko Eve matrix substrate. A charge holding capacitor is shown, and 105 is a capacitor equivalent to a liquid crystal display.
It was manufactured by the process shown in (e), and the final structure was as shown in v1(e).

まず、透明チー(石英ガラス等)2o1上にOVD法で
rio、膜202’l堆積し、更にavD法で多結晶シ
リコン膜を形成し、ホトエッチによりパターニングを行
って多結晶シIIコンの島203f形成する・(第2し
+(a))紳配多結晶シリコンの表面を酸化してゲート
酸化Ia204をヤ成[7、更に、第2の多結晶シリ:
+y$205をcvD波で形成する・(第2図(b))
 @1第2の多結晶シロコン膜をホトエッチによりパタ
ーニングした後、イオン打込み又は熱拡散によって不純
物ドープを行う◎205及び206の部分に不純物がド
ープされるC第21i21(c))層間絶縁Jig (
B i Os等)207をC’VD法により堆積させた
後、ホトエッチによりコンタクトホール20Bを形成す
る・更に、配線金属層209(アルミ尋)をスパッタ又
は蒸着によりν放し、ホトエッチによるパターニングを
行う・C第2図(d))液晶駆動電極膜である導電性透
明膜(し下工TO膜と配す> 210f形成し、ホトエ
ッチによるパターニングを行う・以上でアタテイプマト
I+タス基蓼が完全する。(第2図(a)) IIIE
 2図(・)に於いて211の部分にスイッチング用丁
1テ(第1図の105)を形成してお抄%2120部分
に電荷保持用キャパシタc第1図の104)管形成して
いる・ このように従来構造にょ〉形成された電荷保持用キャパ
シタは、ゲー)IEI!(第1 &+ 1o 1゜10
1’ )とデータ線(第1図102)との間の璽1−々
を防ぐと共に耐圧を確保する為層間絶鋒膜C第2図20
7)の膜厚は1μm程度と厚くしな(てはならない・更
に、液晶ディスプレイを透過形とするために、光を通し
に(い多結晶シ11コンC第2k1205 )が占める
面積はできるだけ小さくしなくてはならない・従ってキ
ャパシタ面積は小さくなる・以上の理由からその容量値
をある程度以上太きくする仁とはできない・C−画素2
5000μ雪1の場合、最大α2PF程度)現在・比較
的簡単で安価な工程により得られるテνテのオフ電流と
液晶の1−り電流との静和の下限値が100Pム〜50
0Pムであること1考慮すると充分な表示性能を有する
画儂ディスプレイを得る為には前記電荷保持用キャパシ
タC第1図104)の容量値を現状の10倍程度C−曲
1素25000μtx”  の場合、2FF程度)とす
る必要がある・′iE発IvIはかかる欠点を除去[、
たもので、その目が・け、77丁及び薄膜キャパシタの
製造工程を工夫することにより上述の要求を満たし、良
好な表示性訃を布中る液晶表示体用アクティブマトリク
ス基枦の構造を提案することにある。
First, a rio film 202'l is deposited on a transparent silicone (silica glass, etc.) 2o1 by an OVD method, a polycrystalline silicon film is further formed by an avD method, and patterned by photoetching to form an island 203f of polycrystalline silicon. Forming (Second Process + (a)) Oxidize the surface of the polycrystalline silicon to form gate oxide Ia204 [7, Further, the second polycrystalline silicon:
+y$205 is formed by cvD wave (Figure 2 (b))
@1 After patterning the second polycrystalline silicon film by photoetching, impurity doping is performed by ion implantation or thermal diffusion. ◎ 205 and 206 portions are doped with impurities.
After depositing B i Os, etc.) 207 by the C'VD method, a contact hole 20B is formed by photoetching.Furthermore, the wiring metal layer 209 (aluminum thickness) is released by sputtering or vapor deposition, and patterning is performed by photoetching. C Figure 2 (d)) A conductive transparent film (prepared with TO film), which is a liquid crystal drive electrode film, is formed and patterned by photoetching. With the above steps, the attaipomat I+Task base is completed. ( Figure 2 (a)) IIIE
In Figure 2 (), a switching pipe (105 in Figure 1) is formed at the 211 part, and a charge holding capacitor (104 in Figure 1) is formed at the 2120 part.・The charge retention capacitor formed in the conventional structure as described above is similar to the IEI! (1st &+ 1o 1゜10
1') and the data line (Fig. 1, 102) and to ensure voltage resistance, an interlayer insulation film C is provided (Fig. 2, 20).
The film thickness of 7) must be as thick as about 1 μm.Furthermore, in order to make the liquid crystal display a transmissive type, the area occupied by the polycrystalline silicon (C2K1205) through which light passes is as small as possible.・Therefore, the capacitor area becomes smaller. ・For the above reasons, it is not possible to increase the capacitance value beyond a certain level. ・C-Pixel 2
In the case of 5000μ snow 1, the maximum α2PF is present) The lower limit of the static sum of the off-current of the TE and the 1-current of the liquid crystal obtained by a relatively simple and inexpensive process is 100P~50
Considering that the current value is 0Pm, in order to obtain a picture image display with sufficient display performance, the capacitance value of the charge holding capacitor C (Fig. 1, 104) should be approximately 10 times the current value. In this case, it is necessary to set it to about 2FF).IvI from iE eliminates this drawback [,
With this in mind, we proposed a structure for an active matrix base for liquid crystal displays that satisfies the above requirements and achieves good display performance by devising the manufacturing process of 77 devices and thin film capacitors. It's about doing.

本発明の実#例に於ける画素表示の一画素に相当する基
本構造単位を従来−1と同様に第5Fに示す・同図に於
ける図番は第1図の101〜105と第3図の501〜
505が対応するものである。
The basic structural unit corresponding to one pixel in the pixel display in the actual example of the present invention is shown in Fig. 5F as in Conventional-1. The drawing numbers in this figure are 101 to 105 and 3 in Fig. 1. 501~ in the diagram
505 corresponds to this.

第!STI?!に示す本実施例は、以下に示す製造工程
によって実現される。
No.! STI? ! The present embodiment shown in is realized by the manufacturing process shown below.

誠4図の(給〜(f)に斤す製造工程に於いて、管ず、
透88基枦(行革ガラス岬)401上にOVD法で81
03膜402%−堆積し、次にITO膜40sをスパッ
タ尋で形成し、ホトエッチによりパターニングする。次
にOVD法で絶縁膜404 (Bias勢)を堆積する
・(第4図(a))次に0VT)法で多結晶シ11コン
膜を形成し、ホトエッチによりパターニングを行って多
結晶シ11コンの島405を形成する・C第4図(b)
)同断面図の上方からの外観図は第5図のようにパター
ニングされている・同図の501は透−基管を・503
は工To膜會・505は多結晶シリコンの島を示してい
る。炉記エテO膜はキャパシタとする為の一方の電極と
なる部分と、該各部分を互いに結合する部分によって構
成されている会前配多結晶シリコンの表面を酸化してゲ
ート酸化膜406をY成し、岬に第2の多結晶シ璽シコ
ン膜を4071OVD法で形成する。(第4図(C))
前記第2の多結蟲シ11コン膜tホトエッチによシバタ
ーニングしたに、イオン打込み又は熱拡散によって、不
純物をドープする。
In the manufacturing process shown in Fig. 4 (supply ~ (f)), pipes,
81 by OVD method on 401 Toru 88 base (Gyokuhaku Glass Cape)
402% of the ITO film is deposited, and then an ITO film 40s is formed by sputtering and patterned by photoetching. Next, an insulating film 404 (Bias type) is deposited using the OVD method (FIG. 4(a)). Next, a polycrystalline silicon film 404 is formed using the 0VT method, and patterned by photoetching. Forming the island of Conn 405・C Figure 4(b)
) The external view from above of the same cross-sectional view is patterned as shown in Figure 5. 501 in the same figure is the transparent base tube. 503
505 indicates an island of polycrystalline silicon. The gate oxide film 406 is made by oxidizing the surface of the polycrystalline silicon, which is made up of a part that becomes one electrode for a capacitor and a part that connects these parts to each other. Then, a second polycrystalline silicon film is formed on the cape using the 4071 OVD method. (Figure 4 (C))
After the second multi-crystalline silicon film 11 is patterned by photo-etching, impurities are doped by ion implantation or thermal diffusion.

408及び4090部分に不純物がドープされる・C第
4図(d))次に全面に層間絶縁13(810a勢)4
10IOVI)法により堆積した後、ホトエッチにヨシ
、コンタクトホール411を形成する・更に、配線金属
412Cアルミ等)fスパッタ又は蒸着によりffff
し、ホトエッチによるパターニングを行なう。C第4図
(e))更に液晶#動電棲である第2のITO膜413
をスパッタ等で彫成し、ホトエラ+によるパターニング
を行なう・pl土で書見−の構造を有するアクティブマ
トリ々スチーが児故する・(第4夕i(?))第4図に
於ける薄膜キャパシタは、第1に形成した工τ0膜(4
0S 1と1E2Kff成LIITOII(41S )
の間に形成される・該第1のITO膜は、第5図に示す
ように各々の部分が全面に結合されておシ、Ie工TO
MIFの1箇所以上をデータ線の信号のグランドレベル
に接続する・従来の電荷保持用キャパパ/りに、ゲート
#線と層間lp縁膜と液晶駆か電極間で4赦されている
のに比べて、本実施−!を適用することにより、面積比
が二十倍1!縦となる為に、従来に比較して二十倍鯵上
の容1%を有する電荷保持用キャパシタを作り込むこと
が可能となる会しかも、製造にIt−する工程は、エテ
O@(Dffl成とホト工程が増風したにすき゛ずTに
コストは15〜20嗟程度の上昇に押えられる。
408 and 4090 portions are doped with impurities.C Figure 4(d)) Next, interlayer insulation 13 (810a group) 4 is applied to the entire surface.
After depositing by 10IOVI) method, photoetch to form a contact hole 411.Furthermore, wiring metal 412C aluminum, etc.) fffff by sputtering or vapor deposition.
Then, patterning is performed by photoetching. C Fig. 4(e)) Furthermore, a second ITO film 413 which is a liquid crystal #electrodynamic
is engraved with sputtering etc. and patterned with Photoera+. ・Active matrices with a shoken structure are produced using PL soil. ・(4th evening (?)) Thin film in Figure 4 The capacitor is made of the first formed τ0 film (4
0S 1 and 1E2Kff formation LIITOII (41S)
As shown in FIG. 5, the first ITO film formed between
Connect one or more points of the MIF to the ground level of the data line signal.Compared to the conventional charge retention capacitor, which has 4 connections between the gate # line, the interlayer LP film, and the liquid crystal drive electrode. The actual implementation! By applying this, the area ratio is 20 times 1! Because it is vertical, it is possible to fabricate a charge retention capacitor with a capacity of 1%, which is 20 times larger than conventional ones. Despite the increase in wind speed in the production and photo processes, the cost increase will be limited to about 15 to 20 million yen.

以上述べたごと(本発明によれば、わずかな工1iIW
I並びにコストの増加だけで、−桁以上保持特性の優れ
たアタテイブマトII々スチーを得ることができる・し
か屯、意見1jIKよシ得られたア々テイブマトリタス
基Wt用いることにより、丁νテのIν−り電流の低下
及びON / OF Ir f rPfl上させるため
の複雑でコストアップにつながる工程を加えることなく
高性能で安価な液晶表示ディスプレイを作ることができ
る・
As stated above (according to the present invention, only a small amount of work is required)
However, by using the obtained attentive matrices Wt, it is possible to obtain attenuated matrices with superior retention properties of - orders of magnitude or more with only an increase in I and cost. - A high-performance, low-cost liquid crystal display can be made without adding complicated and cost-increasing processes to reduce the current and increase the ON/OF Irf rPfl.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、アクティブマ) 11クス基@を用いた液晶
憫示ディスプレイを構成する基本単位を説明するための
図・ 第2図の(a)〜(・)は従来のアクティブマトリクス
基II#&造工程を説明する為の図・ 第S図は本発明によるアタテイブマト11タス基橡を用
いた液晶表示ディスプレイを構成する基本単位を説明す
る為の図・ 第4図の(!L)〜(6は本発明によるア々テイプマト
リクス基板製造工程を胛明する為の翻・か5図は第4図
の(b)の工程に於けるパターンの外−;図である・ 以上 出願人 株式会社 軸訪精工舎 第3図 14−
Fig. 1 is a diagram for explaining the basic unit constituting a liquid crystal display using active matrix II#.・Figure S is a diagram to explain the basic unit that constitutes a liquid crystal display using the attenuating matrix according to the present invention. ・(!L) to ( in Figure 4) 6 is a translation for explaining the at-tape matrix board manufacturing process according to the present invention. Figure 5 is a diagram outside the pattern in the process of Figure 4 (b). Applicant Co., Ltd. Jiku Seikosha Figure 3 14-

Claims (1)

【特許請求の範囲】[Claims] 第1の多結晶シリコン層にソース、ドレイン及びキャン
ネルをν或し、該第1の多結晶シ11コン上に酸1ヒ膜
を形放し、し酸什−上に第2の多綻晶シリコン層をゲー
トとしてν成した薄膜トランジスタから成るアタテイブ
マトII々ス基板の構造に於いて、該第1の多結晶シ1
1コン層を形成針に、導電性透明膜から成る第1の電極
及び絶縁膜を形成し、該第2の多結晶シリコン層をν成
彼、層間I?!Ill?形成しコンタクトホールをあけ
、該第1の多結晶21197層のドレイン電極と結合す
る導電性透明膜から成る第2の電極?形成し、該第1の
電極、該絶縁膜該層間P縁膜及び第2の電極により電り
:保持用キャパシタを形成したことを特徴とするアクテ
ィブマド11クス基枡。
A source, a drain, and a channel are formed on the first polycrystalline silicon layer, an arsenic acid film is formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer is formed on the silica layer. In the structure of an attenuating matrix II substrate consisting of a thin film transistor formed using a layer as a gate, the first polycrystalline silicon
A first electrode made of a conductive transparent film and an insulating film are formed using the first layer as a formation needle, and the second polycrystalline silicon layer is formed with an interlayer I? ! Ill? a second electrode consisting of a conductive transparent film formed with a contact hole and coupled to the drain electrode of the first polycrystalline 21197 layer; 1. An active metal 11x base plate, characterized in that the first electrode, the insulating film, the interlayer P film, and the second electrode form a power holding capacitor.
JP1272582A 1982-01-29 1982-01-29 Active matrix substrate Pending JPS58130561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1272582A JPS58130561A (en) 1982-01-29 1982-01-29 Active matrix substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1272582A JPS58130561A (en) 1982-01-29 1982-01-29 Active matrix substrate

Publications (1)

Publication Number Publication Date
JPS58130561A true JPS58130561A (en) 1983-08-04

Family

ID=11813402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1272582A Pending JPS58130561A (en) 1982-01-29 1982-01-29 Active matrix substrate

Country Status (1)

Country Link
JP (1) JPS58130561A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5162901A (en) * 1989-05-26 1992-11-10 Sharp Kabushiki Kaisha Active-matrix display device with added capacitance electrode wire and secondary wire connected thereto

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5162901A (en) * 1989-05-26 1992-11-10 Sharp Kabushiki Kaisha Active-matrix display device with added capacitance electrode wire and secondary wire connected thereto

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