JPS5813044B2 - oscillation circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to an oscillation circuit.

Conventionally, various types of oscillation circuits have been proposed and put into practical use.

The present invention proposes an oscillation circuit that can comprehensively eliminate the various drawbacks of these conventional oscillation circuits and has a novel circuit configuration.

Specifically, the above-mentioned disadvantages are (1) expensive despite not having high accuracy, (2) relatively large number of elements used in the circuit, and (3) the circuit is large-scale. (4) It is not easy to start or stop oscillation; (5)
) There is a low degree of guarantee that oscillation will occur reliably;
(6) There is a low degree of guarantee that oscillation will stop reliably, (7) When obtaining a rectangular wave oscillation output, the duty cannot be easily changed, (8) The direction of oscillation start, i.e. This method has various disadvantages, such as the fact that it cannot be reliably determined whether oscillation is to be started at the rising edge or the falling edge of the waveform.

Therefore, an object of the present invention is to propose an oscillation circuit with a novel configuration that can eliminate the above-mentioned drawbacks.

In accordance with the above object, the present invention includes first and second OCR circuits that perform charging and discharging with a predetermined time constant, first and second switching elements that cause the first and second OCR circuits to discharge, respectively, and non-inverting switching elements. a flip-flop circuit that turns on the first and second switching elements with an output and an inverted output; a flip-flop circuit that generates first and second reference voltages; 1 and 2nd terminal voltage is “H”
The first and second reference voltages, respectively, are switched to the "L+ side" or "Hl side depending on whether they are on the "L+ side" or "L+ side, respectively.
and a first and second comparator for comparing the magnitude with the terminal voltage of the first comparator, the comparison output of the first comparator is used as the set input of the flip-flop circuit, and the comparison output of the second comparator is used as the set input of the flip-flop circuit. In the oscillation circuit, the flip-flop circuit includes a two-man powered first OR circuit in which the first human power and the second human power are each equipped with an inverter at the front stage, and the same configuration as the first OR circuit. and the set input is applied to the input of the inverter in the first human power of the first OR circuit, and the set input is applied to the input of the inverter in the first human power of the second OR circuit. is applied with the reset input, and the output of one of the OR circuits is connected to the input of the inverter provided in the second input of the other OR circuit in a cross-crossing manner, and The first and second switching elements are both brought into the "open" state by the oscillation start command signal,
Furthermore, the discharge time constant determined by the first CR circuit and the first switching element is different from the discharge time constant determined by the second CR circuit and the second switching element.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an oscillation circuit according to the present invention.

Further, FIG. 2 is a waveform diagram showing waveforms of important parts in FIG. 1.

In the flip-flop circuit 12 of FIG. 1, as shown in detail in the dotted line block 34 of FIG. 3, which will be described later, the first human power and the second human power are connected to an inverter (each OR in block 34 in FIG. 3) at the front stage, respectively. A two-man powered first OR circuit (represented by the triangle marks attached to each input in FIG. 3), and a second OR circuit (represented by a third A set input from a first comparator 14-1, which will be described later, is applied to the input of the inverter in the first human power of the first OR circuit. A reset input from a second comparator 14-2, which will be described later, is applied to the input of the inverter in the first input of the two-OR circuit, and the output of one of the OR circuits is applied to the input of the inverter in the first input of the two-OR circuit. They are connected to the inputs of the inverters provided in the two-man power system, respectively, in a cross-section manner.

The truth table of the RS type flip-flop circuit 12 is as shown in the table below when shown in accordance with the operation order (1) to (2) to be described later.

In the above table, S corresponds to the set input, R corresponds to the reset input, Q corresponds to the non-inverted output, and σ corresponds to the inverted output trap. This is a flip-flop that operates to output the +H9 level or the "L" level shown in Q and Q in the above table depending on the "H+ level" or "L" level.

First, during non-operation, the oscillation start command signal Vc is at "L+ level" at time t.

When an oscillation start command is issued at , the level becomes "H" (see Fig. 2A).

Therefore, the first and second AND circuits i+-i, 11-
2 are both open, and send the non-inverted output Q and the inverted output Q from the RS type flip-flop circuit 12 to the first and second transistors 13-1 and 13-2 at the next stage.

In this case, in the initial state of the IC, both the first capacitor C1 and the second capacitor C2 are in a charging state, and therefore the set input and reset input from the first and second comparators 14-1 and 14-2 are both in the charging state. Since it is at the L'' level, the Q and Q outputs of the flip-flop circuit 12 are both at the 'H'' level in the initial state (see ◯ in the above table).

Therefore, the first and second transistors 13-1, 13-
2 are both turned on.

In the above charging state, the first capacitor C1 and the second capacitor C1
A power supply voltage +■ is applied to the capacitor C2 through the first resistor R and the second resistor R2, respectively, and the charging voltages Vc1 and vc2 are applied (period T in Figure 2, Figure 2).

reference). These charging voltages Vc and Vc2 are applied to the first and second transistors 13-i and 13 which are now turned on.
-2 (see reset periods Tll and T12 in Figure 2).

The terminal voltages of the first and second capacitors are respectively the first and second capacitors.
comparator 14-1 and second comparator 14
-2, the first reference voltage Vref1 and the second
A comparison is made between the reference voltage Vref2 and the reference voltage Vref2.

Here, the first and second comparators 14-1, 14
-2 includes a differential transistor pair as described later, and the first and second reference voltages Vref]tVr
ef2 takes a value on either the "H" side or the "L side" depending on the magnitude relationship with the terminal voltages vc, vc2 of the first and second capacitors C1, C2.

That is, referring to the beginning of FIG. 2, when the terminal voltage Vc of the first capacitor C falls due to discharge during the reset period TLI, the first reference voltage is low since Vref1<Vc. Take the level Vref,·L.

This Vref1・L is shown by a dotted line in the figure, and Vc
When l crosses Vref1.L at time t1, the first comparator 14-1 sends an Hn output to the flip-flop circuit 120 set input.

Therefore, the Q output of the flip-flop circuit 12 is at time t1.
Switches from ゛H'' to ゜L'' (see 2 in Fig. 2 and ◯ in the above table).

As a result, only the first AND circuit 11-1 sends an L+ level output to the first transistor 13-1, which is turned off.

As a result, discharging of the first capacitor C1 is stopped and charging is started (see period T2 at the beginning of FIG. 2).

At this time, Vref1·L comes to a level lower than Vc1, so the first reference voltage Vref1 is set to the higher Vref1.
・Reverse to H (see the dashed line at the opening in Figure 2).

On the other hand, regarding the second capacitor C2, since the Q output of the flip-flop circuit 12 is still at the "H+ level" (see E in Figure 2 and ■ in the above table), the Q output of the flip-flop circuit 12 is , second transistor 13-2
remains on, and the reset period T1 shown in FIG.
Continues to discharge during 2.

When Vc2 crosses the second reference voltage Vref2, the flip-flop circuit 12 is reset from the second comparator 14-2.
” level (see ■ in the table above).

Note that when both the set input and reset input are at the IH+ level, the Q and point outputs of the flip-flop circuit 12 both maintain their previous levels (see
and ■).

Looking again at the first capacitor C1, during period T21 at the beginning of Figure 2, the level of VCI increases due to charging, and now the first reference voltage Vref]·H has reached the 'H' level side due to inversion. and the same level at time t2, and when this level is slightly exceeded, the first comparator 14-1 sends an "L" output to the set input of the flip-flop circuit 120, and its Q output and Q output become "H" and "H", respectively.゜L'' (see Figure 2 2 and E and ■ in the table above).

The time t mentioned above. By the operation from to t2, the system including C1, R1 (upper side) and C2, R2 in FIG.
The system is set so that oscillation starts from the upper system having the smaller discharge time constant CR among the systems (lower side) including the above, and normal oscillation starts after time t2.

After this time t2 has elapsed, the charging voltage Vc is changed to the reference voltage Vr.
ef1.L is crossed, and the output (set input) of the first comparator 14-1 switches from the "L" level to the "H+" level (see ■ in the above table).

As already mentioned, the Q output of the flip-flop circuit 12 is
Since it has now become L+ (see ■ and ■ in the table above), the second transistor 13-2 is turned off, the discharge state of the second capacitor C2 is released, and charging begins to occur (the second
(See period T32 in Figure C).

This charging voltage Vc2 meets the second reference voltage Vref2·H, which has already reached the "Hl side," at time t3, and when it slightly exceeds this, the second comparator 14-2
sends a "L?" output to the reset input of the flip-flop circuit 12, and as a result, the Q output and Q output of the flip-flop circuit 12 become lL' and 'H', respectively (see ■ in the table above), and as shown in FIG. A first oscillation rectangular wave is obtained from OUT.3 The pulse width W1 of this rectangular wave is defined by the time constant of the second capacitor C2 and the second resistor R2.

After this time t3 elapses, the charging voltage Vc2 changes to the reference voltage Vr.
ef2.L is crossed, and the output (reset input) of the second comparator 14-2 switches from "L+ level" to "Hn level" (see ■ in the above table).

At the time t3, the Q output is “L” and the Q output is “HT”.
(■ in the table above), so the first AND circuit 1
1-1, the first transistor is turned off, and the first
The capacitor starts charging again, and at time t4, V
c1 meets Vref1·H.

Then, the first comparator 14-1 sends out an output (set input) at the Lt level, and the flip-flop circuit 12
The Q output and sub-output of are set to "H" and "L+", respectively (see ■ in the above table), and one period of oscillation is completed.

The same operation is then repeated until the oscillation continues.

Note that during the period T4 shown in FIG.
is defined by the time constant of the resistor R1.

In the above description, the features of the present invention are as follows.

What should be noted here is that although the configuration of the present invention has two identical series consisting of AND circuits, transistors, capacitors, resistors, and comparators arranged in parallel,
An oscillation output can be obtained with either series alone.3 However, in this case, taking the upper series in Figure 1 as an example, when the discharged Vc1 matches Vref]・L, the oscillation rectangular wave Get the rising (or falling) and charge V
The configuration must be such that the fall (or rise) of the oscillating rectangular wave is obtained when the voltage Vref1.c, matches Vref1·H.

However, the time it takes for discharged Vc1 to match Vref1·L, that is, the reset period, is defined by the time constant of the first capacitor C1 and the internal resistance of the first transistor 13-1, so the reset period This is accompanied by the inconvenience of time fluctuations.

This is because the internal resistance varies depending on various conditions, such as temperature.

Of course, the first transistor 13-1 may be replaced with a relay contact circuit, but this is uneconomical and impractical.

As a result, a highly accurate oscillation output cannot be obtained with the single series configuration described above.

Therefore, the present invention focuses on the fact that the time constant defined by the first capacitor C1 and the first resistor R1 is quite accurate compared to the reset period, and the oscillation rectangular wave during one cycle is The pulse width W and the pause period P1 are defined by a highly accurate C1R time constant and a highly accurate C2R2 time constant, so that the unstable reset period has no involvement in the formation of the oscillating rectangular wave.

This is clear from the fact that the end of discharge of Vc and Vc2 is not related to any other waveform changes in FIG. 2.

Here, the drawback of the above-mentioned item 1 mentioned at the beginning is eliminated.

Further, to start or stop oscillation, it is sufficient to simply open and close the first and second AND circuits 11-1 and 11-2 using the oscillation start command signal Vc (the disadvantage of item 4 above is eliminated).

Also, charging and discharging of the CR circuit is performed by the flip-flop circuit 12.
Since the oscillations are divided and carried out independently, the disadvantages mentioned in the fifth and sixth paragraphs above, such as the inability to start oscillation or the inability to stop oscillation, can be eliminated.

Furthermore, the duty of the oscillating rectangular wave can be easily varied by simply selecting C1R1 and C2R2 appropriately.
Term shortcomings are eliminated.

Furthermore, as shown in Figure 2, C1 and C
By adding a difference to 2, the directionality of the oscillating rectangular wave is determined. For example, if you set it as C, <C2, the output OUT (first
In Fig. 1), the rise of a rectangular wave is first obtained.

This eliminates the disadvantage of item 8 above.

FIG. 3 is a circuit diagram showing the configuration of FIG. 1 in further detail. In this figure, 31-1 and 31-2 are the first
and a second switching element, 11- in FIG.
1, 13-1 and 11-2, 13-2, respectively.

32-1 and 32-2 are the first and 20th CR circuits, which correspond to C, R, and C2R2 in FIG.

33-1 and 33-2 are first and second comparators, which correspond to the circuits including 14-1 and 14-2 in FIG. 1, respectively.

34 is a flip-flop circuit formed by crossing two OR circuits OR (the triangular marks attached to each input of each OR circuit in the figure each represent an inverter for logic inversion), as described above; This corresponds to 12 in FIG.

Here, the switching elements 31-1 and 31-2, the comparators 33-1 and 33-2, and the flip-flop circuit 34 have already been realized with commercially available small chips, and the separately required elements are the CR circuits 32-1 and 32-2. There are only 2.

Here, the drawbacks of the second and third terms above are eliminated. Already in the description of FIGS. 1 and 2, the comparator 14
-1, 14-2 reference voltages are Vref1/L, Vref2 indicated by dotted lines in relation to Vc17Vc2.
/L or Vref1-H, Vref indicated by a dashed line
As described above, it takes two values of 2/H, but this operation is automatically performed by the comparators 33-1 and 33-2 in FIG. 3, and is what can be called hysteresis of the reference voltage. If this hysteresis is missing, normal oscillation will not occur.

Comparator 33-1 (comparator 33-2 in Fig. 3)
(also the same), the terminal voltage V of the first capacitor C,
c, appears at the base of transistor TR1, and the first reference voltage Vref1 appears at the connection point Q between resistors r1 and r2.

Now, assuming that there is a relationship of Vc1>Vref1, the base current of the transistor TR2 is higher than that of the transistor TR1, and the transistor TR2 becomes saturated or close to it.

Then, the transistor TR3 is turned on, and the potential at the Q point decreases.

As a result, Vref1 takes the lower value Vref1·L.

The relationship of Vc1>Vref1/L is Vc1-Vref1/
When Vc becomes slightly less than Vref1.L after passing through L, the base current of the transistor TR becomes a bit higher than that of the transistor TR2, and the transistor TR2 enters a cut-off state or a state close to it.

Therefore, the transistor TR3 is turned off, the potential at the Q point increases, and VrefH takes on the higher value Vref1·H.

As explained above, according to the present invention, the first
An oscillation circuit is realized which comprehensively eliminates the various drawbacks from 8 to 8.

Note that if the terminal voltage of the capacitor C1 or C2 is used as the output OUT, a triangular wave oscillation output can also be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an oscillation circuit based on the present invention, FIG. 2 is a waveform diagram showing the waveforms of the main parts in FIG. 1, and FIG. 3 is a concrete example of the blocks in FIG. 1. It is a circuit diagram. In the figure, 31-1, 31-2 are the first and second switching elements, and 32-1, 32-2 are the first and second switching elements.
, 33-1 and 33-2 are first and second comparators, and 34 is a flip-flop circuit.

Claims (1)

[Claims] 1. First and second CR circuits that perform charging and discharging with a predetermined time constant; first and second switching elements that cause the first and second CR circuits to discharge, respectively. and; each with a non-inverted output and an inverted output.
and a flip-flop circuit that turns on a second switching element; generates first and second reference voltages by itself, and sets the first and second terminal voltages of the first and second CR circuits to H” side or j
Depending on whether it is on the L1 side, the “L+ side” or “H”
first and second comparators that compare magnitudes with the first and second terminal voltages, respectively, using the first and second reference voltages that switch to the + side; In the oscillator circuit, the comparison output of a comparator is used as a set input of the flip-flop circuit, and the comparison output of the second comparator is used as a reset input of the flip-flop circuit, wherein the flip-flop circuit has a first input and a second input. The first two-man powered system, each equipped with an inverter in the front stage.
an OR circuit, and a second OR circuit having the same configuration as the first OR circuit, and the set input is applied to the input of the inverter in the first human power of the first OR circuit, and the second OR circuit is The reset input is applied to the input of the inverter in the first power of the circuit, and the output of one of the OR circuits is connected to the input of the inverter provided in the second power of the other OR circuit, respectively. The first and second switching elements are both brought into the 'open' state by the oscillation start command signal, and further, the discharge time determined by the first OCR circuit and the first switching element is connected in a cliff-like manner. the constant is the second C
An oscillation circuit characterized in that the discharge time constant is different from that determined by the R circuit and the second switching element.