SU771729A1 - Analogue storage - Google Patents

Description

one

 The invention relates to the analog technique and can be used in control systems of moving objects and devices for storing the instantaneous value of the voltage of a continuous analog signal for unlimited storage time 5.

A device is known for storing the instantaneous value of a continuous signal flj, the storage element of which is designed as a generator of periodic oscillations on a transistor, covered by an alternating current by a negative feedback circuit through a sequence tS but connected resistor and diode, the generator output is connected to the input through a transformer the amplifier and the alternating current input is shunted by a semiconductor diode; through a two to 20 position switch it is connected to a source of negative input voltage, and a positive feedback circuit consisting of a chain of 25 resistors connected in series, a diode and an integrating RC element with an amplifier output.

The main disadvantage of this device is that it cannot store an instantaneous value eg 30

Since a continuous analog signal is generated for an unlimited time due to the absence of an instantaneous voltage value in the base memory cell, the parameters of which, after switching the circuit to storage mode, would not depend on the processes occurring in the circuit, and would be unchanged in time.

The closest to the technical essence of this invention is a device for long-term storage of instantaneous values of analog signals 2, belonging to the class of long-term discrete capacitor memories of multiple action devices with an analog information processing node and an inverse code-to-value conversion node. The elementary memory cell is a combination of a following circuit and a time-pulse phase multi-stable element (MES) with a multi-hump amplitude characteristic.

The number of equilibrium states of an MEA is determined by the ratio of the reference and clock frequencies, which is selected by the developer, based on the required accuracy of the device.

The MUE includes a buffer stage, a comparator, an RS flip-flop and a current amplifier. The input of the comparator receives a triangular voltage from the output of an external triangular voltage generator, and the other, the input voltage from a storage capacitor through a buffer cascade, made on two trasistors. The comparator output is connected to one of the RS-flip-flop inputs, the other input of which receives rectangular pulses from the output of an external rectangular-pulse generator. The pulses from the RS-flip-flop output through a current amplifier at one transistor are fed to a capacitor charge.

The duration of these pulses is inversely proportional to the voltage level across the capacitor. When the input voltage changes from zero to the minimum value, the change in the pulse duration at the output of the RS flip-flop is equal, where n is the frequency ratio of the square pulse generator and the triangular voltage.

The following memory circuit consists of a comparator, an inverter on the transistor and two charge-controlled amplifiers on two transistors and dividing semiconductor diodes.

At one input of the comparator, an input signal is received, at the other, its input is a signal from a storage capacitor through a buffer stage. At the command of an external source, the control signal blocks the comparator output and the voltage on the capacitor is retained due to the operation of the MCE,

The disadvantage of such a device is that the accuracy of its operation in the storage mode of an analogue signal is limited to a preselected finite number of discrete equilibrium states in a multi-hump amplitude characteristic of an MEA,

The aim of the invention is to improve the accuracy of the device.

The goal is achieved by the fact that in an analog storage device containing an amplifier, the input of which is connected to a storage element, for example, one of the capacitor plates, the other capacitor plate is connected to the zero potential bus, a comparator, one of the inputs of which is connected to the output of the device, another input of the comparator connected to the first control bus; the comparator output is connected to the R input of the first RS flip-flop; the first and second nonlinear elements, such as diodes, the second and the control bus, are entered

Kor-iMyTaTop, second RS flip-flop, third non-linear element, for example Diode, delay element, two keys, And element and binary counter, one of the inputs of which is connected to the output of the first key, another input of the binary counter is connected to the output of the delay element, binary outputs the counter is connected to the inputs of the element I, the output of which is connected to the S input of the first RS flip-flop, whose outputs are connected respectively to the input of the delay element, and one of the inputs of the first key, the other input of the first key is connected to the second control bus, output The comparator is connected to the anode of the first diode, the input of the delay element is connected to the anode of the second diode, the cathodes of the first and second diodes are connected to the R-input of the second RS-flip-flop and the cathode of the third diode, the S-input of the second RS-flip-flop is connected to one of the inputs of the first key The third diode anode is connected by the third control bus and one of the switch inputs, the other input of which is connected to the device input, the switch output is connected to one of the capacitor plates and one of the inputs of the second key, the other input of which is connected to the output the house of the second RS trigger; the output of the second key is connected to the first control bus.

FIG. 1 shows a functional diagram of the proposed device; FIG. 2 is a time diagram of the operation of the device.

It contains a switch 1, amplifier 2, a cumulative element, such as a capacitor 3, keys 4 and 5, comparator 6, RS-flip-flops 7 and 8, element 9, binary counter 10, delay element 11, nonlinear elements, such as diodes 12-14 , control tires 15-17, zero potential bus 18.

The device operates in two modes: in tracking mode — the output signal of the device follows changes in the input signal; in memory mode — the device stores the instantaneous value of the analog input signal that occurred at the time the memory command was received.

Tracking mode

The command signal is monitored in the form of a DC voltage corresponding to logical 1 and is fed from bus 17 to the input of switch 1 and through diode 14 connected in the forward direction to the R input of trigger 8, a constant voltage is set at its input output corresponding to the logical O. This voltage enters the input of the key 5 and translates it into

the disconnected state, thereby the initiating circuit of the charging circuit of the capacitor 3 voltage from the bus 15, which is supplied from an external triangular voltage generator (GTH).

At the same time, the switch 1 closes the circuit of the passage of voltage from the input of the device to the charge of the capacitor 3 and further through the amplifier 2 transmits this signal to the output device.

Amplifier 1 is an electrical cxefviy with an output impedance and an input impedance gain.

The constant charge time of a capacitor 3 is determined by the product of its capacitance and the output impedance of the input source in accordance with the formula (1

, , (one)

where T is the time constant of the charge circuit of capacitor 3;

with the value of the capacitance of the capacitor 3;

/ shchG

output impedance of the input signal (we take the P of switch 1 in the closed state to be O).

With the value T, «(where Ty is the minimum possible oscillation period of the component of the spectrum of the analog input signal), we can assume that the device inertia transmits the input signal voltage to its output.

The voltage from the output of the amplifier 2 is fed to one of the inputs of the comparator 6, to the other input of which voltage is supplied from the bus 15.

At the output of the comparator 6, rectangular positive pulses are generated at each instant of exceeding the instantaneous value of the positive voltage of the analog input signal of the current value of the triangular voltage GTH present on the bus 15. The duration of these pulses is directly proportional to the instantaneous voltage value of the analog input signal.

These pulses arrive at the I-input of the trigger 7 and set at its non-inverting output voltage, corresponding to logical 1, and at the inverting output to: voltage, corresponding to logical O.

This control voltage corresponding to the logical 1 simultaneously arrives at :.

The S-input of the trigger 8, on the R-input of which is present in the mode of failure, is a prohibitive voltage corresponding to logical 1. This command prevents a change in the logical state of the voltage on its output;

The R input of the same trigger 8 is through a diode 13 connected in the forward direction. This command additionally blocks a change in the logical state of the voltage at its output, which should not occur before the pulse at the output of the comparator has expired;

to the input of the key 4, which closes the circuit for the passage of positive rectangular pulses from the bus 15 to the counting input of the binary counter 11.

The control voltage, corresponding to a logical O, from the inverter output of this trigger 7 is supplied to:

input binary counter through the time delay circuit 11;

on the R-input trigger 8 through the diode

0 13, included in the forward direction.

If there is a voltage at the inputs of the counter 10, corresponding to a logical 1, at the input

5 and 9 also appears 1, which is fed to the S input of the trigger 8.

During the time of presence at the R-input of the trigger 8 of the prohibiting pulse of positive polarity, according to D stepping from the output of the comparator 6, the single pulses of positive polarity from the output of the element And 9 do not cause changes in the logic levels of the voltages at its outputs.

five

At the end of the pulse at the output of the comparator b, the duration of which is proportional to the instantaneous value of the output voltage of the device, the appearance of a positive pulse at the output of the element And 9

0 causes the state of trigger 8 to change to the opposite.

Now at the non-inverting output of the trigger 7, the Wits logical O, which is fed to the input of the key 5,

5 opens the pulse path from the bus 16 to the input of the counter 10, and the logical 1 at the inverting output, which through the delay element 11 causes the outputs of the counter 10 to zero.

At the same time, the positive pulse at the output of the element 9 disappears, but the output voltages of the trigger 7 remain until

J the arrival of the next positive pulse from the output of the comparator b to the trigger input 7.

Further, the processes in the device are repeated.

Memory mode

0

The memory command comes from the bus 17 in the form of a DC voltage corresponding to a logical O.

Claims (2)

1. USSR author's certificate No. 257156, class, G 11 C 27/00, 1968. 2. Avtometri; Number 3, 1972, p. .122-125 (prototype).