JPS5813015A - Monostable multivibrator - Google Patents

Monostable multivibrator

Info

Publication number
JPS5813015A
JPS5813015A JP56111754A JP11175481A JPS5813015A JP S5813015 A JPS5813015 A JP S5813015A JP 56111754 A JP56111754 A JP 56111754A JP 11175481 A JP11175481 A JP 11175481A JP S5813015 A JPS5813015 A JP S5813015A
Authority
JP
Japan
Prior art keywords
delay line
input
signal
flip
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56111754A
Other languages
Japanese (ja)
Inventor
Hiroshi Yoshimura
寛 吉村
Toshio Shoji
敏夫 東海林
Katsuji Horiguchi
勝治 堀口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56111754A priority Critical patent/JPS5813015A/en
Publication of JPS5813015A publication Critical patent/JPS5813015A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/033Monostable circuits

Abstract

PURPOSE:To realize a high-precision monostable multivibrator by using an input signal to and an output signal from a delay line as a setting and a resetting signal for a flip-flop. CONSTITUTION:An input trigger signal D is inputted to a delay line 21. The delay line 21 is composed of N stages of flip-flops, and the input trigger signal D propagates by a clock signal CK. Therefore, the signal inputted to the delay line 21 is outputted an accurate delay time later. A flip-flop 23 regards the trigger signal D as a data input D and is reset by the trigger signal D. The output of the delay line 21 is supplied to the reset input CL of the flip-flop through an NOR gate 22. Therefore, a high-precision monostable multivibrator is realized on the basis of the accurate delay time. Further, the delay line employs semiconductors to realize high integration.

Description

【発明の詳細な説明】 本発明は高集積にして高精度な単安定マルチバイブレー
タに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a highly integrated and highly accurate monostable multivibrator.

第1図は従来の単安定マルチバイブレータを示す。図に
おいて、1および4はNORゲート、2はコンデンサ、
3は抵抗、5〜7はインバータ、Dは入力トリガ、Rは
リセット信号、Q、Qは出力である。NORゲートIC
=は入力トリガD、リセット信号Rおよび出力Qと等価
なNORゲート4の出力が入力されており、いずれも“
0”のとき、A点は1”となる。コンデンサ2と抵抗3
は微分回路を構成している。NORゲート4:二はリセ
ット信号Rとこの微分回路出力が入力されている。
FIG. 1 shows a conventional monostable multivibrator. In the figure, 1 and 4 are NOR gates, 2 is a capacitor,
3 is a resistor, 5 to 7 are inverters, D is an input trigger, R is a reset signal, and Q and Q are outputs. NOR gate IC
= is input with input trigger D, reset signal R, and output of NOR gate 4 equivalent to output Q, all of which are “
When the value is 0'', the A point is 1''. capacitor 2 and resistor 3
constitutes a differential circuit. NOR gate 4:2 receives the reset signal R and the output of this differentiation circuit.

いま第2図(a)に示すことく、入カトリガD、リセッ
ト信号R1出力Qがいずれも”0”のとき、A点および
B点は”1”となり定常状態にある。この時、入力トリ
ガDが“1”:ユ変化すると、A点は10”に変化し、
さらにB点も瞬時に″0”に変化し、出力Qは’l”1
’−1Qは10”に反転する。B点は@0”に変化した
後微分回路を構成するコンデンサ2と抵抗30時定数に
より漸次@1″に変化し、NORゲート4のスレッショ
ルド電圧VTRを越えたとき、NORゲート4の出力は
′″0”に転じ、従って出力Qおよびζはそれぞれ10
”、′1#に変化する。また第2図Φ)に示すごとく、
リセット信号Rが“1′(二なると、時定数4=達しな
い状態においてもNORゲート4の出力は“0−一変化
し、出力Q、Qがそれぞれ′0”、“1”(二反転する
ことになる。
As shown in FIG. 2(a), when the input trigger D and the output Q of the reset signal R1 are both "0", the points A and B are "1" and in a steady state. At this time, when the input trigger D changes to "1", the A point changes to "10",
Furthermore, point B also instantaneously changes to "0", and the output Q is 'l'1
'-1Q is inverted to 10''. After changing to @0'', point B gradually changes to @1'' due to the time constant of capacitor 2 and resistor 30, which constitute the differentiating circuit, and exceeds the threshold voltage VTR of NOR gate 4. At that time, the output of NOR gate 4 turns to ``0'', so the outputs Q and ζ are each 10
”, '1#. Also, as shown in Figure 2 Φ),
When the reset signal R becomes ``1'' (2), the output of the NOR gate 4 changes from 0 to 1 even when the time constant 4 does not reach 2, and the outputs Q and Q change to ``0'' and ``1'' (2), respectively. It turns out.

このように第1図はリセット付の単安定マルチバイブレ
ータとなるが、数十μs以上の時定数を持つ単安定マル
チバイブレータを半導体集積回路で実現しようとすると
、抵抗およびコンデンサの占有面積が大幅に大きくなり
、かつ時定数の精度も低くなるという欠点がある。
In this way, Figure 1 shows a monostable multivibrator with a reset function, but if we try to realize a monostable multivibrator with a time constant of several tens of microseconds or more using a semiconductor integrated circuit, the area occupied by the resistors and capacitors will become large. It has the disadvantage that it becomes larger and the accuracy of the time constant becomes lower.

本発明はこのような欠点を解決するため、入力トリがが
入力される遅延線と、入力トリガによりセットされ、遅
延線出力もしくはリセット信号によりリセットされるフ
リップフロップで構成したもので、以下図面を用いて詳
細;−説明する。
In order to solve these drawbacks, the present invention consists of a delay line into which an input trigger is input, and a flip-flop that is set by the input trigger and reset by the delay line output or a reset signal. Use details;-explain.

第3図は本発明の一実施例を示す。図シーおいて、21
は単安定マルチバイブレータの時定数を実現するための
遅延線、nはNORゲート、ルはDタイプ・フリップフ
ロップ、24.25はセットアツプ時間を保障するため
のインバータである。
FIG. 3 shows an embodiment of the invention. In figure C, 21
is a delay line to realize the time constant of a monostable multivibrator, n is a NOR gate, le is a D-type flip-flop, and 24.25 is an inverter to ensure setup time.

遅延線21には入力トリガDが入力され、クロック信号
CKにより伝幡される。遅延線21は種々の実現方法が
あるが、後述の第5.図に示すごときダイナミック形マ
スタスレーブフリップフロップで実現し、段数をN段、
クロッ7□□′1□信号CKの周波数N±1 をfとすると、遅延線からは−「砂径に出力される。遅
延線21の出力はリセット信号Rと共ニN0セット人力
CLに与えられる。フリップフロップ器は入力トリガD
をデータ人力りとすると共堪ニクロック入力CKとして
おり、入力トリガDによりてセットされるよう(ニなっ
ている。
An input trigger D is input to the delay line 21 and propagated by the clock signal CK. There are various ways to implement the delay line 21, but the fifth method described below is the method for implementing the delay line 21. This is realized using a dynamic master-slave flip-flop as shown in the figure, and the number of stages is N.
If the frequency N±1 of the clock signal CK is f, then it is output from the delay line to the sand diameter. The flip-flop device has an input trigger D
When data is input manually, it is a synchronized clock input CK, and is set by the input trigger D (2).

いま第4図(a)に示すごとく入力トリガDが”0”、
リセット信号Rが10”のとき、出力Qは1o”の状態
を保持している。入力トリガDが11”に変化すると、
フリップフロップnがセットされ、出力Qは1”となる
。同時C二人カトリガDは遅延線21にも入力される。
Now, as shown in Fig. 4(a), the input trigger D is "0",
When the reset signal R is 10'', the output Q maintains the state of 1o''. When the input trigger D changes to 11”,
Flip-flop n is set, and output Q becomes 1''. Simultaneous C two-person trigger D is also input to delay line 21.

遅延線21に入力された”1″信号はクロック信号CK
により遅延#j21を伝幡し、ユ旦砂径に出力され、N
ORゲートnを介してフリップフロップ器をリセットし
、出力Qを“0”にする。
The “1” signal input to the delay line 21 is the clock signal CK
The delay #j21 is transmitted and output to the Yutan sand diameter, and the N
The flip-flop device is reset via the OR gate n, and the output Q is set to "0".

また第4図(b)に示すごとく、リセット信号Rが“1
#になると、遅延線出力が10″状態であっても強鱗的
にフリップフロップおはリセットされ、出力Qは10”
になる。  \                 1
このように第3図の構成をとることにより、抵抗やコン
デンサを用いないで単安定マルチバイブレータが実現で
きる。
Further, as shown in FIG. 4(b), the reset signal R is "1".
When it becomes #, even if the delay line output is in the 10" state, the flip-flop is forcefully reset, and the output Q becomes 10".
become. \ 1
By adopting the configuration shown in FIG. 3 in this manner, a monostable multivibrator can be realized without using resistors or capacitors.

以下、ρμsの単安定マルチバイブレータの設計例を示
すに、第1図に示す従来形では、時定数=0.69RC
より、R=32にΩ、C= 1000pFであり、例え
ば抵抗としてポリシリコン、容量として拡散を使用し、
それぞれ32Ω肩、 5 XIO”−’pシン−である
とすると、占有面積は抵抗で約I X 10’ gn2
、コンデンサで2X106師2となり、はソ1,5顛×
1.5鰭の大きさとなる。また、実現精度は±10チ以
上である。一方、第3図に示す本発明の実施例では、例
えば実現精度を±10 %以下とすると、遅延線のクロ
ック周波数fは±1/f < 2.2 pSより500
KF(Zとなり、遅延線の段数NはN/f=22/jS
より11段と求まる。いま遅延線を例えば第5図に示す
周知のダイナミック形マスタスレーブフリッチフロップ
で実現し、パタンルール311m程度の技術を用いたと
すると第3図の実施例の占有面積は約1×105μm2
、すなわち、0.33 uzX O,33vmとなり、
大幅な小型化を図れるとと\なる。
Below, we will show a design example of a monostable multivibrator with ρμs. In the conventional type shown in Fig. 1, the time constant = 0.69RC
Therefore, R = 32 Ω, C = 1000 pF, and for example, using polysilicon as the resistor and diffusion as the capacitor,
Assuming 32Ω shoulder and 5 XIO”-'p syn-, the occupied area is about I X 10'gn2 in resistance.
, with a capacitor it becomes 2x106 x 2, which is 1,5 x
The size is 1.5 fins. Furthermore, the realized accuracy is ±10 inches or more. On the other hand, in the embodiment of the present invention shown in FIG. 3, if the realized accuracy is ±10% or less, the clock frequency f of the delay line is 500 pS since ±1/f < 2.2 pS.
KF(Z, and the number of delay line stages N is N/f=22/jS
Therefore, 11 steps can be obtained. For example, if the delay line is realized by the well-known dynamic master-slave flip-flop shown in FIG. 5, and a technology with a pattern rule of about 311 m is used, the area occupied by the embodiment shown in FIG. 3 is approximately 1×105 μm2.
, that is, 0.33 uzX O, 33vm,
It would be great if it could be significantly downsized.

なお第5図で31〜34はインバータ、35.37はト
ランスミッションゲート、あはNANDゲート、38は
NORゲートである。
In FIG. 5, 31 to 34 are inverters, 35 and 37 are transmission gates, A is a NAND gate, and 38 is a NOR gate.

以上述べたごとく、本発明によれば、占有面積が大で高
精度を得にくい抵抗やコンデンサを不要とするため、高
集積、高精度な単安定マルチバイブレータを実現できる
As described above, according to the present invention, a highly integrated and highly accurate monostable multivibrator can be realized because resistors and capacitors that occupy a large area and are difficult to obtain high precision are unnecessary.

【図面の簡単な説明】 第1図は従来例を示す回路図、第2図(a)および(b
)は第1図の動作を説明するための波形図、第3図は本
発明の一実施例を示す回路図、第4図(a)および(b
)は第3図の動作を説明するための波形図、第5図は第
3図の遅延線の具体例を示す回路図である。 21・・・遅延線、 n・・・NORゲート、 乙90
.フリップフロップ。 代理人 弁理士 鈴 木   誠1ゾ占へ、饋。 第1図 第2図 φ)(b) 第3図
[Brief explanation of the drawings] Fig. 1 is a circuit diagram showing a conventional example, Fig. 2 (a) and (b)
) is a waveform diagram for explaining the operation of FIG. 1, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIGS. 4(a) and (b)
) is a waveform diagram for explaining the operation of FIG. 3, and FIG. 5 is a circuit diagram showing a specific example of the delay line of FIG. 3. 21...Delay line, n...NOR gate, Otsu90
.. flip flop. My agent, patent attorney Makoto Suzuki, is here. Figure 1 Figure 2 φ) (b) Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1、 入力トリガが入力される遅延線と、上記入力トリ
ガによりセットされ、上記遅延線出力もしくはリセット
信号によりセットされるフリップフロップからなること
を特徴とする単安定マルチバイブレータ。
1. A monostable multivibrator comprising a delay line into which an input trigger is input, and a flip-flop that is set by the input trigger and set by the output of the delay line or a reset signal.
JP56111754A 1981-07-16 1981-07-16 Monostable multivibrator Pending JPS5813015A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56111754A JPS5813015A (en) 1981-07-16 1981-07-16 Monostable multivibrator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56111754A JPS5813015A (en) 1981-07-16 1981-07-16 Monostable multivibrator

Publications (1)

Publication Number Publication Date
JPS5813015A true JPS5813015A (en) 1983-01-25

Family

ID=14569334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56111754A Pending JPS5813015A (en) 1981-07-16 1981-07-16 Monostable multivibrator

Country Status (1)

Country Link
JP (1) JPS5813015A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008091311A (en) * 2006-09-10 2008-04-17 Alpine Electronics Inc Led driving apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008091311A (en) * 2006-09-10 2008-04-17 Alpine Electronics Inc Led driving apparatus

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