JPS59207727A - Programmable oscillation circuit - Google Patents

Abstract

PURPOSE:To obtain the highly accurate setting of an on/off time and to facilitate the change of setting by providing a pulse generator that generates a pulse signal controlled by a crystal oscillator and a counter that sets on/off time. CONSTITUTION:A pulse generator 1 generates a pulse signal 1a of specified period controlled by a crystal oscillator. Counters 4, 5 count signals 2a, 3a of AND gates 2, 3 that AND the pulse signal 1a and Q signal and Q' signal of an FF10. Comparators 8, 9 compare signals 4a, 5a consisting of count values of counters 4, 5, and when they coincide, output signals 8a, 9a. The RS type FF10 is reset by the signal 8a, and set by the signal 9a and supplies signals Q, Q'. In such a constitution, a programmable oscillation circuit that can set on/off time at high accuracy and can change setting easily is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an oscillation circuit that periodically repeats on-off operations and in which on-off times can be set arbitrarily.

Conventionally, in this type of circuit, an e-ramp signal is generated in a ramp (romP) signal generation circuit including a time constant circuit consisting of a resistor and a capacitor, and this ramp signal is turned on and off.
There was an oscillation circuit that detected an appropriate level corresponding to the off-time pressure, outputted a pulse, and reset the ramp signal generation circuit.

Since the conventional oscillation circuit is configured as one or more,
The on/off time was determined by the time constant of the time constant circuit. However, as is well known, capacitors and resistors have considerably larger temperature fluctuation characteristics than crystal oscillators, etc.
Oscillation circuits including such elements have poor setting accuracy and stability, and have the disadvantage that changing settings is not easy.

This invention was made in order to eliminate the drawbacks of the conventional methods described above, and includes a pulse generator that generates a controlled time base signal in a crystal oscillator, and a pulse generator that sets the on/off time. and a pulse counter circuit.
Therefore, it is an object of the present invention to provide a programmable oscillation circuit in which the on/off time can be set with high accuracy and the settings can be easily changed.

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1#'i, a pulse generator that generates a pulse signal 1a with a predetermined period controlled by a crystal oscillator; 2.
3 is an AND gate that takes the AND of the pulse signal 1a and the Q1Q signal described later, 4.5 is a counter that counts the signals 2a, 3a of AND gates 2 and 3, and 6 and 7 are for differentiating the Q and Q signals. .

The signal 6a thus obtained is guided to counters 4 and 5.

These capacitors 8 and 9 are set by comparing the signals 4a and 5a consisting of the count values of the counters 4 and 5 with the setting signals NF and No, and when they match, the signals 8a+9a
10 is an R8 type flip-flop which is reset to L by signal 8a and set by signal 9a, and Q is set by signal 9a.

Supply Q signal.

FIG. 2 is a timing diagram showing the operation of the circuit shown in FIG. 1. To explain the operation, the initial state is flip.
When the Q and Q signals of the flop 10 go down as Q=0 and Q=1, the AND gate 3 opens and the pulse signal 1a from the pulse generator 1 is applied to the pulse counter 5 as the signal 3a. On the other hand, AND gate 2 is not opened and does not allow pulse signal 1a to pass through. Since the counter 5 counts the pulses of the signal 3a, its count value increases with time, and this count value is applied to one input of the comparator 9 from the signal 5aK. Comparator 9Fi signal 5a and setting signal No. (corresponds to final blade on time T□)
If the signal 5a is different from the setting signal NO at time t1, the signal 9a is output, that is, it is set to logic 1, and the flip
Set the flop of 10. K-machining, flip-
The Q signal of flop 10 becomes a logic 1; the Q signal becomes a logic 0.
Therefore, AND gate 2 opens and AND gate 3 closes. Therefore, the pulse signal from the pulse generator 1 is no longer applied to the aid counter 5, and "!7" (
The ERI counter 4 is reset when the Q signal changes from logic O to logic 1. At the same time, the pulse signal 1a from the pulse generator 1 and the like passes through the AND gate 2 to the signal 2a.
is applied to the counter 4 and starts counting. The count value of the counter 4 increases with time, and this count value is applied to the signal 4aK and one input of the comparator 8. ), and when this count value reaches the setting signal N, at time t2, the comparator 8 outputs the signal 8a (logical 1
) and reset the flip-flop 10.

The Q signal of flip-flop 10 becomes a logic zero, and the Q signal inverts to a logic one. In addition, it returns to the same state as the initial state mentioned above, and the same operation is repeated from now on.

The signal Bati of the comparator 8 becomes a pulse train signal having an on time T□ and an off time T2, and becomes the output of the circuit. Setting signals No. and NF can be set to any value, so
The on time T1 and off time T2 of the signal 8a can be arbitrarily selected.

In addition, in the above embodiment, as a flip-flop, R
Although the case of the -S flip-flop has been described, other types of 7-rip-flops can also have the same effect as the above embodiment.

As described above, according to the present invention, since the on/off time is determined by counting pulses from a stable crystal oscillator, a stable output signal can be obtained and the on/off time can be easily set. Next door.

This has the effect of obtaining highly accurate cutting signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a programmable oscillation circuit according to an embodiment of the present invention, and FIG. 2 is a time chart diagram illustrating the operation of the circuit shown in FIG. 1...Pulse generator, 2, 3...AND gate. 4.5... Counter, 6, 7... Capacitor, 8,
9... Comparator, 10... R-S Flicup fist flop. Agent Masuo Oiwa No. 1 Figure 1 Figure 2

Claims (1)

[Claims] A pulse generator that generates a pulse signal of a predetermined period; and a pulse generator that converts the pulse signal of the pulse generator into a first gate signal and a second gate signal that is an inverted logic of the first gate signal. a first counter that counts the pulse signal of the first gate circuit and is reset at a logic level change point of the first gate signal; a second counter that counts pulse signals of the second gate circuit and is reset at a logic level change point of the second gate signal; a first comparator for detecting that the count value of the first counter is equal to or greater than a predetermined first set value; a second comparator for detecting that the count value of the second counter is equal to or greater than a predetermined second set value; a flip-flip that is set and reset by the output signals of the first and second comparators, respectively, and supplies the first and second gate signals; The programmable oscillator circuit used as the signal to be sent to.