JPS6324664Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a retrigger monostable multivibrator, and more particularly to a retrigger monostable multivibrator capable of outputting pulses having an accurately set pulse width.

A conventional retrigger monostable multivibrator uses a time constant using a capacitor C, a resistor R, etc. to continue generating pulses for a predetermined time constant from the final trigger point.
However, in a retrigger monostable multivibrator that uses a time constant such as RC, there are large variations in the set pulse width due to variations in the time constant of RC etc. or other attached circuits, so precise accuracy such as time detection is required. Currently, it cannot be used for this purpose.

An object of the present invention is to provide a retrigger monostable multivibrator that outputs pulses with precisely set pulse widths.

According to the present invention, there is provided a shift register having a plurality of stages, capable of inputting a clock pulse and a single input pulse, sequentially shifting the single input pulse through each stage using the clock pulse, and outputting the state of each stage; An OR circuit or a NAND circuit connected to the output of each stage of the shift register, and outputs an output pulse having a pulse width determined by the period of the clock pulse and the number of stages of the shift register of the shift register. A retrigger monostable multivibrator is proposed, which is characterized in that it is obtained as the output of a circuit or a NAND circuit.

Embodiments of the retrigger monostable multivibrator according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows one embodiment of a circuit according to the present invention, which is composed of a shift register 1 and an OR circuit 2, and a single pulse having a pulse width T _IN is input to the shift register 1 from an input terminal. An accurate clock pulse calibrated by a crystal or the like is input to the shift register 1, and the clock pulse input to the shift register 1 sequentially shifts the pulses input to the shift register 1 to each stage constituting the shift register. The output of this stage is input to the OR circuit 2. Then, the output of OR circuit 2 is that the output of the shift register connected to the input of that circuit is all “0”.
Outputs “1” until it becomes . The operating waveforms of each part in the circuit of FIG. 1 will be explained with reference to FIGS. 2A and 2B.

Figure 2A shows the case where the input pulse has the same pulse width as the period of the clock pulse;
In, a is the clock pulse waveform, b is the input pulse waveform, and c, d, e, f, g are the shift register 1.
h is an output waveform having a pulse width T _W and represents the output of the OR circuit 2. In the case shown in Figure 2A, the number of stages in the shift register 1 is 5, but in general, in the case of n stages, the difference between the output pulse width _TW , the clock pulse period _TC , and the number of stages N of the shift register is The following relationship holds true.

T _W =NT _C (1) Figure 2B shows the case where the input pulse has a pulse width twice the period of the clock pulse. In Figure 2B, as in Figure 2A, a is the clock pulse waveform, and b is the Input pulse waveform, c, d, e, f,
g represents a waveform that is sequentially shifted in the shift register 1 and input to each input terminal of the OR circuit 2, and h represents an output waveform having a pulse width T _W and represents the output of the OR circuit 2. In the case shown in Fig. 2B, the number of stages of the shift register 1 is 5, but in general, the output pulse width is for the case of n stages.
T _W vs. input pulse width T _IN vs. clock pulse period T _C
The following relationship holds true between N and the number of stages N of the shift register.

T _W =NT _C +T _IN -T _C (2) Comparing Figure 2 A and B, Figure 2 A is the second
In Figure B, this can be considered as a special case where T _IN −T _C =0.

In the embodiment shown in FIG. 1, the case where the polarity of the input pulse is positive is shown, but even when the input pulse is negative polarity, the same output pulse as in the case of FIG. 1 can be obtained. is shown in FIG. 3 as another embodiment of the present invention. In FIG. 3, by using the shift register 3 and the NAND circuit 4, it is possible to obtain a positive output pulse even for a negative input pulse by taking the NAND of the output of the shift register 3. Since the waveforms of each part of the circuit in FIG. 3 can be more easily understood than the waveforms of each part shown in FIGS. 2A and 2B for the circuit of FIG. 1, their explanation will be omitted here.

Of course, in order to increase the accuracy of setting the output pulse width in the monostable multivibrator shown in FIGS. 1 and 3, it is possible to increase the repetition period of the clock pulse and increase the number of stages of the shift register.

As explained in detail above, by using the circuit according to the present invention, it is possible to set an output pulse width precision that was previously impossible, and the effect is extremely large when used in precision applications such as time detection.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the monostable multivibrator according to the present invention, and FIGS. 2A and B are operation waveform diagrams of each part of the block diagram of FIG. 1.
FIG. 3 is a block diagram of another embodiment of the monostable multivibrator according to the present invention. In the figure, 1 and 3 are shift registers, 2
is an OR circuit, and 4 is a NAND circuit.

Claims (1)

[Scope of utility model registration request] A shift register having a plurality of stages, capable of inputting a clock pulse and a single input pulse, sequentially shifting the single input pulse through each stage using the clock pulse, and outputting the state of the stage, and each stage of the shift register. an OR circuit or a NAND circuit connected to the output of the OR circuit or NAND circuit, and outputs an output pulse having a pulse width determined by the period of the clock pulse and the number of stages of the shift register of the shift register. A retrigger monostable multivibrator characterized by: