JPS58129883A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To make signal processing easy and to increase the sensitivity, by providing a transfer gate and a storage capacitor between a horizontal switch MOS transistor (TR) and a vertical signal line and connecting a connecting point between the gate and the TR to a reset gate. CONSTITUTION:Before signals stored in a photodiode 11, pulses phit, phis, phiR are sequentially turned on, a virtual signal is picked up from a reset TR17, and the potential under the storage capacitor 16 is reset to a voltage VR. Further, pulses phiv, phit, phis, phix are sequentially turned on and signals are sent to a CTD storage gate 13. When the pulse Ot is turned on, the voltage VR is set so as to flow charges to a vertical signal line 14, the potential of the line 14 is decreased and the transfer gate is in a sufficiently conductive state. Succeedingly, when the pulse phis is turned on, the charges flowing before and the signal charges are shifted to the gate 16 in a short time. Thus, through the simple signal processing, the device having high sensitivity is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a diode array in the light receiving section and uses a charge transfer element (ChargeTransf) as a readout register.
The present invention relates to a two-dimensional solid-state imaging device (hereinafter simply abbreviated as HOTOSE/SU) equipped with a CTD (hereinafter abbreviated as CTD).

Two types of photosensors are conventionally known: MO8 type and CCD type. Compared to the latter, the former has a higher utilization rate for the chip size and higher sensitivity, but each has its own advantages and disadvantages, such as the output signal is small and signal processing is difficult. However, there was something.

As a photo sensor to solve this problem, as shown in Fig. 1, an MO8 method is used for the light receiving part and a CCD is used for the readout register.
A method using the method 4) has been proposed.

Figure 1 shows a conventional example of a photosensor that has a diode array in the light receiving section and a CTD in the readout register.
In use, l is a photodiode array consisting of a p-n junction, 2
is a vertical switch MOS transistor (abbreviated as vMO8T); 3 is a scanner that sequentially switches the MOS transistors of : with clock φ7; 4 is a vertical signal line; 5 is a vertical switch MOS transistor;
is a Mol transistor for horizontal switch (hereinafter abbreviated as HMO8T).
The signal charges read out from the vertical signal line 4 are sent to the HMO8 through the VMO8T in synchronization with the pulse φx4.
It is sent to the CTD 6 via the T5 and read out sequentially from the Brian 7.

The photosensor shown in Figure 1 was expected to have excellent characteristics as a device that combines the advantages of the Mos method and the CCD method, but in reality, it has achieved extremely inadequate performance for the following reasons. .

FIG. 2 is a circuit diagram explaining the problem of the photo sensor shown in FIG.
13 schematically shows one storage electrode of the CTD, which is a horizontal register.

Photodiode 11 shown in FIG. vertical signal line 14,
If the capacitances of the storage electrodes 13 of the CTD are cP, cv, and Cc, then Cv>C, Cc-, (1) is generally satisfied. Signal charge taken out to the vertical signal line.・C out of 7
Since the amount Qc taken into TD is, Qc<Qv, and the signal charge can be sufficiently CT
It cannot be imported into D. Furthermore, the potential change Δvv due to the charge Qv taken out to the control signal line 14 is very small compared to the potential change ΔvP due to the optical signal in the photodiode section, so HMO8T12 is sufficiently conductive even when the pulse φ switch is turned on. state, the charge transfer time is very long, and sufficient transfer cannot be performed.

FIG. 3 is an equivalent circuit diagram illustrating in detail the present invention that solves the above problem. 10 and 14 in the figure are the same as in FIG. In Figure 3, the vertical signal line 14 and HMO8T12
A transfer gate 15, a storage voltage 1i16, and a reset transistor 17 are provided between the two.

FIG. 4 is a diagram showing an example of the timing of the drive pulse of the photosensor according to the present invention, and the direction shown by the arrow 30 is the ON state. The operation of the circuit shown in FIG. 3 will be explained below using the timing shown in FIG. 4.

First, before reading out the signal accumulated in the photodiode 11, φ1, φ, φ are turned on sequentially as shown in 22, 23, and 24 to generate a pseudo signal due to dark current accumulated during the horizontal readout time tH (29). is extracted from the reset transistor 17, and the potential under the storage capacitor 16 is reset to VB. Next is φ.

φ1. φ1. φ8 is sequentially turned on as shown at 25.26 and 27.28, and the signal is transferred to the CTD storage gate 13. Here, when φ1 turns on, the storage gate) 16 below is used as the source, and the charge is transferred from here to the vertical signal line 1.
By setting v8 so that it flows into the 4th side, the potential of the vertical signal line 14 can be lowered, and the transfer gate becomes sufficiently conductive. Therefore, φ is turned on and the storage gate) 16 is reversely turned to the drain side.
The charges and signal charges that previously flowed in can be transferred from the manual signal line 14 side to the storage gate 16 side in a short time. That is, a certain amount of charge is sent from the reset gate 17 side to the vertical signal line 14, and this is sent to the diode array 11.
By causing the signal charge sent from the side to flow back to the storage capacitor 16 side and further transferring it to the CTD, it becomes possible to send most of the signal charge to the CTD within a short time.

(The above transfer operation is performed during the horizontal retrace period 1B (Fig. 4, 21)
) is all done within. ) Here, it is also possible to connect the reset game ) 17 directly to the manual signal line 14, for example.

However, in such a connection, Cv＞C,・, Cc,
Since it is C8, even a slight change in VB causes a large change in the amount of charge.
Since the potential change at 3 is large, strict control of vl is required, and in reality it is difficult to obtain sufficient characteristics.

Therefore, the reset gate 17 is connected to the transfer gate 15 and the HMO
It is extremely important to provide between 8T12.

FIG. 5 is a diagram showing an embodiment of the present invention based on the above-mentioned principle, in which 1 to 7 are the same as shown in FIG. 1, 41 is a transfer gate, 42 is a storage capacitor, and 43 is a reset gate. be.

FIG. 6 shows an example of a sectional view of an embodiment of the present invention. In the figure, 61 is a p-type S1 substrate, 62 to 64 are n-swelled diffusion layers, 65 is an n-type S1 layer, 66 is an insulating film such as SiO2,
67. 69 to 72 are electrodes such as polycrystalline Sl, 68 is wiring made of a conductor such as A/, 62 is a photodiode, 67 is VMO8T, 68 is a vertical signal line, 69 is a transfer gate, 70 is a storage capacitor, 71 ViHMO8T
, 72 form storage gates of the CTD, respectively. Here, as a CTD, since the horizontal register requires high-speed operation of 5 to 10 MHz, B CD (Bulk C
Harge-transfer Device: M
, Kubo, Proc, 6th Combon 5ol
id 5tate Devlces, Tokyo, p1
73 (Jan.

(1975)), an n-layer 65 was provided. Although the reset gate is not shown in FIG.
is located adjacent to and perpendicular to the drawing.

In the above embodiments, a device that mainly uses electrons as the signal charge was shown, but it is clear that this can be applied in the same way even when holes are used by reversing the conductivity type of the semiconductor and the polarity of the voltage. Furthermore, it is clear that the structures and materials shown in FIG. 6 are not limited to these, and may be replaced with other structures having equivalent functions.

As explained above, according to the present invention, in a two-dimensional solid-state imaging device in which a diode array is provided in a light receiving section and a charge transfer element is provided in a readout register, a transfer gate is provided between a horizontal switch MO8) transistor and a vertical signal line. By providing a capacitor and connecting the point between the transfer gate and the horizontal switch MO8) transistor to the reset gate, it is possible to almost completely transfer the signal charge to the charge transfer element in a short period of time, and the signal charge accordingly A two-dimensional solid-state imaging device that is easy to process and has high sensitivity can be realized.

[Brief explanation of the drawing]

1 and 2 are diagrams showing a conventional solid-state imaging device, and FIGS. 3 and 4-1, FIG. 5, and FIG. 6 are diagrams showing an embodiment of the present invention. 41... Transfer gate, 4.2... Storage capacity, 43.
...Reset gate. Agent Patent Attorney Akio Takahashi ■ 2 Figure ψ1 ψ

Claims (1)

[Claims] 1. In a solid-state imaging device that transmits optical signal charges from a plurality of photodiodes to a charge transfer element and reads them out, a transfer gate, an accumulation Capacity setting C. Furthermore, a solid-state imaging device characterized in that a connection point between the transfer gate and the horizontal switch MO8) transistor is connected to a reset voltage source via a reset gate.