JPH07142692A - Photoelectric conversion device - Google Patents

Abstract

PURPOSE:To dispense with a memory such as a frame memory provided outside by a method wherein photoelectric conversion elements each composed of memory means connected to photodiodes which carry out a photoelectric conversion action through the intermediary of a switching means are provided. CONSTITUTION:Low level pulses are applied to terminal 112 and 113 to turn Trs 102 and 103 ON, a photodiode 101 and memory devices 106 and 107 are turned ON, and then low level pulses are applied to a terminal 111. Then, after a voltage is applied to terminals 116 and 117, high level pulses are applied to terminals 114 and 115 to reset the memory devices 106 and 107. Thereafter, the photodetecting part of the photodiode 101 is made to start its photocarrier storing action. After photocarriers are stored in the photodiode 101, light signals are transferred centering on the memory device 106, and the Tr 102 is turned OFF to hold photocarriers. By this setup, a memory means such as a frame memory provided outside can be dispensed with, and a photoelectric conversion device of this constitution can be simplified in a system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device for outputting a plurality of signals from a photodiode for photoelectric conversion.

[0002]

2. Description of the Related Art In recent years, with the development of LSI manufacturing technology, the solid-state image pickup device and the processing technology of the obtained video signal have advanced to a high degree.

For example, an example of moving image processing of MPEG1 is shown in FIG.
5 (Takenori Senoo, "Multimedia and Package", Proc.
~ 31, 1993). Here, a moving image process is shown in which a video signal that changes moment by moment is written in a memory for each frame, a correlation calculation between a previous frame and a current frame is performed, and a changed object image is coded.

[0004]

However, when making such a system, not only the frame memory,
The system itself, such as the driver circuit for addressing, has become relatively large-scale.

In view of the above problems, the present invention has been made in order to reduce the cost by reducing the system scale.

[0006]

The photoelectric conversion device of the present invention comprises a photoelectric conversion element comprising a photodiode for photoelectric conversion and a plurality of memory means connected to the photodiode via switch means. It has a plurality.

[0007]

According to the present invention, a photoelectric conversion element in a photoelectric conversion device is constituted by a photodiode and a plurality of memory means connected to the photodiode via a switch means, whereby a memory such as a frame memory is externally provided. It is possible to simplify the system by eliminating the need to provide means.

[0008]

Embodiments of the present invention will be described in detail below with reference to the drawings. <First Embodiment> FIG. 1 shows an equivalent circuit of a unit photoelectric conversion cell (photoelectric conversion element) according to the first embodiment of the present invention. In this embodiment, photoelectric conversion is performed by the photodiode 101, and the bipolar transistor 1 is used as a memory element.
06 and 107 are used, and
It is connected through the transistors 102 and 103 (switches).

Except for the photodiode 101,
All cell regions are shielded from light by a metal such as AL. The operation is performed in the order of reset, storage of optical carriers, transfer from the photoelectric conversion unit to the memory unit, and signal reading from the memory. These will be briefly described below.

First, a low level pulse is applied to the terminals 112 and 113, and the PMOS transistors 102 and 10 are
3 is turned on, the photoelectric conversion unit and the memory unit are electrically connected to each other, and then a Low-level pulse is applied to the terminal 111, whereby the photoelectric conversion unit and the memory unit are initialized to the voltage of the terminal 110 (first Reset). Next, terminals 116 and 11
When a high level pulse is applied to the terminals 114 and 115 after applying a predetermined voltage to the transistor 7 and the base potential of the transistor is increased by capacitive coupling, a forward bias is applied between the base and the emitter, and the bipolar transistor 10
Reference numerals 6 and 107 respectively perform emitter follower operations (second reset).

Upon completion of the second reset, the terminal 11
4,115 pulses fall, the base of the memory
At the same time that the emitters are reverse biased, the terminals 112,
A high-level pulse is applied to 113, the PMOS transistors 102 and 103 are turned off, the light receiving unit and the memory unit are separated, and then the light receiving unit starts the operation of accumulating optical carriers.

Here, at the time of the second reset, two memory cells were used, but there is no problem even if only one of them is used.

Next, when a predetermined accumulation time (t ₁ : first accumulation) is completed, first, in the first memory section (here, for example, the NPN transistor 106 is a cell constituted mainly). In order to transfer an optical signal, when a low level pulse is applied to the terminal 112 and the PMOS transistor 102 is turned on, the photocarriers stored in the photodiode part are transferred to the base region of the NPN transistor 106, and then the PMOS carrier is turned on. Transistor 102
The optical carrier is retained by turning off the.

At this time, the potentials of the photodiode and the base region of the memory section immediately before the transfer are set to Vd0 and Vb1, respectively.
0, the junction capacitance of the photodiode region is Cd,
When the total capacitance connected to the base region including the junction capacitance of the memory portion is Cb, the base potential Vb ₁₁ after transfer is represented by the following equation.

[0015] Therefore, in order to improve the transfer efficiency from the photodiode region to the memory region, it is desirable to design Cb as small as possible with respect to Cd. Further, since the base region of the NPN transistor 106 is shielded from light after the transfer, the storage operation is not newly performed in the base region, but the storage operation is continuously performed in the photodiode portion.
After a lapse of time t2 after the start of storage (second storage operation), perform exactly the same carrier transfer operation to the other NPN transistor 107 (memory 2) of the NPN transistor 106 that has previously transferred optical carriers. Due to
The optical carriers at the storage times t1 and t2 can be held in separate memories.

At this time, assuming that the potentials of the memory 2 before and after the transfer are Vb20 and Vb21, respectively, and the potential of the photodiode region immediately before the transfer is Vb ₂ , the base potential of the memory 2 after the transfer is: It is represented by. Here, the number of optical carriers generated in the photodiode during the accumulation time of t1 and t2 is N
1 and N2, with α as a proportional constant, N1 = α · t1 (3) N2 = α · t2 (4), but the number of optical carriers transferred to the memory Nm1, N2
Since m2 is capacity-divided as in the above formula (2), Nm1 = β · N1 (5) Nm2 = β · ((1-β) · N1 + (N2-N1)) (6) ) Becomes Here, the first term in the parentheses of the above equation (6) is the optical carrier remaining in the photodiode region after the transfer to the memory 1, and the second term is the optical carrier generated between t1 and t2. Therefore, as β becomes smaller than 1, Nm1
And the linearity of Nm2 with respect to the storage time is lost. In this case, by resetting the photodiode region immediately before the second accumulation, the first term of the above formula (6) is set to 0.
Therefore, the linearity of Nm2 can be ensured. Specifically, after transferring the photocarriers to the memory 1, a low-level pulse is applied to the terminal 113 to turn on the PMOS transistor 103 to turn on the cathode of the photodiode 101 and the NPN transistor 1.
When the low level pulse is applied to the terminal 111 after the base of 07 is turned on, the PMOS transistor 108
Is turned on, and the photodiode region and the base region of the transistor 107 are initialized.

Next, a high-level pulse is applied to the terminal 111 to turn off the PMOS transistor 108, and then the emitter terminal 117 of the NPN transistor 107 is set to the reset potential to perform the second reset and the reset operation is performed. When completed, the photodiode starts the second accumulation operation. By this operation, the number of carriers stored in the photodiode during the first and second storage periods can be made linear with the storage time.

The operation of the unit cell has been described above with reference to FIG. 1. The clock input terminals 111, 112, 113,
Since there are five, 114 and 115, it may be difficult to integrate them at a high density.

In that case, as shown in FIG.
The terminal 114 and the terminal 113 and the terminal 115 are commonly connected, and a ternary pulse may be applied to the terminals 112 and 113. As a ternary pulse, a high level is a level used in the description of FIG. 1 A low level is a level used in the description of FIG.
It is applied to the terminal during the accumulation period at a voltage value that causes the F state. And it is sufficient.

Further, as shown in FIG. 3, C _OX1 , C
There may be no problem even if you delete _OX2 .

In the second reset and read operations, this is the gate-source overlapping capacitance of the PMOS transistors 102 and 103, and the NPN transistor 10
This is the case where the base potentials of 6 and 107 can be controlled.

FIGS. 4 to 6 show a plan view and an x-direction and y-direction cross-sectional view of an example of a photoelectric conversion cell using the present invention. 4 to 6 show, for example, a poly-Si1 layer as an interconnection, an AL
This is an example of formation using a two-layer process. In each drawing, 220 is an n-type substrate, 221 is an n-type epitaxial layer, 204 and 205 are p-type layers, and 202 and 203 are dark n layers.
A mold layer, for example, 202 is an NPN transistor 106.
, 203 becomes the emitter region of the NPN transistor 107, and these transistors function as a memory. Further, the region indicated by 201 is the p-type layer 20.
6 and the n-type epitaxial layer 221 are photodiodes (light receiving regions), and 213 and 214 are PMOs for separating the light receiving region and the memory region.
This is the gate portion of the S switch. Reference numeral 212 is a gate wiring of a PMOS switch that separates adjacent photodiode regions, and a gate 214 is a wiring 216 formed of AL2 for connecting between adjacent pixels.
16 to n-type layers 202 and 203 (NPN transistor 1
The structure is such that the memory region can also be shielded from light by extending over the emitter regions (06, 107). 21
Reference numeral 5 is a selective oxide film and 218 is an interlayer insulating film.

Next, an operation of reading an optical signal from the memory in the photoelectric conversion device using the photoelectric conversion cell will be described with reference to FIG.

A portion 8 abbreviated by a square symbol in the drawing
0 corresponds to the sensor unit shown in FIGS. In this embodiment, the operation of the line sensor in which the sensors are arranged one-dimensionally will be described.

It is assumed that the sensor resetting and accumulating operations are performed by the method described above.

After the accumulation is completed, a high level pulse is applied to the terminal 75 to turn on the NMOS transistor 83, and then a high level pulse is applied to the terminal 71, so that the memory section 1 on the sensor cell (for example, at time t1). The base potential of (holding the accumulated optical carriers) is lifted by capacitive coupling, the NPN transistor 106 (shown in FIG. 3) is turned on, and the operation of reading an optical signal from the memory unit 1 to the capacitor 85 is performed. Similarly, the memory unit 2
The optical signal (for example, holding the optical carriers accumulated at time t2) is read out to the capacitor 86. The above operation is performed in parallel for each sensor cell, and the optical signals of all pixels are simultaneously read into the capacitors.

Next, when the scanning circuit 93 is activated, signals are serially transferred from the capacitors to the output lines via the NMOS transistors 87 and 88, and the optical signal of the memory 1 is passed through the output amplifier 91 to the terminal 79 and the optical signal of the memory 2 is transmitted. The signal is output to the terminal 80 through the output amplifier 92. The terminal 77
When a high level pulse is applied to the NMOS transistors 89 and 90, the NMOS transistors 89 and 90 are turned on, and the output line is
The reset potential is given by. Also, terminals 74 and 7
When a high level pulse is applied to 5, the NMOS transistors 81 and 83 are turned on, and the temporary storage capacitor 85 and the vertical output line are initialized to the reset voltage given from the terminal 73. Similarly, when a high level pulse is applied to the terminals 74 and 76, the NMOS transistor 82,
84 is turned on, and the temporary storage capacitor 86 and the vertical output line are initialized to the reset voltage given from the terminal 73.

As described above, by incorporating the memory element in the photoelectric conversion cell, it is not necessary to provide a frame memory outside the solid-state image pickup device, and the system can be simplified.

Further, when the correlation calculation between different frames is normally performed, it is necessary to read the signal of the same memory a plurality of times. However, in this embodiment, since the bipolar transistor forming the emitter follower is used as the memory element, It can be read multiple times. At this time, the ratio γ of the signal voltage destroyed at each read is expressed by the following equation.

[0030] C _B ... Base capacity of memory NPN transistor h _FE ... Current amplification rate of memory NPN transistor C _V ... Temporary storage capacity (85, 86, ...) And load capacity of emitter signal Therefore, the smaller the value of γ, the greater the number of times of reading. For that purpose, C _B is increased.

Increase h _FE .

Reduce C _V. In many cases, these parameters are determined so that γ is 90% or more. <Embodiment 2> FIG. 8 is a circuit diagram showing a second embodiment according to the present invention.

This embodiment is an area sensor in which the photoelectric conversion cells shown in FIG. 3 are arranged two-dimensionally, and the vertical output line 62 has the output terminal of the memory 1 and the vertical output line 63 has the output terminal of the memory 2. It is connected. Therefore, the two vertical scanning circuits 60 and 61 drive the two drive lines for each photoelectric conversion cell. At the time of the second resetting of the photoelectric conversion cells, all the drive lines may be boosted to the High level at the same time, or the vertical scanning circuit may be operated to sequentially perform row by row.

At the time of reading a signal from the memory 1, a high level pulse is applied to the terminals 74 and 75, and NMO is applied.
The S transistors 81 and 83 are turned on, and the temporary storage capacitor 85 and the vertical output line 62 are initialized to the reset voltage given from the terminal 73. Next, when the pulse of the terminal 74 is lowered and the NMOS transistor 81 is turned off, the vertical scanning circuit 60 is operated so that a high level pulse is applied to the drive line 64.
From the signal passing through the vertical output line 62 to the temporary storage capacitor 85.
Read to. After that, the horizontal scanning circuit 93 is operated in the same manner as in the first embodiment to serially read the signals of the first row.

When the signal reading from the memory 1 of the first row is completed, similarly, the temporary storage capacitor 85 is reset and the signal from the memory 1 of the next row is read. By repeating the above operation for the number of rows, it is possible to serially read the signals of the memory 1 of all the pixels.

Further, the signal of the memory 1 is temporarily stored in the storage capacity 85.
, And before operating the horizontal scanning circuit 93,
High pulse is applied to the terminals 74 and 76, and the capacitance 86,
And the vertical output line 63 is reset, and then the pulse of the terminal 74 is lowered to turn off the NMOS transistor 82.
After this state, the vertical scanning circuit 61 is operated to drive the drive line 6
When a high level pulse is applied to 5, the signal of the memory 2 can be read out to the capacitor 86 via the vertical output line 63. After that, when the horizontal scanning circuit 93 is driven, the signal of the memory 1 is output from the terminal 79 and the content of the memory 2 is output from the terminal 80 simultaneously via the NMOS transistors 87 and 88 and the output amplifiers 91 and 92, respectively. It is read serially. Therefore, the terminals 79, 8
If a difference operation is performed on a signal of 0 (for example, a simple differential amplifier may be provided in the solid-state image sensor), a difference signal between frames can be easily obtained, and the system can be simplified easily. Can be achieved. When a high level pulse is applied to the terminal 77, the NMOS transistors 89 and 90 are turned on, and the output line becomes the reset potential given from the terminal 78.

In the above first to second embodiments, the signal reading operation is performed in the order of the memory 1 and the memory 2 after all the storage operations are completed.
It goes without saying that there is no problem even if they are read in the order of.
Further, there is no problem even if the signal is read from the memory 1 during the second accumulation operation. Further, as a result of performing the correlation calculation between the two frames, when the motion amount is small and high accuracy cannot be obtained, the information in the memory 1 is retained as it is, and the motion amount continues until the motion amount becomes large enough to ensure the accuracy. After performing the accumulation operation, the data may be transferred to the memory 2 and the operation may be performed again. Further, as described in the first embodiment, there is no problem even if the memory and the photodiode are reset and new storage is performed while the information in the memory 1 is held as it is. <Third Embodiment> FIG. 9 is a circuit diagram showing a third embodiment of the present invention.

This embodiment is a modification of the second embodiment shown in FIG. 8 and has a single vertical scanning circuit. Therefore, since the two memories are driven by using the single scanning circuit 60, the selection switches 70 and 71 are provided in each row of the sensor.

For example, when the scanning circuit 60 is operated after applying a high level pulse to the terminal 66, a read operation is performed on the memory 1 of each sensor, and after applying a low level pulse, the scanning circuit 60 is applied. Is operated, the reading operation is performed on the memory 2 of each sensor.

Therefore, as compared with the second embodiment, although the space for the switch means for each row is required, the space can be saved by the amount of the scanning circuit 61, leading to cost reduction. <Fourth Embodiment> FIG. 10 is a circuit diagram showing a fourth embodiment according to the present invention.

This embodiment is an improvement of the second embodiment shown in FIG. In the first embodiment, when the signal is read from the memory to the temporary storage capacity, the destruction rate γ of the original signal on the memory is expressed by the above-mentioned equation (8).

This embodiment is made for the purpose of reducing C _V in the equation (8), and the equivalent circuit is as shown in FIG.

In the present embodiment, buffer means 66 and 67 are provided for each vertical output line 62 and 63 as compared with the second embodiment, and the value of C _V in equation (8) is temporarily stored. Capacity 8
It can be reduced by 5,86. Here, the value of the temporary storage capacity is often designed in consideration of transfer efficiency during horizontal transfer, and a value of 1 pF or more is often used.
Also, the value of the vertical output line parasitic capacitance naturally increases as the number of connected elements increases, but it becomes about 5 pF for up to 1000 elements. Therefore, the effect of reducing the degree of signal destruction according to the present embodiment is great, and often leads to a reduction of 20% or more. The driving method and the like of this embodiment are the same as those of the second embodiment. <Embodiment 5> One of the methods for detecting motion from a moving image,
There is a pattern matching method (blank-out, "Digital signal processing of images", Nikkan Kogyo Shimbun pp221-227). This is a method in which two consecutive frame images are gradually shifted and a position where the difference is minimized is searched for, and that position is set as a motion.

That is, the image g _i-1 (x,
y) and the image g _i (x of the current frame, y) and thinking, by shifting the image g _i (x, y) of the current _{frame, min ΣΣ {g i (x} + ξ, y + η) -g i-1 (x , y)} ² or, _min ΣΣ | and requests a ^{_{2 | g i (x + ξ}} , y + η) -g i-1 (x, y).

In this embodiment, two consecutive frame images are held in the memories 1 and 2, respectively, and g _i (x + ξ, y + η) -g _i-1 (x, y) is directly output when reading out. The specific equivalent circuit diagram is as shown in FIG.

The operation of this embodiment will be briefly described.

First, according to the method of the first or second embodiment, two continuous frame images g _i-1 (x, y) and g _i are respectively stored in the memory 1 and the memory 2 on each photoelectric conversion cell. (X,
The signal corresponding to y) is retained. Now, let us consider a case where g _i (x + ξ, y + η) −gi ₋₁ (x, y) when both ξ and η are positive.

First, a High pulse is applied to the terminals 74 and 75 to reset the temporary storage capacitor 85 and the vertical output line 62 to the voltage applied to the terminal 73. Next, terminal 75
Then, when the vertical scanning circuit 60 is operated after the pulse of the terminal 74 is lowered, the signal of the memory 1 of the photoelectric conversion cell of the first row is read to the temporary storage capacitor 85. Simultaneously with the completion of reading, after the pulse of the terminal 75 is lowered, a High pulse is applied to the terminals 74 and 76 to reset the temporary storage capacitor 86 and the vertical output line 63. During this reset period, the vertical scanning circuit 60 'is idled by η-1. When the reset period ends, the pulse at the terminal 74 falls, and when the vertical scanning circuit 60 'outputs the next η bit, the signal of the memory 2 of the photoelectric conversion cell in the ηth row is read to the temporary storage capacitor 86. , The pulse of the terminal 76 falls at the same time when the reading is completed.

First, the horizontal scanning circuit 93 'is set to ξ-1.
After idling by the number of bits, horizontal scanning circuits 93, 93 '
Are operated in synchronization with each other, the terminals 79 and 80 have g _i-1 (x, 1) and g _i (x + ξ, 1) (x = 1,
2, ...) is output.

Although not shown in FIG. 11, terminals 79 and 8
A signal of 0 can be easily obtained as g _i (x + ξ, 1) -g _i-1 (x, 1) by providing a differential amplifier, for example.

By performing the same operation on the remaining rows, a signal of g _i (x + ξ, y + η) -g _i-1 (x, y) is directly output from the solid-state image pickup device. Therefore, it is possible to realize a low-cost system that does not require a frame memory for motion detection.

In the above description, both ξ and η are positive values, but in the case of negative values, this can be easily done by simply replacing the scanning circuit for idle feed. <Embodiment 6> In the embodiments up to now, the photoelectric conversion cell having the device structure shown in FIGS. 4 to 6 has been described, but in the case of this structure, the accumulation operation is completed and the optical carrier is transferred to the memory. Even during the holding period, the photoelectric conversion operation continues in the photodiode section, and carriers generated near the device surface of the photodiode section enter the memory section because the PMOS transistor is in the OFF state. However, carriers generated at a relatively deep portion of the substrate diffuse under the PMOS transistor,
It may be mixed in the memory section.

In this embodiment, the device structure of the sensor portion is improved. As shown in FIGS. 12 to 13, a p ⁺ layer 217 is provided in a band shape immediately below the photodiode portion, and a potential Vp at the outer peripheral portion. Is given. This structure uses well-known VOD (Vertical Overflow Drain) for this sensor structure in CCD devices, and allows photo carriers to flow into the p ⁺ layer before carriers move by diffusion under the PMOS transistor. This controls crosstalk from the photodiode section to the memory section. The potential of the p ⁺ layer 217 does not cause any problem for each sensor cell, but the chip size can be made smaller when the sensor cells are arranged outside the light receiving region. <Embodiment 7> In the first to sixth embodiments, each photoelectric conversion cell has two memory sections, but three or more memory cells are separately provided.
There is no problem even if there is a memory section. However, if the proportion of the memory area in the photoelectric conversion cell increases, the sensitivity naturally lowers. In this embodiment, in order to prevent a decrease in sensitivity, a micro lens is provided above each photoelectric conversion cell as shown in FIG.

As a result, the light that has hitherto been applied to the memory portion can be focused on the light receiving area, and the sensitivity can be prevented from lowering. In addition to the microlenses, the same effect can be obtained by stacking photoelectric conversion films (Harada, “2.
CCD type solid-state image sensor for HDTV of 1,000,000 pixels, laminated with amorphous Si photoelectric conversion film "," Nikkei Electronics ", February 22, 1988, NO. 441, pp2
07-212).

[0055]

As described in detail above, according to the present invention, the photoelectric conversion element is constituted by the photodiode and the plurality of memory means connected to the photodiode through the switch means. Further, it is possible to simplify the system by eliminating the need to provide a memory means such as a frame memory externally.

[Brief description of drawings]

FIG. 1 is an equivalent circuit of a unit photoelectric conversion cell according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit of a unit photoelectric conversion cell according to another embodiment of the present invention.

FIG. 3 is an equivalent circuit of a unit photoelectric conversion cell according to another embodiment of the present invention.

FIG. 4 is a plan view of an example of a photoelectric conversion cell using the present invention.

5 is a cross-sectional view in the x direction of the photoelectric conversion cell in FIG.

6 is a y-direction cross-sectional view of the photoelectric conversion cell in FIG.

FIG. 7 is a circuit configuration diagram showing an embodiment of a photoelectric conversion device using a photoelectric conversion cell according to the present invention.

FIG. 8 is a circuit configuration diagram showing another embodiment of a photoelectric conversion device using the photoelectric conversion cell according to the present invention.

FIG. 9 is a circuit configuration diagram showing another embodiment of the photoelectric conversion device using the photoelectric conversion cell according to the present invention.

FIG. 10 is a circuit configuration diagram showing another embodiment of the photoelectric conversion device using the photoelectric conversion cell according to the present invention.

FIG. 11 is a circuit configuration diagram showing another embodiment of the photoelectric conversion device using the photoelectric conversion cell according to the present invention.

FIG. 12 is a cross-sectional view showing an embodiment in which the device structure of the sensor unit is improved.

FIG. 13 is a sectional view showing an embodiment in which the device structure of the sensor unit is improved.

FIG. 14 is a cross-sectional view showing a case where a microlens is provided on a photoelectric conversion cell.

FIG. 15 is an explanatory diagram of a moving image processing example of MPEG1.

[Explanation of symbols]

 101 Photodiode 102 PMOS Transistor 103 PMOS Transistor 106 Bipolar Transistor 107 Bipolar Transistor 110 Terminal 111 Terminal 112 Terminal 113 Terminal 114 Terminal 115 Terminal 116 Terminal 117 Terminal

Claims (2)

[Claims] 1. A photoelectric conversion device comprising a plurality of photoelectric conversion elements each comprising a photodiode for performing photoelectric conversion and a plurality of memory means connected to the photodiode via a switch means. 2. The memory means comprises a pair of two main electrode regions made of a semiconductor of the same conductivity type and a control electrode region made of a semiconductor of a conductivity type opposite to the main electrode region. The photoelectric conversion device according to claim 1, further comprising a transistor that stores the signal of 1. in the control electrode region.