JPH07115182A - Photoelectric transducer having memory function and solid-state image pickup device - Google Patents
Photoelectric transducer having memory function and solid-state image pickup deviceInfo
- Publication number
- JPH07115182A JPH07115182A JP5258172A JP25817293A JPH07115182A JP H07115182 A JPH07115182 A JP H07115182A JP 5258172 A JP5258172 A JP 5258172A JP 25817293 A JP25817293 A JP 25817293A JP H07115182 A JPH07115182 A JP H07115182A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- film
- transparent electrode
- solid
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006386 memory function Effects 0.000 title description 6
- 238000006243 chemical reaction Methods 0.000 claims abstract description 30
- 238000007667 floating Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000010408 film Substances 0.000 claims description 43
- 238000009792 diffusion process Methods 0.000 claims description 36
- 238000003384 imaging method Methods 0.000 claims description 30
- 239000010409 thin film Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 230000008569 process Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は高精細ファクシミリ、デ
ジタル複写機、画像入力機器や静止画カメラ等に利用さ
れるメモリー機能付き光電変換素子および固体撮像装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion element with a memory function and a solid-state image pickup device used in high-definition facsimiles, digital copying machines, image input devices, still image cameras and the like.
【0002】[0002]
【従来の技術】従来、CCD型、MOS型固体撮像装置
が開発、実用化されてビデオカメラ、ファクシミリ、デ
ジタル複写機等に広く使われている。半導体デバイス、
プロセス技術の急激な進歩により、特にCCD型固体撮
像装置の画素数、感度、撮像速度等の諸性能が飛躍的に
向上した。今や、ハイビジョンテレビ用の固体撮像装置
の開発が精力的に進められている。ハイビジョンテレビ
では200万画素(1920×1036画素)を必要と
し、そのために最先端の微細プロセスを駆使してその開
発が進められ、単一の画素サイズは約7×7μm2まで
縮小された。しかしながら、これ以上の画素サイズの縮
小はデバイスおよびプロセス面で難しいレベルに近づい
ている。MOS型固体撮像装置はフォトダイオードに蓄
えられた信号電荷をMOS型電界効果トランジスタ(M
OS−FET)のスイッチ動作によって順次選択的に取
り出すもので、MOS型はデバイスおよびプロセスがC
CD型に比べて簡単であるために、画素数の増大および
低コスト化に適しているが、信号感度が微弱で且つ容量
性結合による雑音が大きいために、CCD型に比べて感
度、S/Nの面で劣る。2. Description of the Related Art Conventionally, CCD type and MOS type solid state image pickup devices have been developed and put into practical use, and are widely used in video cameras, facsimiles, digital copying machines and the like. Semiconductor device,
Due to the rapid progress of the process technology, various performances such as the number of pixels, the sensitivity and the imaging speed of the CCD type solid-state imaging device have been dramatically improved. Now, development of a solid-state imaging device for a high-definition television is energetically advanced. A high-definition television requires 2 million pixels (1920 × 1036 pixels), and for that reason, the development has been advanced by making full use of the latest fine process, and the single pixel size has been reduced to about 7 × 7 μm 2 . However, further reduction of the pixel size is approaching a difficult level in terms of device and process. The MOS-type solid-state imaging device uses the MOS-type field effect transistor (M
(OS-FET) is sequentially and selectively taken out by the switch operation. In the MOS type, the device and process are C
Since it is simpler than the CD type, it is suitable for increasing the number of pixels and lowering the cost. However, since the signal sensitivity is weak and the noise due to capacitive coupling is large, the sensitivity and S / Inferior in terms of N.
【0003】昨今、S/N向上のために各画素内で信号
レベルを増幅した後、MOS−FETからなるスイッチ
を介して画像信号を取り出す増幅型MOS固体撮像装置
(特公昭58−50030号公報)が開発されている。
従来例における増幅型MOS固体撮像装置の光電変換素
子の断面図および等価回路を各々図4(a)、(b)に
示す。同図(a)に示す光電変換素子30は半導体基板
1上に形成したMOS−FET、そのゲート電極31上
に設けた捕集電極32、光導電膜9および透明電極10
からなり、透明電極10に適切な直流電圧を印加した状
態で、被写体からの光が光導電膜9に入射すると、その
入射光量に応じた信号電圧が捕集電極32を通じてゲー
ト電極31に誘起されて増幅された信号電流がMOS−
FETのソース電極3またはドレイン電極4に現われる
という原理に基ずくもので、各水平走査によって読み出
した後、ライン毎に順次、ゲート電極31を所望の電圧
にリセットする。同図(b)に示す等価回路は(a)の
光電変換素子30、アクセス用MOS−FET17、リ
セット用MOS−FET33およびアクセス用MOS−
FET17のゲート電極を行毎に共通に接続してなる垂
直選択ライン18a、18b、18c、同MOS−FE
Tのソース電極を列毎に共通に接続してなる水平選択ラ
イン19a、19b、19c、リセット用MOS−FE
T33のゲート電極を行毎に共通に接続してなるリセッ
トライン34a、34b、34c、水平選択用MOS−
FET20a、20b、20c、垂直駆動回路22と水
平駆動回路23およびリセット駆動回路35からなる。
光電変換素子以外に1画素あたり2個のMOS−FET
が必要であり、更に垂直選択ライン18a、18b、1
8cと水平選択ライン19a、19b、19cおよびリ
セットライン34a、34b、34cの3本の配線が必
要であり、これが高集積化の障害となっている。Recently, an amplifying type MOS solid-state image pickup device (Japanese Patent Publication No. 58-50030) for extracting an image signal through a switch composed of a MOS-FET after amplifying a signal level in each pixel for improving S / N. ) Is being developed.
A sectional view and an equivalent circuit of a photoelectric conversion element of an amplification type MOS solid-state imaging device in a conventional example are shown in FIGS. 4 (a) and 4 (b), respectively. The photoelectric conversion element 30 shown in FIG. 3A is a MOS-FET formed on the semiconductor substrate 1, a collection electrode 32 provided on the gate electrode 31, a photoconductive film 9 and a transparent electrode 10.
When the light from the subject is incident on the photoconductive film 9 in the state where an appropriate DC voltage is applied to the transparent electrode 10, a signal voltage corresponding to the incident light amount is induced in the gate electrode 31 through the collection electrode 32. Signal current amplified by MOS-
This is based on the principle of appearing in the source electrode 3 or the drain electrode 4 of the FET, and after reading by each horizontal scanning, the gate electrode 31 is reset to a desired voltage sequentially for each line. The equivalent circuit shown in FIG. 9B is the photoelectric conversion element 30, the access MOS-FET 17, the reset MOS-FET 33, and the access MOS-of FIG.
Vertical selection lines 18a, 18b, 18c, which are formed by commonly connecting the gate electrodes of the FETs 17 for each row, and the same MOS-FE.
Horizontal selection lines 19a, 19b, 19c formed by commonly connecting the source electrodes of T for each column, reset MOS-FE
Reset lines 34a, 34b, 34c formed by commonly connecting the gate electrodes of T33 for each row, horizontal selection MOS-
It comprises FETs 20a, 20b, 20c, a vertical drive circuit 22, a horizontal drive circuit 23 and a reset drive circuit 35.
Two MOS-FETs per pixel other than photoelectric conversion elements
Is required, and vertical selection lines 18a, 18b, 1
8c, horizontal selection lines 19a, 19b and 19c, and reset lines 34a, 34b and 34c are required, which is an obstacle to high integration.
【0004】情報処理システムにおける画像入力機器、
静止画カメラ用固体撮像装置は静止画を対象とするため
に動画の場合ほどの高速撮像を必要としない。しかしな
がら、通常の印刷物と同等の高画質が要求されるため
に、ハイビジョンテレビ用固体撮像装置に比べても、更
に大きな画素数が必要とされる。つまり、400万〜2
500万個の画素数が必要である。これを従来方式のC
CD型またはMOS型固体撮像装置で実現することは極
めて困難である。従って、現在はデジタル複写機、ファ
クシミリ、画像入力機器における画像読み取りには1次
元固体撮像装置が用いられている。この場合、主走査は
電気的に行い、副走査は機械的な駆動によってページ読
み取りをしている。読み取りは1ライン毎に行なうため
に、必要な撮像素子は1ラインのみで簡単になるが、読
み取り速度が遅い。Image input device in information processing system,
The solid-state image pickup device for a still image camera does not require high-speed image pickup as in the case of a moving image because it targets a still image. However, since a high image quality equivalent to that of an ordinary printed matter is required, a larger number of pixels is required even compared with a solid-state imaging device for high-definition television. That is, 4 million to 2
A pixel count of 5 million is required. This is the conventional C
It is extremely difficult to realize with a CD type or MOS type solid-state imaging device. Therefore, currently, a one-dimensional solid-state image pickup device is used for image reading in digital copying machines, facsimiles, and image input devices. In this case, main scanning is performed electrically, and sub-scanning is page reading by mechanical drive. Since the reading is performed for each line, the required image pickup element is simple with only one line, but the reading speed is slow.
【0005】[0005]
【発明が解決しようとする課題】現在、最多の画素数を
誇るハイビジョンテレビ用固体撮像装置の画素数は約2
00万画素である。情報処理システムにおける画像入力
装置では対象は静止画であるが、ビデオカメラ以上の高
精細な読み取りが要求され、400万〜2500万画素
の撮像装置が必要になる。従来のCCD型やMOS型の
固体撮像装置で画素数をこのレベルまで増大させること
は技術的に困難であると同時にコストの面からも難し
い。At present, the number of pixels of a solid-state image pickup device for a high-definition television, which boasts the largest number of pixels, is about two.
It is, 000,000 pixels. Although an image input device in an information processing system targets still images, it requires high-definition reading that is higher than that of a video camera, and requires an imaging device with 4 to 25 million pixels. It is technically difficult and costly to increase the number of pixels to this level in the conventional CCD type or MOS type solid-state imaging device.
【0006】画像情報は一旦、画像メモリーに蓄えられ
て、信号処理が施される。従って、広い意味での画像入
力装置では、撮像装置とメモリーが対となって使用さ
れ、画素数の増大と共に回路規模が大きくなる。The image information is once stored in the image memory and subjected to signal processing. Therefore, in the image input device in a broad sense, the image pickup device and the memory are used as a pair, and the circuit scale increases as the number of pixels increases.
【0007】[0007]
【課題を解決するための手段】光電変換素子はSi基板
上に形成したソース拡散層、ドレイン拡散層およびトン
ネル酸化膜、トンネル酸化膜上に設けた浮遊ゲート、浮
遊ゲート上に酸化膜を介して設けた制御ゲート、制御ゲ
ート上に順次形成した光導電膜と透明電極から構成す
る。A photoelectric conversion element includes a source diffusion layer, a drain diffusion layer and a tunnel oxide film formed on a Si substrate, a floating gate provided on the tunnel oxide film, and an oxide film on the floating gate. The control gate is provided, a photoconductive film sequentially formed on the control gate, and a transparent electrode.
【0008】上記の光電変換素子とアクセス用スイッチ
からなる画素を2次元配列して撮像面を形成し、各画素
の光導電膜、透明電極を画素間で共通の薄膜層とするこ
とによって固体撮像装置を構成する。なお、アクセス用
スイッチはMOS−FETで構成する。Pixels composed of the above photoelectric conversion elements and access switches are two-dimensionally arranged to form an image pickup surface, and the photoconductive film and transparent electrode of each pixel are formed into a thin film layer common to the pixels, thereby forming a solid-state image pickup. Configure the device. The access switch is composed of a MOS-FET.
【0009】[0009]
【作用】Si基板およびウエル拡散層に高電圧を、透明
電極にリセット電圧を印加し、撮像面全面に光照射する
と光導電膜の光導電効果によりリセット電圧が制御ゲー
トに導かれ、全画素の浮遊ゲート上の電荷がウエル拡散
層に引き抜かれる。その後、Si基板およびウエル拡散
層を零電位にして透明電極に撮像用電圧を印加して、被
写体からの画像を撮像面に結ばせると画像パターンに従
って浮遊ゲートに電荷が注入される。この撮像状態の
後、透明電極に読み取り用電圧を印加して垂直選択ライ
ンおよび水平選択ラインの各1ラインを順次アクセスす
ることにより、画像信号を読み取る。When a high voltage is applied to the Si substrate and the well diffusion layer and a reset voltage is applied to the transparent electrode and the entire image pickup surface is irradiated with light, the reset voltage is guided to the control gate by the photoconductive effect of the photoconductive film, and all the pixels are exposed. The charge on the floating gate is extracted to the well diffusion layer. After that, the Si substrate and the well diffusion layer are set to zero potential, and an imaging voltage is applied to the transparent electrode to connect an image from a subject to the imaging surface, and charges are injected into the floating gate according to the image pattern. After this imaging state, a reading voltage is applied to the transparent electrode to sequentially access each one of the vertical selection line and the horizontal selection line to read the image signal.
【0010】本発明の固体撮像装置において、画素は基
本的に1個の光電変換素子と1個のアクセス用MOS−
FETのみで構成されること、およびリセット動作状態
および撮像動作状態は共に透明電極および光電変換膜を
介して行われるために、リセット用MOS−FETおよ
びリセットラインが不要になる。よって、チップの平面
構造が極めて簡単になり画素数および画素密度の増大が
容易になる。更に画像入力装置において、撮像装置とメ
モリーデバイスが同一のSi基板上に集積化されている
ためにシステムが簡単になる。In the solid-state image pickup device of the present invention, the pixel is basically one photoelectric conversion element and one access MOS-
The MOS-FET for resetting and the reset line are not necessary because the FET is configured only, and the reset operation state and the imaging operation state are both performed through the transparent electrode and the photoelectric conversion film. Therefore, the planar structure of the chip is extremely simple, and it is easy to increase the number of pixels and the pixel density. Further, in the image input device, the system is simplified because the image pickup device and the memory device are integrated on the same Si substrate.
【0011】[0011]
【実施例】以下、本発明の実施例を図面を参照しながら
説明する。Embodiments of the present invention will be described below with reference to the drawings.
【0012】図1は本発明の第1の実施例おける半導体
基板上に形成したメモリー機能付き光電変換素子の平面
図である。光電変換素子はSi基板1上にウエル拡散層
2を設けてその上にソース拡散層3、ドレイン拡散層4
および両拡散層間に介在する形でトンネル酸化膜5を設
け、トンネル酸化膜5上にポリSi膜からなる浮遊ゲー
ト6を堆積し、更に浮遊ゲート6上に酸化膜7を介して
ポリSi膜からなる制御ゲート8を堆積し、制御ゲート
8上に順次、光導電膜9と透明電極10を堆積すること
によって製作する。11、12は各々Al膜からなるソ
ースおよびドレイン電極である。本図では基板1はn型
導電体、ウエル拡散層はp型導電体で、ソース拡散層3
およびドレイン拡散層4はn型であり、チャンネルはn
型である。なお、ドレイン拡散層4を正電源に接続する
と、ソース拡散層3に接続したソース電極11からフロ
ーティグゲート6上の電荷によって制御された信号電流
が出力される。トンネル酸化膜5は所望の電界を印加す
ることによって、ウエル拡散層2と浮遊ゲート6間で電
子の授受を可能にするものであり、その膜厚は約10n
mである。制御ゲート8はトンネル電流を制御したり、
読み出し条件を設定するための電界を発生させるもので
ある。基板から制御ゲート8までの構造はフラッシュメ
モリーのセル構造に類似している。メモリーセル上に光
導電膜9と透明電極10を堆積させた構造で、光電変換
とメモリー機能を達成させている。光導電膜9としては
a・Si、CdSまたは有機光導電体等の光導電膜が適
している。透明電極10としてはITO膜が適してい
る。ウエル拡散層をグランド電位にして、透明電極10
に正の撮像電圧を印加した状態で露光すると、光導電膜
9の動作により制御ゲートにも撮像電圧が伝わり、トン
ネル酸化膜6を介して信号電荷がウエル拡散層から浮遊
ゲート6に注入される。その結果、ソース拡散層3、ド
レイン拡散層4および2種のゲート電極6、8からなる
MOS−FETの閾値電圧Vthは大きくなり、信号電流
は減少する。露光しない場合は光導電膜が導電しないた
めに浮遊ゲート6の電荷は変化せず、Vthも変化しな
い。よって、信号電流は減少しない。FIG. 1 is a plan view of a photoelectric conversion element with a memory function formed on a semiconductor substrate according to the first embodiment of the present invention. In the photoelectric conversion element, a well diffusion layer 2 is provided on a Si substrate 1, and a source diffusion layer 3 and a drain diffusion layer 4 are formed on the well diffusion layer 2.
Further, a tunnel oxide film 5 is provided so as to be interposed between both diffusion layers, a floating gate 6 made of a poly-Si film is deposited on the tunnel oxide film 5, and a poly-Si film is further formed on the floating gate 6 via an oxide film 7. Then, the control gate 8 is deposited, and the photoconductive film 9 and the transparent electrode 10 are sequentially deposited on the control gate 8. Reference numerals 11 and 12 denote source and drain electrodes each made of an Al film. In this figure, the substrate 1 is an n-type conductor, the well diffusion layer is a p-type conductor, and the source diffusion layer 3
And the drain diffusion layer 4 is n-type and the channel is n-type.
It is a type. When the drain diffusion layer 4 is connected to a positive power supply, the source electrode 11 connected to the source diffusion layer 3 outputs a signal current controlled by the charges on the floating gate 6. The tunnel oxide film 5 makes it possible to transfer electrons between the well diffusion layer 2 and the floating gate 6 by applying a desired electric field, and the film thickness thereof is about 10 n.
m. The control gate 8 controls the tunnel current,
An electric field for setting the read condition is generated. The structure from the substrate to the control gate 8 is similar to the cell structure of flash memory. With the structure in which the photoconductive film 9 and the transparent electrode 10 are deposited on the memory cell, photoelectric conversion and a memory function are achieved. As the photoconductive film 9, a photoconductive film such as a.Si, CdS, or an organic photoconductor is suitable. An ITO film is suitable as the transparent electrode 10. With the well diffusion layer at the ground potential, the transparent electrode 10
When exposure is performed with a positive imaging voltage applied to, the imaging voltage is transmitted to the control gate by the operation of the photoconductive film 9, and the signal charge is injected from the well diffusion layer to the floating gate 6 through the tunnel oxide film 6. . As a result, the threshold voltage Vth of the MOS-FET composed of the source diffusion layer 3, the drain diffusion layer 4 and the two kinds of gate electrodes 6 and 8 becomes large, and the signal current decreases. When not exposed, the charge of the floating gate 6 does not change and Vth does not change because the photoconductive film does not conduct. Therefore, the signal current does not decrease.
【0013】図2は本発明の第2の実施例における固体
撮像装置の等価回路を示す。2次元配列した各画素15
は実施例1の光電変換素子16とアクセス用MOS−F
ET17からなる。18a、18b、18cはアクセス
用MOS−FET17のゲート電極を行毎に共通に接続
してなる垂直走査ライン、19a、19b、19cはア
クセス用MOS−FETのソース電極を列毎に共通に接
続してなる水平走査ライン、20a、20b、20cは
水平走査用MOS−FET、21は水平走査用MOS−
FET20a、20b、20cのソース電極を共通に接
続してなる画像信号出力ライン、22は垂直走査ライン
18a、18b、18cを順次駆動するための垂直駆動
回路、23は水平走査用MOS−FET20a、20
b、20cを順次駆動するための水平駆動回路である。
24は光電変換素子を構成するウエルを共通に接続する
共通ウエルラインである。各光電変換素子16のソース
電極は各アクセス用MOS−FETのドレインに接続
し、光電変換素子16のドレイン電極は正電源に接続し
ている。画素は基本的に1個の光電変換素子16と1個
のMOS−FET17のみで構成されること、およびリ
セットプロセスと撮像プロセスは共に光導電膜9を介し
て一斉に行われるために、リセットラインが不要になる
ことにより構造が極めて簡単になり画素数および画素密
度の増大が容易になる。なお、1次元配列した光電変換
素子16とアクセス用MOS−FETからなる画素と、
水平走査用MOS−FETと水平駆動回路とから1次元
固体撮像装置が構成できることは明かである。FIG. 2 shows an equivalent circuit of the solid-state image pickup device according to the second embodiment of the present invention. Each pixel 15 arranged two-dimensionally
Is the photoelectric conversion element 16 and the access MOS-F of the first embodiment.
It consists of ET17. Reference numerals 18a, 18b and 18c are vertical scanning lines formed by commonly connecting the gate electrodes of the access MOS-FETs 17 for each row, and 19a, 19b, 19c are commonly connected for each column of the source electrodes of the access MOS-FET. Horizontal scanning line, 20a, 20b and 20c are horizontal scanning MOS-FETs, and 21 is a horizontal scanning MOS-FET.
An image signal output line formed by commonly connecting the source electrodes of the FETs 20a, 20b, and 20c, a vertical drive circuit 22 for sequentially driving the vertical scan lines 18a, 18b, and 18c, and a horizontal scan MOS-FET 20a and 20.
It is a horizontal drive circuit for sequentially driving b and 20c.
Reference numeral 24 is a common well line for commonly connecting wells forming photoelectric conversion elements. The source electrode of each photoelectric conversion element 16 is connected to the drain of each access MOS-FET, and the drain electrode of the photoelectric conversion element 16 is connected to the positive power supply. The pixel is basically composed of only one photoelectric conversion element 16 and one MOS-FET 17, and since both the reset process and the imaging process are simultaneously performed via the photoconductive film 9, the reset line is By eliminating the above, the structure becomes extremely simple and the number of pixels and the pixel density can be easily increased. In addition, a pixel including a photoelectric conversion element 16 and a MOS-FET for access, which are arranged one-dimensionally,
It is obvious that a one-dimensional solid-state image pickup device can be constructed from the horizontal scanning MOS-FET and the horizontal drive circuit.
【0014】次に、リセット、撮像、読み出しの3つの
動作状態からなる本光電変換素子16の典型的な撮像方
式を図3を参照しながら説明する。第1のリセット動作
状態では透明電極を零電位にしてウエル拡散層を高電圧
(約10v)に保った状態で、光導電膜9の全面に被写
体とは別に、光源から強い光を照射することによって、
その光導電効果で制御ゲートを零電位にし、浮遊ゲート
6上の電荷をウエル拡散層2に吐き出させる動作状態で
ある。その結果、浮遊ゲート6から電荷が消失し、光電
変換素子を構成するMOS−FETの閾値電圧Vthが負
になる。つまり、このリセット動作状態の終了後には光
電変換素子を構成する全MOS−FETのVthは負にな
る。第2の撮像動作状態では透明電極に撮像電圧(約1
0v)を印加し、ウエル拡散層を零電位にした状態で露
光することによって、光導電膜9の光導電効果により撮
像面上の画像パターンに従って制御ゲートに撮像電圧が
印加され、制御ゲートの電位パターンにしたがってトン
ネル酸化膜を介して信号電荷がウエル拡散層2から浮遊
ゲート6に注入される。その結果、ソース拡散層3、ド
レイン拡散層4および2種のゲート電極からなるトラン
ジスタの閾値電圧Vthは画像パターンに従って正にな
る。露光されていない光導電膜9は導電しないために、
制御ゲート8の電圧に変化はなく、従って浮遊ゲート6
の電荷も変化せず、Vthは負のままである。撮像時間は
光導電膜9とトンネル電流の応答時間で決まり、光導電
膜としてa・Siを用い、トンネル酸化膜厚10nmの
場合、100μs以下である。第3の読み出し動作状態
は透明電極を零電位に保ち、光導電膜の全面にリセット
時と同一の光源から強い光を照射した状態で、垂直駆動
回路22および水平駆動回路23から各々走査信号を出
力することによって、順次、選択された画素からの画像
信号が画像信号出力ライン21に出力させる。つまり、
アクセス用MOS−FET17を2次元的に走査するこ
とによって、光電変換素子16を構成するMOS−FE
Tの閾値電圧に従って、2値化された画像信号が画像信
号出力ライン21から出力される。読み出し時、透明電
極10に印可する電圧を制御することによって、2値化
のスライスレベルを変えることもできる。画像信号が不
揮発性メモリーの浮遊ゲート8に蓄えられているため
に、非破壊的に読み出すことが出来ると同時に電源を切
っても画像情報が失われない。従って、このメモリー機
能は画像処理用のメモリーも兼ねることができる。Next, a typical image pickup system of the photoelectric conversion element 16 having three operation states of reset, image pickup and read will be described with reference to FIG. In the first reset operation state, the transparent electrode is set to zero potential and the well diffusion layer is kept at a high voltage (about 10 V), and intense light is emitted from the light source to the entire surface of the photoconductive film 9 separately from the subject. By
The photoconductive effect brings the control gate to zero potential, and the charge on the floating gate 6 is discharged to the well diffusion layer 2. As a result, the charge disappears from the floating gate 6, and the threshold voltage Vth of the MOS-FET forming the photoelectric conversion element becomes negative. That is, after completion of the reset operation state, Vth of all MOS-FETs constituting the photoelectric conversion element becomes negative. In the second imaging operation state, the imaging voltage (about 1
0v) is applied to expose the well diffusion layer at zero potential, and an imaging voltage is applied to the control gate according to the image pattern on the imaging surface due to the photoconductive effect of the photoconductive film 9. Signal charges are injected from the well diffusion layer 2 into the floating gate 6 through the tunnel oxide film according to the pattern. As a result, the threshold voltage Vth of the transistor including the source diffusion layer 3, the drain diffusion layer 4, and the two kinds of gate electrodes becomes positive according to the image pattern. Since the unexposed photoconductive film 9 does not conduct,
There is no change in the voltage of the control gate 8 and therefore the floating gate 6
The electric charge of Vth remains unchanged and Vth remains negative. The imaging time is determined by the photoconductive film 9 and the response time of the tunnel current, and is 100 μs or less when a.Si is used as the photoconductive film and the tunnel oxide film thickness is 10 nm. In the third read operation state, the transparent electrode is kept at zero potential, and the vertical drive circuit 22 and the horizontal drive circuit 23 respectively send scanning signals while the entire surface of the photoconductive film is irradiated with intense light from the same light source as at the time of reset. By outputting, the image signals from the selected pixels are sequentially output to the image signal output line 21. That is,
A MOS-FE that constitutes the photoelectric conversion element 16 by two-dimensionally scanning the access MOS-FET 17.
A binarized image signal is output from the image signal output line 21 according to the threshold voltage of T. It is also possible to change the binary slice level by controlling the voltage applied to the transparent electrode 10 during reading. Since the image signal is stored in the floating gate 8 of the non-volatile memory, it can be read nondestructively and at the same time the image information is not lost even when the power is turned off. Therefore, this memory function can also serve as a memory for image processing.
【0015】[0015]
【発明の効果】本発明の光電変換素子では信号電荷が浮
遊ゲートに保持されるために、非破壊読み出しが出来る
ばかりではなく、電源を切断してもメモリ−機能により
画像信号が消滅しない。また、本発明の固体撮像装置で
は画素が基本的に1個の光電変換素子と1個のアクセス
用MOS−FETで構成され、且つリセットラインが不
要であるためにチップの平面構造が極めて簡単になり、
画素数および画素密度の増大が容易になる。更に、撮像
装置とメモリーデバイスが同一のSiチップとして集積
化されるためにシステムが簡略化できる。以上の諸機能
により本発明の産業上の効果は極めて大である。In the photoelectric conversion element of the present invention, since the signal charge is held in the floating gate, not only non-destructive reading can be performed, but also the image signal does not disappear due to the memory function even when the power is turned off. Further, in the solid-state image pickup device of the present invention, the pixel is basically composed of one photoelectric conversion element and one access MOS-FET, and since the reset line is not necessary, the planar structure of the chip is extremely simple. Becomes
It is easy to increase the number of pixels and the pixel density. Furthermore, since the image pickup device and the memory device are integrated as the same Si chip, the system can be simplified. Due to the above various functions, the industrial effect of the present invention is extremely large.
【図1】本発明の第1の実施例における光電変換素子の
断面図FIG. 1 is a sectional view of a photoelectric conversion element according to a first embodiment of the present invention.
【図2】本発明の第2の実施例における固体撮像装置の
等価回路図FIG. 2 is an equivalent circuit diagram of a solid-state imaging device according to a second embodiment of the present invention.
【図3】本発明の固体撮像装置の撮像方式を示す図FIG. 3 is a diagram showing an imaging method of the solid-state imaging device of the present invention.
【図4】(a)は従来例における増幅型MOS固体撮像
装置の光電変換素子の断面図 (b)は従来例における増幅型MOS固体撮像装置の等
価回路図4A is a cross-sectional view of a photoelectric conversion element of an amplification type MOS solid-state imaging device in a conventional example, and FIG. 4B is an equivalent circuit diagram of an amplification type MOS solid-state imaging device in a conventional example.
1 Si基板 2 ウエル拡散層 3 ソース拡散層 4 ドレイン拡散層 5 トンネル酸化膜 6 浮遊ゲート 7 酸化膜 8 制御ゲート 9 光導電膜 10 透明電極 16 光電変換素子 17 アクセス用MOS−FET 18 垂直走査ライン 19 水平走査ライン 20 水平走査用MOS−FET 21 画像信号出力ライン 22 垂直駆動回路 23 水平駆動回路 24 共通ウエルライン DESCRIPTION OF SYMBOLS 1 Si substrate 2 Well diffusion layer 3 Source diffusion layer 4 Drain diffusion layer 5 Tunnel oxide film 6 Floating gate 7 Oxide film 8 Control gate 9 Photoconductive film 10 Transparent electrode 16 Photoelectric conversion element 17 Access MOS-FET 18 Vertical scanning line 19 Horizontal scan line 20 Horizontal scan MOS-FET 21 Image signal output line 22 Vertical drive circuit 23 Horizontal drive circuit 24 Common well line
Claims (3)
ル拡散層領域に形成したソース拡散層、ドレイン拡散層
およびトンネル酸化膜、トンネル酸化膜上に設けた浮遊
ゲート、浮遊ゲート上に酸化膜を介して設けた制御ゲー
ト、制御ゲート上に順次形成した光導電膜と透明電極か
らなることを特徴とする光電変換素子。1. A well diffusion layer formed on a Si substrate, a source diffusion layer and a drain diffusion layer and a tunnel oxide film formed in a well diffusion layer region, a floating gate provided on the tunnel oxide film, and an oxide film on the floating gate. A photoelectric conversion element comprising a control gate provided via a photoconductive film, a photoconductive film sequentially formed on the control gate, and a transparent electrode.
ッチからなる画素を1次元または2次元配列し、光導電
膜、透明電極を各々画素間で共通の薄膜層としたことを
特徴とする固体撮像装置。2. A pixel comprising a photoelectric conversion element according to claim 1 and an access switch is arranged one-dimensionally or two-dimensionally, and a photoconductive film and a transparent electrode are formed as a thin film layer common to each pixel. Solid-state imaging device.
加し、リセット電圧を透明電極に印加し、撮像面の全面
に光照射することによって、リセット電圧を制御ゲート
に導き、浮遊ゲート上の電荷を除去する第1の動作状態
と、Si基板およびウエル拡散層を零電位にして、撮像
用電圧を透明電極に印加した後、被写体からの画像パタ
ーンを撮像面に結ばせることにより、ウエル拡散層から
浮遊電極へ電荷を注入させる第2の動作状態、および垂
直選択ラインおよび水平選択ラインの各1ラインを順次
アクセスすることにより、画像信号を読み取る第3の動
作状態からなることを特徴とする請求項2記載の固体撮
像装置。3. A high voltage is applied to the Si substrate and the well diffusion layer, a reset voltage is applied to the transparent electrode, and the entire surface of the image pickup surface is irradiated with light, whereby the reset voltage is guided to the control gate, and the reset voltage is applied to the floating gate. The first operation state in which electric charges are removed, the Si substrate and the well diffusion layer are set to zero potential, the imaging voltage is applied to the transparent electrode, and then the image pattern from the subject is connected to the imaging surface, so that the well diffusion is performed. A second operation state in which charges are injected from the layer to the floating electrode and a third operation state in which an image signal is read by sequentially accessing each one of the vertical selection line and the horizontal selection line are characterized. The solid-state imaging device according to claim 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5258172A JPH07115182A (en) | 1993-10-15 | 1993-10-15 | Photoelectric transducer having memory function and solid-state image pickup device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5258172A JPH07115182A (en) | 1993-10-15 | 1993-10-15 | Photoelectric transducer having memory function and solid-state image pickup device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07115182A true JPH07115182A (en) | 1995-05-02 |
Family
ID=17316531
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5258172A Pending JPH07115182A (en) | 1993-10-15 | 1993-10-15 | Photoelectric transducer having memory function and solid-state image pickup device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07115182A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997045875A1 (en) * | 1995-05-10 | 1997-12-04 | National Semiconductor Corporation | Base capacitor coupled photosensor with emitter tunnel oxide for very wide dynamic range in a contactless imaging array |
WO1998021756A1 (en) * | 1996-11-12 | 1998-05-22 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Sensor element |
US6141243A (en) * | 1996-11-12 | 2000-10-31 | Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. | Sensor element |
JP2017537454A (en) * | 2014-07-09 | 2017-12-14 | キム,フン | Image sensor unit pixel and light receiving element thereof |
-
1993
- 1993-10-15 JP JP5258172A patent/JPH07115182A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997045875A1 (en) * | 1995-05-10 | 1997-12-04 | National Semiconductor Corporation | Base capacitor coupled photosensor with emitter tunnel oxide for very wide dynamic range in a contactless imaging array |
WO1998021756A1 (en) * | 1996-11-12 | 1998-05-22 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Sensor element |
US6141243A (en) * | 1996-11-12 | 2000-10-31 | Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. | Sensor element |
KR100319057B1 (en) * | 1996-11-12 | 2001-12-29 | 슈베르트 헬무트 | Sensor element |
JP2017537454A (en) * | 2014-07-09 | 2017-12-14 | キム,フン | Image sensor unit pixel and light receiving element thereof |
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