JPS58129751U - current mode logic circuit - Google Patents

current mode logic circuit

Info

Publication number
JPS58129751U
JPS58129751U JP19527082U JP19527082U JPS58129751U JP S58129751 U JPS58129751 U JP S58129751U JP 19527082 U JP19527082 U JP 19527082U JP 19527082 U JP19527082 U JP 19527082U JP S58129751 U JPS58129751 U JP S58129751U
Authority
JP
Japan
Prior art keywords
transistor
emitter
bias
base
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19527082U
Other languages
Japanese (ja)
Inventor
ウイリアム・ダブリユ−・アラン
ハ−バ−ト・ストツパ−
Original Assignee
バロ−ス・コ−ポレ−シヨン
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by バロ−ス・コ−ポレ−シヨン filed Critical バロ−ス・コ−ポレ−シヨン
Publication of JPS58129751U publication Critical patent/JPS58129751U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086—Emitter coupled logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の全体的な補償ネットワークの概略図、
第２図はマイナス１の温度補償ファクターとマイナス２
の全体的温度補償ファクターを有する温度補償サブサー
キットの概略図、第３図はプラス１の温度補償ファクタ
ーと０の全体的補償ファクターを有する温度補償サブサ
ーキットの概略図、第４図は本考案の全電圧温度補償回
路の概略図、第５図は第４図の全体的電圧温度補償回路
を含む改良された電流モード・論理回路の概略図である
。 １１・・・補償ネットワーク出カドランシスター、１３
．２１，２７，３３，４５，５１，５５゜５７・・・抵
抗、２５．３１．４１．４９．６１゜７１．８７，９１
．９３，１０１，１２３゜１２７・・・トランジスター
、１９・・・温度補償回路、３７・・・温度補償サブサ
ーキット、３９・・・温度補償ネットワーク出力、４１
・・・出力補償トランジスター〇 １４０−Ｘ１１Figure 1 is a schematic diagram of the overall compensation network of the present invention;
Figure 2 shows a temperature compensation factor of minus 1 and a temperature compensation factor of minus 2.
FIG. 3 is a schematic diagram of a temperature compensation subcircuit with an overall temperature compensation factor of plus 1 and an overall compensation factor of 0; FIG. Schematic Diagram of the Total Voltage Temperature Compensation Circuit. FIG. 5 is a schematic diagram of an improved current mode logic circuit including the total voltage temperature compensation circuit of FIG. 11...Compensation Network Output Ran Sister, 13
．． 21, 27, 33, 45, 51, 55° 57... Resistance, 25.31.41.49.61° 71.87, 91
．． 93,101,123°127...Transistor, 19...Temperature compensation circuit, 37...Temperature compensation subcircuit, 39...Temperature compensation network output, 41
...Output compensation transistor〇140-X11

Claims (1)

【実用新案登録請求の範囲】 コレクタ、ベース及びエミッタを具備する第１トランジ
スタ及び第２トランジスタを有し、第１トランジスタの
エミッタが第２トランジスタのエミッタに共通接続し、
第１トランジスタのベースが入力部として機能し、両ト
ランジスタの少なくとも一つのコレクタが回路出力部と
して機能する！流モードであって、 第１トランジスタ及び第２トランジスタの共通接続エミ
ッタに電源電圧を結合するバイアス部材と、電源電圧及
び接合温度の変化を補償するため当該バイアス部材を制
御行酷に変える補償部材とからなり、当該バイアス部材
は、前記共通接続のエミッタと電源の間に直列接続した
第１のバイアス用トランジスタ及び第１のエミッタ抵抗
を含み、当該第１のバイアス用トランジスタのコレクタ
は当該共通接続のエミッタに接続し、当該第１のバイア
ス用トランジスタのエミッタは当該第１のエミッタ抵抗
を介して電源に接続し、当該バイアス部材は更に当該第
２トランジスタのベースと電源の間に直列接続した第２
のバイアス用トランジスタ及び第２のエミッタ抵抗を含
み、当該第２のバ゛　　イアス用トランジスタのコレク
タは当該第２トランジスタのベースに溶銃し、当該第２
のバイアス用トランジスタのエミッタは当該第２のエミ
ッタ抵抗を介して電源に接続し、当該バイアス部材は、
当該第２トランジスタのベースとの間に接続したバイア
ス抵抗を含むことを特徴とする電流モード論理回路。[Claims for Utility Model Registration] A first transistor and a second transistor each having a collector, a base, and an emitter, the emitter of the first transistor being commonly connected to the emitter of the second transistor;
The base of the first transistor acts as an input and the collector of at least one of both transistors acts as a circuit output! a biasing member for coupling a power supply voltage to the commonly connected emitters of the first transistor and the second transistor; and a compensation member for controlling the biasing member in a controlled manner to compensate for changes in the power supply voltage and junction temperature. The bias member includes a first bias transistor and a first emitter resistor connected in series between the commonly-connected emitter and the power supply, and the collector of the first bias transistor is connected to the commonly-connected emitter. The emitter of the first biasing transistor is connected to a power supply via the first emitter resistor, and the biasing member is further connected to a second transistor connected in series between the base of the second transistor and the power supply.
a bias transistor and a second emitter resistor, the collector of the second bias transistor is connected to the base of the second transistor, and the collector of the second bias transistor is connected to the base of the second transistor;
The emitter of the bias transistor is connected to the power supply via the second emitter resistor, and the bias member is
A current mode logic circuit including a bias resistor connected between the base of the second transistor and the base of the second transistor.
JP19527082U 1973-06-01 1982-12-24 current mode logic circuit Pending JPS58129751U (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US36608373A 1973-06-01 1973-06-01
US366083 1973-06-01

Publications (1)

Publication Number Publication Date
JPS58129751U true JPS58129751U (en) 1983-09-02

Family

ID=23441599

Family Applications (2)

Application Number Title Priority Date Filing Date
JP5431474A Pending JPS5023166A (en) 1973-06-01 1974-05-15
JP19527082U Pending JPS58129751U (en) 1973-06-01 1982-12-24 current mode logic circuit

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP5431474A Pending JPS5023166A (en) 1973-06-01 1974-05-15

Country Status (6)

Country Link
JP (2) JPS5023166A (en)
BE (1) BE815399A (en)
DE (1) DE2424415C2 (en)
FR (1) FR2232151B1 (en)
GB (1) GB1449727A (en)
NL (1) NL183691C (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5021684A (en) * 1989-11-09 1991-06-04 Intel Corporation Process, supply, temperature compensating CMOS output buffer

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3289092A (en) * 1962-12-31 1966-11-29 Gen Electric Direct-current low voltage regulator utilizing a transistor
US3430155A (en) * 1965-11-29 1969-02-25 Rca Corp Integrated circuit biasing arrangement for supplying vbe bias voltages
US3522446A (en) * 1967-08-31 1970-08-04 Tokyo Shibaura Electric Co Current switching logic circuit
US3573495A (en) * 1968-08-26 1971-04-06 Ibm Threshold circuit apparatus employing input differential amplifier for temperature stabilizing the threshold lenel thereof
US3636384A (en) * 1970-09-14 1972-01-18 Ibm Base-to-emitter compensation for current switch emitter-follower circuits

Also Published As

Publication number Publication date
BE815399A (en) 1974-09-16
JPS5023166A (en) 1975-03-12
GB1449727A (en) 1976-09-15
NL7406701A (en) 1974-12-03
FR2232151B1 (en) 1978-09-15
DE2424415A1 (en) 1974-12-19
NL183691B (en) 1988-07-18
FR2232151A1 (en) 1974-12-27
NL183691C (en) 1988-12-16
DE2424415C2 (en) 1983-04-14

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