JPS58129564A - Interlocking device - Google Patents

Abstract

PURPOSE:To prevent a dead lock, by separating occupancy decision of a start bus which is not used, in case of response and return of memory access, from occupancy deicision of other bus, and occupying only the start bus in case of access of interlock, so that response to other processor can be executed. CONSTITUTION:To start, data and response bus occupancy request lines 51-53, a priority deciding circuit 61 is connected, and the deciding circuit 61 is provided dispersedly in each processor, and an interlock signal line 54 is made a signal of an open collector. In case when an interlock signal is not outputted to this signal line 54, requests on the request lines 51-53 are checked by the circuit 61, and in case when a degree of request of a bus occupancy request which it has outputted is high, an output of the circuit 61 is outputted as a start bus occupancy approval signal through gates 62, 63. Also, in case when an interlock request signal 65 is outputted, an FF66 is set, and the interlock signal is outputted until an interlock releasing signal 67 is outputted. In this way, response to other processor can be executed, and a dead lock is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device in which at least one memory device and a plurality of processors are connected to a common path, and data is transferred between the memory device and the processors via the common path. The present invention relates to an interlock device for interlocking and accessing a memory device.

Multiply Setuna systems that use multiple processors to improve processing performance are emerging. In these systems, rounding and common paths are often used, in which the amount of space increases when separate signal lines are provided to connect a memory device commonly used by each processor and each processor. However, since many processors use a common path and shared memory, if a single processor were to monopolize these resources until the memory access is completed, increasing the number of processors would reduce processing efficiency by 90%. Therefore, the common path in these systems uses split transfer, which separates the activation and response of a memory access and makes it available to other processors, and the shared memory buffers multiple memory accesses. The structure is such that it can be processed in a ring.

In such a system, when a specific processor attempts to occupy a memory device, that is, to perform interlocked reading and writing, the following problem occurs. When interlocking, 'tl
Message activation of other processors that occurs can be prevented by occupying the common path to the @ that cannot be used by that processor, but if this is done, the memory accesses of other processors that are already buffered in the shared memory will be prevented. Since this access was issued before the interlock access, if the interlock access is unable to return a response, the interlock access will also be unable to return a response, leading to a deadlock situation. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an interlock device that does not cause deadlock when a plurality of processors connected via a common path interlock and access a shared memory.

A feature of the present invention is that the occupancy determination of the startup path, which is always used when starting up a common path and is not used when returning a memory access response, is separated from the occupancy determination of other paths, and interlocked access is performed. In some cases, only this startup path is occupied. Hereinafter, the present invention will be explained in detail by way of an example.

An example of an overall configuration diagram of the first WAK system is shown.

The memory device 1, the external memory device 2, the input/output processor 3 (IOP), and the job processor 4 (JOBP) are connected by a common path 5, and information is exchanged between each other via the common path 5. is possible. The memory device 1 is
Memory section 11 (M) for storing programs and data
and a memory control unit 12 (MCU) that controls reading and loading of programs and data, and the memory unit 11 and memory control unit 12 are connected by a memory path 13. The external memory device 2 is composed of an external memory section 21 that stores programs and data to be stored in the memory section 11 in page units, and a file processor 22 (FCP) that is a control section of the external memory section 21. The unit 21 and the file processor 22 are connected by an external memory path 23. The job processor +4 is composed of an instruction cache 41, a data cache 42, a unit 43, and an E unit 1, and is connected by an instruction bus 41 and an instruction bus 411. Data cache 42 and E unit 44 are connected by E unit bus 46. ■Unit 43
The E units 44 and 44 are connected by paths, but these paths are not numbered. Although only one job processor 4 is shown here, it is possible to connect more than one job processor 4. In this way, programs can be issued independently while sharing the memory device 1. The job processor 4, which will be described below, has a pipeline-sensitive layer consisting of a unit 43 and a g-nit 44, and has an instruction middle 41 and a data middle 44 for each object. When the unit 11 accesses the command path, the instruction path is
It is checked whether or not KTo exists, and if it exists, the data is sent to the I unit 43 as an instruction path via the euet path 4S. If it does not exist, the virtual address of the instruction word is sent to the memory control unit 1 via the common path 5.
Send to 2. The memory control unit 12 converts the virtual address into a real address of the memory unit and accesses the memory unit 11. The obtained 9 data are sent via common path 5 to life@rl
? Sent to Yash 41, Samo KI3-sL Foots 4
5 to the instruction unit 43, and is processed by the unit 43 and stored in the instruction cache 41 for viewing. The I unit 43 decodes the obtained nine instructions and reads E.
:L chive) Instructs 44 "what to do." Based on this command, the E unit 44 collects necessary data from internal registers and the data center 42 (if it is not on the data cache 42, from the memory section 11 in the same way as the instruction cache), performs arithmetic processing, and stores the results. It is stored in the internal register xp or t sled section 11. The latter's print part 1
An example of the configuration of the 0th-order common path S will be described in which when storing the result in 1, if the data at the corresponding position has already been taken into the data storage 42, that data is also updated. As shown in Figure I@2, the common path 5 is a startup path 55. which is used for actually transferring information. Data bus 56. Response path 57 and OK necessary boot path occupancy request to determine which processor or memory device will use each of these O paths 55 to 57 @51. Data bus occupancy request line 52. It includes a response path occupancy request line 53 and an interlock signal line 54, and is used in a time-sharing manner. The contents of the information for each path 55 to 57 are as follows: (1) Startup path 55 ・Address ・Type of access (for example, whether it is a read access/write access, how many bytes to access,
etc.) ・Access key (used for protection check performed in MCU12) (2) Data bus 56 ・Write data/read data (3) Response path 57 ・End signal/return code (9 digits generated during access) and page fold information).

# How these paths 55-57 are used
It is shown in Figure I3. In the figure, the 0 mark indicates use. As shown in this figure, 1. Read request in (m) and read response in (b).
It is possible to process three combinations of the read request (d) and the write response (C) and the write response (C) and the write response (d) at the same time in the same time slot. Next pass 55
Figure 4 shows how 57 is used. In this figure, JOBP4 initiates a memory read on MCU12 at time slot 0, and the corresponding read data is returned at time slots N and N+1. , MAKUTAI A S*
At bit 1, 10P3 initiates a memory read to MCU12, and a response is returned at time point 1)N+2. In this manner, the common path 5 separates activation and response, 9, or performs so-called split transfer, and the memory device 1 is configured to be able to process multiple memory accesses.

As described above, before transferring the voltage paths 55 to 57, it is necessary to perform occupancy control.

This is done by the processor or memory device desiring the transfer issuing occupancy requests 51 to S3 for the path used for one transfer before the transfer 01 time suit, giving priority to these requests, and permitting the transfer. There are various ways to prioritize Jin, but we will omit the details here. However, an occupation request made by a response has a higher priority level than an occupation request made by @. This is because if a response cannot be returned due to an exclusive request due to activation, the activation process will become stuck on the memory device, resulting in a deadlock state.1For example, in the case of this example, as shown in the fs3 diagram If the data read response in (b) and the data write start request in (C) conflict, the former takes precedence. So J
OBP4 and l0P3 are attempting to perform read activation, and each has issued a activation path occupation request 51. Of these, JOE
Assuming that IF4 has a higher priority level than 10P3, time slot 1-CJOBP4 uses the activation path 55 to activate the read, and at the same time stops the occupancy request. On the other hand, since occupancy of l0P3 is not permitted, it is assumed that tt issued the activation path occupancy request 51 in time slot 1 as well. In this slot 1, there is no occupancy request from JOBP4, so in time slot 2, l0P3 can be activated for reading.

In such a system, when each processor accesses the memory device 1 by excluding access from other processors, that is, by interlocking, the boot path 55 is
To prevent other processors from using tK, by occupying the startup path 55, future startups from other processors are excluded, and the memory device 1 that is currently processing For startup, the data bus 56. This is to make it possible to return a response using the response path 57. If these responses cannot be returned, the startup process will get stuck on the memory device, resulting in a deadlock situation. . As shown in FIG. 6, a processor that attempts to interlock and access the memory device 1 receives the boot path occupancy request 11 and uses the boot path 55 in the time slot for transferring the boot path 5sK information.
It issues an interlock signal 54 indicating that the processor occupies the boot path i, and this signal prevents it from accepting boot path occupancy requests 51 from other processors. This is achieved, for example, by the circuit shown in Figure 7. In this figure, the priority determination circuit 61 for each of the occupancy requests 51 to b3 is distributed to each processor, and the interlock signal line 54 is an open collector signal line. First, if the ink look signal 54 is not filled, each occupancy request 51 to 53 is checked by the priority judgment circuit 61, and if the priority of the own out-maru activation path occupancy request 51 is one level higher, it is given priority. Judgment circuit 61
An occupancy permission signal 64 for the activation path 55 is outputted through an AND gate 62 and an OR gate 63. Therefore, this processor is able to transfer information to boot path 155 in the next time slot. (9) At this time, if the interlock request signal 65 is issued from the processor, J
The flip-flop 66 is set to -, and the interlock signal 54 is outputted via the gate 68. This interlock signal 54 is issued until the interlock release signal 67 is issued, and during this time this processor is not connected to the startup bus 5.
5t-remains occupied If the interlock signal 54 is issued from another processor, the output of the priority determination circuit 61 is prohibited by the inverter gate 69 and the p-AND gate 62, so that Boot path occupancy permission signal 6
Since 4 is not output, the startup bus 5s is not used and therefore memory startup is not possible.0 or more 011K.

According to the present invention, only the startup path is occupied during the interlock, so no deadlock occurs in which responses from other processors accumulated on the memory device can be returned.

[Brief explanation of the drawing]

Figure 1 is a diagram showing a typical overall configuration of a multiplex gastric system using a common path. Figure 9 shows how it is used, Figure 4 is a meme chart showing how the common path is used, Figure 5 shows the path occupancy determination, and GSS is occupancy determination at interlock. Figure 9 shows 0@child, and Figure 1IT shows an example of an occupancy determination circuit that implements the present invention. 1...Memory device, 3...Input/output coupler, 4.
...Disodic buprosetuna%5...Common pass, 51-・m
dynamic path occupancy request line, 54... interlock signal line, 5
5...Start-up lotus, 56--Data bus, 57...Response path, Figure 1 Male Figure 3 Yi! 5 Figure 6 q Continuation of figure 1 page 0 Author: Toshiyuki Ide 5-2-1, Hitachi University, Mika-cho Inside Omika Factory, Hitachi, Ltd. Applicant: Hitachi Engineering Co., Ltd., 3-chome, Saiwai-cho, Hitachi City 2 number 1

Claims (1)

[Claims] 1. At least one memory device and multiple processors are connected via a common path, data is transferred between the memory device and the processors via the common path, and the memory device processes activation of multiple memory devices. In a data processing system that is designed to perform Data transfer from the memory device to the processor uses a response path and a data bus, and when the processor interlocks and accesses the memory device, only the scissors activation path is occupied. .