JPS59125465A - Multi-processor system - Google Patents

Abstract

PURPOSE:To shorten the waiting time due to the bus conflict by giving an access to a shared memory after switching and selecting successively the buses in accordance with the address value. CONSTITUTION:Buses B1-Bn are connected to a shared memory M. The region of the memory M is divided into regions M0-Mn-1, and the buses B1-Bn are connected to these regions respectively. Then CPU blocks CB0-CBn-1 are connected to the buses B1-Bn. These CPU blocks switch and select successively the buses B1-Bn in accordance with the value of the address which gives an access to the memory M.

Description

Detailed Description of the Invention (a1 Technical field of the invention)
The present invention relates to a multiprocessor system having (processors), and more particularly relates to a hash system in a multiprocessor system that shares main memory memory.

fblPrior art and its problems Figure 1 shows a multiprocessor system in which memory is shared by multiple CPUs.
CPU n and shared memory 1 are connected to one lotus B.

In such a system, as shown in FIG. 2, it is assumed that access to the shared memory M starts at time 1 when CPU i is running, and ends at time L3. Then, even if another CPU j tries to access shared memory M at time t2, since path B is used by CPU i, CPU j cannot access shared memory M until time t3, when the access operation by CPU 1 ends. have to wait. From L3 to t1, CPUj dedicates lotus B. In this way, while a certain CPU is using bus B, other CPIJs cannot access the shared memory, and by waiting for bus B to become free during tz=tx, the processing power decreases accordingly. The advantages of multiprocessor systems are lost.

(C) Purpose of the Invention The present invention aims to eliminate such problems in conventional multiprocessor systems that share memory, and to minimize the waiting time when shared memory access conflicts. purpose.

(d1 Structure of the Invention To achieve this object, the present invention uses a plurality of lotuses in a multiprocessor system in which memory is shared by a plurality of CPUs, allocates a shared memory area to each lotus, and assigns a shared memory area to each lotus. ``The U block is provided with means for selecting a lotus based on the value of the address for accessing the memory, between each lotus.

(Example of the e+ invention) Next, how the multiprocessor system according to the invention is actually implemented will be explained using an example. FIG. 3 is a block diagram showing the entire structure of the multiprocessor system. It is configured to be included in a CPU block equipped with a lot selection section and the like, and has n and 4 of 1 to Bn, each of which is connected to a shared memory M. The memory area of the shared memory M is divided into 0=n-+, and the lotuses B1 to Bn are connected to each memory area @Mo-Mn-+. and cpu block C
Bo -CBm-+ is connected to total tenohas B1-Bn.

FIG. 4 is a block diagram showing the configuration of one cPU block. The CPU is connected to the shared memory M via a system lot consisting of lotuses B1 to Bn, but also includes a dedicated local memory 1. CPII is connected by a data bus/control bus 2 to local memory IJ1 and each bus arbiter A1-An. address bus 3
is connected to the local memo 1 and decoder input, and is also connected to each of the hash arbiters A1 to An through the divider 4. Further, the divider 4 is connected to a decoder D2, and the decoder D+ is also connected to the decoder D2.

When memory is accessed from CP[I, the
-Res is decoded by the decoder DI to determine whether the local memory 1 or both are the memory M, and if the shared memory M is being accessed, the selection of 1ζ has is performed as follows. That is, a shared memory selection signal is input from decoder D1 to decoder D2, and the address value is divided by divider 4. Then, the remainder value is input to the decoder D2, and the quotient is transferred to the address bus 3' from the hash arbiter A1 to Δ
Enter n. The decoder D2 selects one of the system lots B1 to Bn according to the input remainder value.

If the remainder is 0, the lotus B1 is selected and connected to the memory area Mo, and the address bus 3'' is connected to the shared memory M.
Arres of O is specified and If the remainder is 1, lotus B2 is selected and connected to memory area M1,
An address is designated from 71 "res has 3". In this way, the value of the address is divided, the address bus is selected by the remainder, and the address is designated by the value of the quotient.

FIG. 5 is a time chart showing the usage status of each bus B1 to Bn when the shared memory M is shared in this way, in the case where there are four buses.

Now, when CPU i accesses shared memory M, according to the result of the above division, hash T3 I= B 2 =
B3-=B+=B1... are selected in this order. In other words, since access to memory generally spans consecutive addresses, in order to allocate multiple sets of lotuses, if decoding is performed using the remainder of the address value as described above, lotuses B1...B4 can be sequentially arranged in cycles. selected. Therefore, looking at lotus BI, while lotus B1 is selected, it competes with other CPUs, but other lotuses B2 to B4 are selected, and between 2 and L5, other CPUs are in use. can. Other CPII j is same lotus B1
If , the shared memory M is accessed via the hash B+ between t2 and t5. Similarly, CPU
CPLI i and CPUs other than CPUj
During free time not selected by CPII j, the same lotus B+ can be shared and the shared memory M can be accessed. All of the other lotuses B2 to B4 (similarly,
The bus is selected in a time-sharing manner and the shared memory M is accessed.

Now, since the same address area is accessed from two CIs) 11, for example, in lotus B1, CPL
Even if I i and C, PU j conflict and CPU i preferentially selects bus B1, CI'U i will soon select the next bus Bl and release bus B1, so that CPU
Uj only needs to wait between t1 and L2, and the waiting time is significantly reduced compared to the conventional one-pass method.

if) Effects of the Invention According to the present invention, when a memory is shared by a plurality of ct'u, multiple sets of busses are provided, the bus is sequentially switched and selected according to the value of the bus, and the shared memory is A method of accessing the information is adopted. Therefore, even if the same address is accessed by multiple CPUs, the same lot will soon be released and another Cl1o, 6<< can be selected, reducing the waiting time caused by lotus contention and speeding up processing. Capabilities will be improved.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional 1-hass method multiprocessor system, and Figure 2 is a time chart showing the shared memory access status in the same system. FIG. 4 is a block diagram showing an embodiment of one CI]tl block, and FIG. 5 is a time chart 1 which does not show the access state of the shared memory according to the method of the present invention. In the figure -(, M is shared memory, Mθ~Mn-1 is memory area, B+=Bn hash, CB[噸~CBm-1 is c
In the pu block, D+ and D+ are decokes, 4 is a divider, and A1 to An are hash arbiters, respectively.

Claims (1)

[Claims] In a multiprocessor system in which memory is shared by a plurality of CP[+], a plurality of sets of busses are used to allocate a shared memory area to each bus, and each CPIJ block has its own path and 1. A multiprocessor system, comprising: means for selecting an address based on the value of an address at which memory is to be accessed during the processing.