JPS58127895U - Motor speed control device - Google Patents
Motor speed control deviceInfo
- Publication number
- JPS58127895U JPS58127895U JP1982122473U JP12247382U JPS58127895U JP S58127895 U JPS58127895 U JP S58127895U JP 1982122473 U JP1982122473 U JP 1982122473U JP 12247382 U JP12247382 U JP 12247382U JP S58127895 U JPS58127895 U JP S58127895U
- Authority
- JP
- Japan
- Prior art keywords
- motor
- control device
- speed control
- output
- motor speed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Electric Motors In General (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のＰＬＬを用いたモータの速度制御装置の
回路系統図、第２図は本考案の実施例を示す回路系統図
である。
なお図面に用いられている符号において、２は位相比較
器、３はループフィルタ、４はサーボアンプ、５は被制
御モータ、７はプログラマブルカウンタ、８は速度切換
えスイッチ、９はデコーダである。FIG. 1 is a circuit diagram of a motor speed control device using a conventional PLL, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. In the reference numerals used in the drawings, 2 is a phase comparator, 3 is a loop filter, 4 is a servo amplifier, 5 is a controlled motor, 7 is a programmable counter, 8 is a speed changeover switch, and 9 is a decoder.
Claims (1)
の検出器の出力を分周するプログラマブルカウンタと、
基準発振器と、上記カウンタ及び、・ 上記基準発振
器の両方の出力が供給される位相比較器と、この位相比
較器の出力が供給されるループフィルタと、このループ
フィルタの出力が供給されて上記モータの速度を制御す
るサーボアンプとを夫々具備するＰＬＬを用いたモータ
の速度制御装置において、上記プログラマブルカウンタ
の分周比をデコードしてこの分周比に応じた出力電圧を
発生するデコーダを設け、この出力電圧により上記サー
ボアンプ、上記位相比較器及び上記ループフィルタのう
ち少くとも１つの利得を制御するように構成し、これに
よって、上記ＰＬＬのループ利得が上記分周比に拘らず
一定となるようにしたことを特徴とするモータの速度制
御装置。A motor, a detector that detects the rotation speed of this motor, and a programmable counter that divides the output of this detector.
a reference oscillator, the counter, and a phase comparator to which the outputs of both the reference oscillators are supplied, a loop filter to which the output of the phase comparator is supplied, and an output of the loop filter to which the motor is supplied. A motor speed control device using a PLL, which includes a servo amplifier for controlling the speed of the programmable counter, and a decoder that decodes the frequency division ratio of the programmable counter and generates an output voltage according to the frequency division ratio, The output voltage is configured to control the gain of at least one of the servo amplifier, the phase comparator, and the loop filter, so that the loop gain of the PLL is constant regardless of the frequency division ratio. A motor speed control device characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982122473U JPS58127895U (en) | 1982-08-12 | 1982-08-12 | Motor speed control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982122473U JPS58127895U (en) | 1982-08-12 | 1982-08-12 | Motor speed control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58127895U true JPS58127895U (en) | 1983-08-30 |
Family
ID=30101316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1982122473U Pending JPS58127895U (en) | 1982-08-12 | 1982-08-12 | Motor speed control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58127895U (en) |
-
1982
- 1982-08-12 JP JP1982122473U patent/JPS58127895U/en active Pending
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