JPS58127445A - Error correction system - Google Patents

Abstract

PURPOSE:To reduce the memory capacity used as a table, by obtaining the syndrome at each block from a plurality of partial syndromes obtained from a plurality of tables and correcting errors of information. CONSTITUTION:A shift register 2 shifts information from a terminal 1 with a clock pulse applied from a clock generator 4 and supplies it to a latch circuit 5. A synchronizing detector 3 detects the synchronism of the block and supplies the result to a reset terminal of a counter 6. The counter 6 divides in terms of frequency the clock pulse grom the generator 4 and supplies it to the latch circuit 5. The latch circuit holds the bits in one block applied from the shift register 2 every time the pulse is applied from the counter 6. Tables 8 and 9 formed in a memory 7 are indexed with high-order and low-order bits, respectively. The two partial syndromes thus obtained are inputted to an exclusive logical sum circuit for calculation, allowing to obtain the syndrome.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction method, and by cooling syndromes for each block from partial syndromes obtained from N tables, the memory capacity used for the table is reduced, and it is possible to The purpose of this invention is to provide an error correction method with short processing time.

Conventionally, when the information to be transmitted is error-correctable, such as a Hamming code, the necessary bits are extracted from each block of the transmitted information and arithmetic operations are performed to correct the error bits. Generating a syndrome for this requires a large amount of processing time. Furthermore, if this syndrome is generated using hard logic, the processing time will be very short, but the circuit will be complex and enormous. For this reason, there has conventionally been a method of generating syndromes for all cases in which each bit of one block is involved, creating a table, and searching this table (table lookup) to shorten the processing time.

FIG. 1 shows the structure of an example of a Hamming code of 1 block of 16 bits. In the figure, if MSB is bit b181L8B is bit b1, bits b1 to b11 are data bits, bits b12 to b are check bits, and bit bIll is a parity bit. The syndromes S, .about.S6 of this Hamming code are created by the following equation 1.

s, = b1ob3o+b, o+b7■b80+b1o
O+b11e) b12・-...+1)82=b, (i
) b2eb, e) b, O+b, (i) b, (E) bl,
■b, 3...-(2) s3=b, ■b2Φb3■b
4■b8Φb, ■bXo■b, 4-...(31s,
= b1o+b, ■b, o+ b4Φb5Φb, o+ b
, Φb1. −・−+41s, = b, orb
,o,@)4o,w,eb,o,tb,o,. el,s
l, o, 3o, 4o, s16... (5) Here, ■ indicates addition of modulo-2.

In the conventional method described above, syndromes 81 to S5 are generated for all cases in which each bit b1 to b118 of one block are handled using equations (1) to (5), and the syndromes 81 to S5 are stored in the memory.
Create a table as shown in the figure. bit b of this table
A portion I corresponding to □ to b16 is a memory address, and a syndrome S□ to S generated from bits b and ˜b1+8 is stored in a portion □.

Here, "-" in part n is an unused bit.

Here, each block of transmitted information uses the bits b1 to b1□ constituting each block as addresses to look up the table shown in the second figure, read out the syndromes 81 to S corresponding to each block, and read out the syndromes 81 to S corresponding to each block. Bits b1 to b16 forming a block by Syo~Sll
If multiple errors or 1-bit errors in the block are detected and it is known which bit the error bit is among bits b1 to b16 (in the case of a 1-bit error, all the error bits are known), the error bit in the block is detected. The transmitted information is output after being corrected. In this conventional method, syndromes 81-S,
Although the time required to find the values is greatly shortened and high-speed error correction is possible, the difference between b) b□ and b1. (7) A table corresponding to all 16 bit values is required, and this table will occupy 64 bytes (64 = 2") of memory capacity. For this reason, this error correction method can be When used in a general television receiver that receives broadcasts, it has the disadvantage that it is impossible to exclusively use the large capacity of 64 bytes for error correction.

The present invention eliminates the above-mentioned drawbacks, and one embodiment thereof will be described with reference to FIG. 3 and the following figures.

FIG. 3 shows a block diagram of one embodiment of the error correction system according to the present invention. In the figure, l is an input terminal through which transmitted information is input, and the input information is supplied to a shift register 2 and a synchronization detector 3. Shift register 2 is 16
It has a bit configuration, and the information from the input terminal 1 is shifted by a clock pulse supplied from the clock generator 4, and the stored contents of each of the 16 bits are constantly supplied to the corresponding bit of the latch circuit 5 having a 16e configuration. ing.

Further, the synchronization detector 3 detects the synchronization of the blocks forming the information from the input terminal 1 and supplies this to the reset terminal of the counter 6. After being reset, the counter 6 counts clock pulses from the clock generator 4 and supplies the latch circuit 5 with pulses obtained by dividing the clock pulses by 1/16. The latch circuit 5 stores and holds one block of bits b1 to b16 supplied from the shift register 2 every time a pulse is supplied from the counter 6. Also,
The latch circuit 5 has the upper 8 bits (bits b, -b,).

It is divided into lower 8 bits (bits b1 to b8),
A table 8.9 created in the memory 7 is searched using the upper 8 bits and lower 8 bits.

Here, equations (1) to (5) are divided as shown below.

51a=b1oΦbo■b,, -=-(la)s
2a= b, ■b11■b13...(2a) s3
a=b, eb□. ■bt4==...(3a) S<a=
bss ・-・(4a)s, = b, e
b□. ■b1□eb1□■b18■b14■bxs■b
,6. , , , (5a) S□1. : b 1 ■
b30b, ■b7Φb8... (1b) s2.
= b□Φb2■b50b6■b8... (
2b) S3b=b1■b2Φb, ■b4Φb8...
・・・ (3b)s =b■b■bΦb orb Ob
■b... (4b)4b 1 2 3
4 6 6 7Ssb = bleb2eb3
Φb4Φb, orb, ■b, o+b, ・-・(5b
)Sn=Sna■8. b (n is 1, 2, 3, 4.5) -
--(6) As shown in equation (6), the entire syndrome (bits b0 to b16) is obtained from the partial syndrome based on the upper 8 bits and the partial syndrome based on the lower 8 bits.

As shown in FIG. 4 (5), Table 8 uses the upper 8 bits (bits b, ~b1.) as an address, and the bits b,
~b16, partial syndrome 51a-8IIa generated using equations (1a) to (5a) is stored.

Table 9 also uses the lower 8 bits (bits b1 to b8) as an address, as shown in FIG.
Partial syndrome S1.1 generated using equations (tb) to (5b) from 1 to b8. ~・S5. is memorized.

Table 8 shows, for example, the latch circuit 5 from bit b16 to 11C to bit b1 rollollool 011
When 11001J is stored, the top 8 pins) r
The partial syndrome obtained by searching ololloolJ as an address [---01101J is supplied to one input terminal of the exclusive OR circuit 10, and table 9 is similarly searched using the lower 8 bits r01111001J as an address. Partial syndrome r---1 obtained by
1011J is supplied to the other input terminal of the exclusive OR circuit 10. The exclusive OR circuit 10 is a partial syndrome S
1a −Ssa, 5tt) ~Sab (6)
Perform calculations on the formula and create syndrome SX~8. get. In the above example, including the unused 3 bits, the syndrome S is obtained, and then r---10110J is obtained at the age of 81, and this obtained syndrome [---xolloJ is the determination circuit 1
1, where the error bit (in this case bit b,
) is set to 1 (in this case, the MSB
roooo 0001000000 up to LSB
00J) is generated and supplied to the correction circuit 12. The correction circuit 12 performs correction by calculating the exclusive OR of the corresponding bits of this correction bit string and bits b1 to bIII of one block supplied from the shift register 5 (in this case, the corrected information is LS in order from MSB
rolol 100001111001J) is output from the output terminal 13.

In this way, each table 8.9 has 256 bytes (256 bytes).
=2'), each award of the memory 7 used by both is 512 bytes, which requires only 1/128th of the memory capacity of the conventional 64 bytes.

In addition, in the same way as above, the table is divided into four parts and bit b
~b, b ~bb ~b, b ~ta
tm tt ・ 1
8 5 If you create a partial syndrome for each of 4b1 and calculate the exclusive OR of the partial syndromes of the 4 buildings, the memory capacity will be 64 bytes (64 =
2'+2'+24+24) is fine. However, since it takes a long time to request Syndrome 81-Sg,
The number of table divisions is determined depending on the required processing speed and the allowable memory capacity 1, and is not limited to the two divisions of tables 8 and 9 as in the above embodiments.

Note that shift register 2. The latch circuit 5 has an 8-bit configuration, and the counter 6 is set to octal, and the circuit is time-divided so that the lower 8 bits are used to first look up the table 9, and then the upper 8 bits that are supplied are turned off to look up the table 8. However, the present invention is not limited to the above embodiments.

As described above, the error correction method according to the present invention transmits encoded information for each block in an error-correctable format,
In an error correction method that corrects errors for each block of information, the block is divided into N parts (N is a positive integer), and the bit strings that make up each part are addresses and the partial syndromes generated by the bit strings are stored. Since the syndrome for each block is calculated from the N partial syndromes obtained from the N tables and error correction is performed on the information, the memory capacity used for the table is small and the logic is complicated. It does not require any calculations and can be processed satisfactorily by a low-level microcomputer, etc., and the processing time is short.Furthermore, even when changing the bit arrangement during encoding or changing the parity check matrix, it is only necessary to change the stored contents of the table. It has the advantage of being easily adaptable.

[Brief explanation of drawings]

Fig. 1 is a diagram schematically showing one block of information, Fig. 2 is a diagram schematically showing an example of a conventional table configuration, and Fig. 3 is a block system diagram of an embodiment of the system of the present invention. Figure 4 (5)
, (B) is a diagram schematically showing the table configuration shown in the third figure. 1...Input terminal, 2...Shift register, 4.Fist
Clock generator, 5... Latch circuit, 7... Working memory, 8, 9... Table, 10... Exclusive OR circuit, 11... Fist judgment circuit, 12... Correction circuit, 13 fist·
・Output terminal.

Claims (1)

[Claims] In an error correction method in which information encoded in each block is transmitted in an error-correctable format and the error is corrected for each block, the block is divided into N (N is a positive number of ships).
The bit string that constitutes each part is divided into N parts, and N tables are stored in which the partial syndromes generated by the bit string are stored at addresses, and the N partial syndromes obtained from the N tables are An error correction method whose distinguishing feature is to find the syndrome for each block and perform error correction on the information.