JPS58125161A - マルチ計算機装置 - Google Patents

マルチ計算機装置

Info

Publication number
JPS58125161A
JPS58125161A JP754782A JP754782A JPS58125161A JP S58125161 A JPS58125161 A JP S58125161A JP 754782 A JP754782 A JP 754782A JP 754782 A JP754782 A JP 754782A JP S58125161 A JPS58125161 A JP S58125161A
Authority
JP
Japan
Prior art keywords
data
input
output
central processing
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP754782A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6327740B2 (enrdf_load_stackoverflow
Inventor
Tetsuo Shishido
宍道　徹夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Information and Control Systems Inc
Original Assignee
Hitachi Ltd
Hitachi Control Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Control Systems Inc filed Critical Hitachi Ltd
Priority to JP754782A priority Critical patent/JPS58125161A/ja
Publication of JPS58125161A publication Critical patent/JPS58125161A/ja
Publication of JPS6327740B2 publication Critical patent/JPS6327740B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP754782A 1982-01-22 1982-01-22 マルチ計算機装置 Granted JPS58125161A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP754782A JPS58125161A (ja) 1982-01-22 1982-01-22 マルチ計算機装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP754782A JPS58125161A (ja) 1982-01-22 1982-01-22 マルチ計算機装置

Publications (2)

Publication Number Publication Date
JPS58125161A true JPS58125161A (ja) 1983-07-26
JPS6327740B2 JPS6327740B2 (enrdf_load_stackoverflow) 1988-06-06

Family

ID=11668813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP754782A Granted JPS58125161A (ja) 1982-01-22 1982-01-22 マルチ計算機装置

Country Status (1)

Country Link
JP (1) JPS58125161A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4757441A (en) * 1985-02-28 1988-07-12 International Business Machines Corporation Logical arrangement for controlling use of different system displays by main proessor and coprocessor
US4833596A (en) * 1985-02-28 1989-05-23 International Business Machines Corporation Logical arrangement for controlling use of different system displays by main processor and co-processor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56159759A (en) * 1980-05-13 1981-12-09 Omron Tateisi Electronics Co Selecting method for input and output equipment of multiple computer system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56159759A (en) * 1980-05-13 1981-12-09 Omron Tateisi Electronics Co Selecting method for input and output equipment of multiple computer system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4757441A (en) * 1985-02-28 1988-07-12 International Business Machines Corporation Logical arrangement for controlling use of different system displays by main proessor and coprocessor
US4833596A (en) * 1985-02-28 1989-05-23 International Business Machines Corporation Logical arrangement for controlling use of different system displays by main processor and co-processor

Also Published As

Publication number Publication date
JPS6327740B2 (enrdf_load_stackoverflow) 1988-06-06

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