JPS58123224A - Monostable multivibrator - Google Patents

Abstract

PURPOSE:To prevent chattering from occurring at the trailing part of an output delay pulse even if a DC voltage from a DC power source has a fine noise component by changing reference voltage sources according to an output signal. CONSTITUTION:Transistors (TR) Q24 and Q25 constitute a differential amplifier; the time constant circuit of a resistance R25 and a capacitor C21 is connected to the base of the TRQ24 and the reference voltage generating circuit consisting of resistances R28 and R29 is connected to the base of the TRQ25. Further, a TR which turns on when an input is present is connected to the capacitor C21 and a similar TRQ26 is connected to the resistance R29. A TRQ27 is an output TR, whose collector output is connected to the base of a TRQ22 provided in parallel to an input TRQ21 to provide feedback. The circuit of a diode D21 and a resistance R32 operates at the trailing edge of the output pulse to prevent chattering.

Description

[Detailed description of the invention] The present invention also relates to monostable multivibrator page 2 It is.

A conventional monostable multivibrator has the configuration shown in FIG.

That is, in FIG. 1, transistors Q1 and Q2 and resistor R2 constitute a NOR gate, and transistor Q
3. Each Q6 constitutes a pulse amplification circuit. Resistance R
6 and capacitor C1 constitute a time setting circuit, and resistors R8 and R9 constitute a reference voltage source. Further, a transistor QQ and resistors R6 and R7 constitute a 4/6 differential amplifier, which is used as a comparison circuit. The transistor Q7 and the resistor R11 constitute a detection circuit.

Note that the resistors R1, R3, R4, and R1° are resistors for limiting the current.

The operation of the conventional example configured in this way will be explained.

First, the operation when the time constant of the gap setting circuit is selected so that the pulse time width t2 of the output delayed pulse is longer than the pulse time width t1 of the input pulse will be described with reference to FIGS. 1 and 2.

First, the input signal a applied to the input terminal 1 turns on the three-page transistor Q1, and the voltage at point B in FIG. 1 becomes a low level (hereinafter referred to as L level) as shown in FIG. Become. Transistor ~3°Q6 is then turned off. Since the transistor Q3 is turned off, charging of the capacitor C1 from the DC voltage source via the resistor R6 is started. Also, since transistor Q6 is turned off,
The base voltage of the transistor Q6 is a reference voltage VB (VB is a voltage obtained by dividing the power supply voltage Vcc by resistors R8 and R9). Here, the pulse time width t2 of the output delay pulse f is
Since the time constant of the time setting circuit is selected to be longer than the pulse time width t1 of the input pulse a, during the period when the input signal is at H level, the base voltage of the transistor Q5 is longer than the base voltage of the transistor Q4. transistor Q
4 is in an off state, and transistor Q6 is in an on state. When the transistor Q5 is in the off state, the voltage at point 8 in Fig. 1 becomes L level as shown in Fig. 2 e, and the transistor Q7 becomes in the on state, and the voltage at the output terminal 2 becomes low as shown in Fig. 2 e. It becomes H level as shown in 1 f.

Next, the input transistor Q1 is turned off, but since the base voltage of the transistor Q2 is at the H level, the voltage at point E in FIG. 1 remains at the L level as shown in FIG. 2 e.

Then, when the voltage of the capacitor C1 becomes VB as shown in FIG. 2C, the transistor Q4 turns on.
Transistor Q6 is turned off.

When transistor Q5 turns off, transistor Q
7 is turned off, the voltage at the output terminal 2 becomes L level. Therefore, the time width of the signal f output from the output terminal 2 is larger than the time width of the input pulse, as shown in FIG. 2f.

Note that the pulse time width t2 of the output delay pulse is t2=R-
CII IVcc/(Vcc-VB)2i.

1n Next, the time constant of the time setting circuit is set so that the pulse time width t2 of the output delay pulse f output from the output terminal 2 is shorter than the pulse time width t of the input pulse a applied to the input terminal 1. The behavior when you select “.

This will be explained using FIGS. 1 and 3.

First, when the input signal applied to the input terminal 1 becomes H-ray 6:', the transistor Q1 is turned on, and the collector of the transistor Q1 becomes L level. Therefore, transistor Q3. Q6 are respectively turned off.

Since the transistor Q3 is in the off state, charging of the capacitor C1 starts from the DC voltage source via the resistor R6. If the input signal remains at H level, capacitor C
1 rises to the voltage Vcc of the DC voltage source. Furthermore, since the transistor Q6 is in the off state, the base voltage of the transistor Q6 becomes the reference voltage VB.

Next, as shown in FIG. 3A, when the input signal changes from H level to L level, transistor o1i becomes off, and transistor Q3. Q6 is turned on. When the transistor Q3 is turned on, the discharge current of the capacitor C1 flows through the collector of the transistor Q. Therefore, the voltage waveform at the connection point C between the resistor R6 and the capacitor C becomes a waveform as shown in FIG. 3C. Also transistor Q6
When in the on state, the level of the collector of the transistor Q6 becomes 7) EL6 level, so the voltage in Figure 1 becomes VB only during the period when the input signal is at H level, as shown in Figure 3d. here,
During the period from time to when the input signal becomes H level to time ta when the voltage of capacitor C1 becomes VB, transistor Q4 is in an off state because the base voltage of transistor Q5 is higher than the base voltage of transistor Q4. Transistor Q6 is turned on. While the transistor Q6 is in the OFF state, the collector of the transistor Q6 is at the low level.
level and transistor Q7 turns on, so
The voltages at point E in FIG. 1 and the output terminal 2 are as shown in FIG. 3 e and f. Therefore, the pulse time width t2 of the output delay pulse output from the output terminal 2 is t2-ta-
to, t2=R5・C1・Q n l V c
c/(Vca-VB)l. However, in general, there is no perfect DC voltage source, and there is a small random noise component. In particular, in a DC voltage source that uses a switching regulator, the carrier wave component (!5!/10 KHz component) of the switching regulator inevitably remains. Therefore, since the reference voltage source VB always has a noise component on it, if the pulse time width t2 of the output delayed pulse is shorter than the pulse time width t1 of the input pulse as shown in FIG. When the base voltage of transistor Q4 and the base voltage of transistor Q6 are compared around time 1a when

Because the transistor Q6 repeats on and off states several times due to the noise component of the reference voltage VB, the falling portion of the output delay pulse at the output terminal 2 causes chattering several times. There is a drawback.

The present invention provides a monostable multivibrator that can be easily integrated into an integrated circuit, and aims to solve the drawbacks of the conventional example. An embodiment of the present invention is shown in FIG. 4 below.

In FIG. 4, transistor 021. Q22 and resistor R22 constitute a NOR gate, and transistor Q23
．． Each Q26 constitutes a pulse amplification circuit. Resistance R
2, and condensation? Configure the time setting circuit with C21,
The resistors R28P and R29 constitute a first reference voltage source.

Also, transistor Q24IQ25 and resistor R26t
A differential amplifier is configured with R2□, and this is used as a comparison circuit. Transistor Q27. and resistor '31 constitute a detection circuit. A second reference voltage source is configured by connecting the diode D21 and the resistor R32 to the first reference voltage source.

Note that the resistor R21t''231R24*R30 is a resistor for limiting the current.

The operation of this embodiment configured as above will be explained. In FIGS. 5 and 6, a to f indicate voltage waveforms at points A to F shown in FIG. 4.

First, the operation when the time constant of the time setting circuit is selected so that the pulse time width t2 of the output delayed pulse is longer than the pulse time width t1 of the input pulse will be described with reference to FIGS. 4 and 5.

First, when the input signal applied to the input terminal 1 becomes H level, the transistor Q21 turns on, and the voltage at point B in FIG. 4 becomes L level as shown in FIG. The transistor 023tQ26 is then turned off. Since the transistor Q23 is turned off, charging of the capacitor C21 from the DC voltage source via the resistor R25 is started. Also, since the transistor Q26 is turned off, the base voltage of the transistor Q25 is the reference voltage vBH.
(vBH is the voltage obtained by dividing Vcc by resistor R2B*R29). Here, the pulse time width t of the output delay pulse
Since the time constant of the time setting circuit is selected so that 1 is longer than the pulse time width t2 of the input pulse, the input signal is H.
During the level period, the base voltage of transistor Q25 is higher than the base voltage of transistor Q24, transistor Q24 is in an off state, and transistor Q5 is in an on state. Since the transistor Q25 is in the on state, the voltage at point E in FIG. 4 is at the L level, the transistor Q2□ is in the on state, and the voltage at the output terminal 2 is at the H level.

Therefore, diode D21 becomes reverse biased and non-conductive, and the base voltage of transistor Q25 becomes reference voltage vBH. Next, when the input level falls from the H level to the L level, the transistor Q21 is turned off, but since the base voltage 0 of the transistor Q22 is at the H level, the voltage at point E in Figure 4 is as shown in Figure 6. It remains at L level like E. and capacitor C21
When the voltage of transistor Q2. becomes VBH as shown in FIG.
is in the off state. When the transistor Q25 is turned off, the transistor Q2□ is turned off, so that the voltage at the output terminal 2 becomes L level. Therefore, the time width of the signal output from the output terminal 2 is larger than the time width of the input pulse, as shown in FIG. 6f. In addition, the pulse width t2 of the output delayed pulse is t2=R26,C211n(Vcg4VC
c-VB) becomes 1.

Next, the operation when the time constant of the time setting circuit is selected so that the pulse time width t2 of the output delay pulse output from the output terminal 2 is shorter than the pulse time width t1 of the input pulse applied to the input terminal 1. will be explained using FIGS. 4 and 6. First, when the input signal applied to input terminal 1 becomes H level, transistor Q21 is turned on, and the collector of transistor Q21 becomes L level. Therefore, 11 transistors Q23IQ26 are each turned off. Since the transistor Q23 is in the off state, charging of the capacitor C21 from the DC voltage source via the resistor R26 is started. If the input signal remains at H level, the voltage of capacitor C21 rises to the voltage Vcc of the DC voltage source.

Further, since the transistor Q26 is in the off state, the base voltage of the transistor Q25 becomes the reference voltage ②BH. Next, as shown in FIG. 6a, when the input signal changes from H level to L level, transistor Q21 turns off.
Transistor Q231Q28 is turned off.

When transistor Q23 turns on, transistor Q
The discharge current of the capacitor C1 flows through the collector of the capacitor C1. Therefore, the voltage waveform at the connection point C between the resistor R25 and the capacitor C21 becomes a waveform as shown in FIG. 6C. Further, when the transistor Q26 is turned on, the level of the collector of the transistor Q26 becomes L level. Here, during the period from time t0 when the input signal becomes H level to time t when the voltage of capacitor C21 becomes VBH, transistor Q24 is turned off because the base voltage of transistor Q25 is higher than the base voltage of transistor Q24. state, transistor Q25 is in the on state. Then, during the period when transistor Q25 is in the on state, transistor Q
Since the collector of 25 is at L level and the 9 transistor Q2□ is turned on, the voltage at point E in FIG. 4 and the output terminal 2 becomes as shown in e and f in FIG. 6. Furthermore, during the period from time ta to the fall of the input pulse applied to input terminal 1, the base voltage of transistor Q25 is lower than the base voltage of transistor Q24, so transistor Q26 is turned off and the collector of transistor Q26 is at H level. Since the transistor Q2□ is turned off, the collector of the transistor Q2□ becomes L level.

During this period, transistor Q26 is in an off state.

Among the voltages at point D and points □, 1...'F in FIG. 4, point D has a higher level, so diode D21 becomes conductive.

Pace voltage taste of y transistor Q26 from VBH to vBL (
Since resistor R32 is connected in parallel to R29, vB is lower than vBkl.
The voltage at the fourth plot point becomes as shown in FIG. 6d.

According to the present invention described above, even if a minute noise component is added to the DC voltage source by switching the reference voltage source based on the output signal, no chattering occurs at the falling edge of the output delay noxle. This has the advantage that it is easy to integrate the circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a conventional monostable multivibrator, FIGS. 2 and 3 are diagrams showing voltage waveforms at points OA to F in FIG. 1, respectively, and FIG. 4 is a circuit diagram showing an example of a conventional monostable multivibrator. The circuit diagrams of the multivibrator in the embodiment, FIGS. 5 and 6, are diagrams showing voltage waveforms at points OA to F in FIG. 4. 1...Input terminal, 2...Output terminal. Name of agent: Patent attorney Toshio Nakao and one other person 2 Figure 3 Figure t. Figure 5 Figure 6 JO 111

Claims (1)

[Claims] a NOR gate having an input signal applied to a first input terminal; a first .NOR gate connected to the output terminal of the NOR gate; Second
a pulse amplification circuit, a time setting circuit connected to the first pulse amplification circuit, and a first reference voltage source connected to the output signal of the time setting circuit and the second pulse amplification circuit. or a comparison circuit that compares the output of the second reference voltage source and a detection circuit that detects the output of the comparison circuit, and the output of the detection circuit is applied to the second input terminal of the NOR gate. A monostable multivibrator characterized in that the first reference voltage source is switched to the second voltage source by the output of the detection circuit, and an output signal is obtained from the output terminal of the detection circuit.