JPS58115808A - Method of producing laminated porcelain condenser - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a multilayer imager capacitor that eliminates warpage.

(2) Background of the technology Multilayer image capacitors are hand-shaped, large-capacity ceramic capacitors that are directly stored on a hybrid substrate, and have a protruding electrode structure that causes them to collapse. It is also said that

Figure 1 is a cross-sectional view of a multilayer imager capacitor, and a front view thereof, in which a dielectric layer 3 with an electrode pattern 2 screen-printed on the lower dummy dielectric layer l is shown. The electrodes are laminated with a protruding structure, and an upper dummy dielectric layer 4 having the same thickness as the lower dummy electric layer 1 is provided at the top, and a terminal electrode 5 is coated with conductive paint on the lower side.
is provided.

In a capacitor with such an electrode protruding structure, as shown in Figure 1, the effective part is the overlap between the upper electrode pattern 2' and the lower electrode pattern 2, which are present with the dielectric layer 3 in between. It works as a 41 area electric current. mosquito\
The laminated imager capacitor (capacitor) is 7
Cutting a raw sheet (green sheet) formed into an F shape according to the electrode pattern using force or a machine and firing it.
It is created from this, but there are two ways to make a raw sheet.

1. Laminate the required number of thin sheets with electrode patterns printed on them while aligning them, and press them together to form a chemical compound.
What to do.

2. A chemical sort is created by forming not only the electrode pattern but also the dielectric layer by screen printing.

The present invention relates to a step capacitor made by the latter method.

(3) Prior art and problems The conventional way to make chemical sheets is to use a metal foil coated with a mold release agent or a synthetic resin film such as polyethylene terephthalate as a substrate, and then print the first film on the substrate using a screen printing method.
A raw sheet with the structure shown in the figure is formed.

For example, after forming a lower dummy layer 1 with a thickness of about 200 μm uniformly in a square of about 20 cIL using a screen printing method, conductive paste such as silver/palladium (Pd) based paste is applied to the electrode pattern 2ζ to a total thickness of 3 to 5 μm. Then, after drying, the dielectric paste is uniformly printed to a thickness of about 40 mm to form the dielectric layer 3, and the operation of drying is repeated as many times as necessary. A green sheet is completed by printing dielectric paste to the same thickness as the dummy layer 1 to form an upper dummy layer 4 and peeling it off from the substrate.

Next, the chip capacitor is completed by cutting it using force and a cutter according to the electrode pattern, baking it at a high temperature of about 1250° C. for about 2 hours, and baking silver on the rear end surface to provide the terminal electrode 5. .

However, the capacitor formed in this manner has a tendency to curve in the direction in which it was in contact with the substrate, as shown in FIG. The reason for this is that when dielectric paste and conductive paste are applied and laminated by screen printing on the board,
The area of the printed surface that comes into contact with the substrate is fixed, whereas the area above is not constrained by the machine, and each time a layer is formed by printing, a drying process is performed, so the solvent evaporates, and therefore the lamination is not possible. As it progresses, the density of the upper layer increases compared to the lower layer.

Reference numeral 11311 is an explanatory diagram of this tendency, in which the horizontal axis shows the density of the compound, the vertical axis shows the sheet thickness, and curve 6 shows the tendency of this density change.

Therefore, the density of the lower dummy dielectric layer is small when it is peeled off from the substrate after forming the upper dummy dielectric layer, and when it is cut into the size of a chip capacitor and fired at a high temperature of 1000°C or higher, sintering progresses. As a result, the density of the ferroelectric layer becomes uniform, and as a result, the degree of shrinkage of the lower layer is large, and therefore #! Warpage as shown in Figure 2 occurs in the chip capacitor. If this causes warping of the chip and the capacitor,
this! Not only does this result in poor appearance, but it also causes delamination and cracking of the chip, leading to defects. For this reason, conventional methods for making chips without warpage have included devising the stacking method during firing, but no good method has been found to eliminate warpage.

(4) Object of the Invention An object of the present invention is to provide a method for manufacturing a chip capacitor that does not cause warpage by changing the composition of a dielectric paste.

(5) Structure of the Invention The present invention prevents warping during firing by changing the composition of the dielectric paste used for forming the upper dummy layer 4 to that used for forming the lower dummy layer 1 and the dielectric layer 3. It is intended to do so.

In other words, as shown in Figure 3, the dielectric layers that exist in a multilayer structure have a density that increases toward the top, but the upper dummy layer provided on the top layer is formed from a dielectric paste with a low density. This corrects the non-uniform density distribution.

As for the thickness of the dielectric layer that constitutes the chip capacitor, it is advantageous to make it as thin as possible in order to increase the capacitance as long as the insulation resistance does not decrease, and in this example, it is approximately 40μ.
m is used. On the other hand, the lower dummy layer and the upper dummy layer need to have a considerable thickness as an exterior and protective layer for the capacitor, and in this embodiment, a thickness of about 200 am is used. Therefore, even if there is a considerable density difference between the upper and lower layers by multilayering several layers of lO, the strain caused by this can be corrected by a single thick upper dummy layer.

Now, the density of the dielectric paste coating layer can be adjusted by changing the blending amount of the binder.

In other words, dielectric paste is mainly composed of dielectric powder, binder, dispersant, and solvent.
Some of the solvents evaporate during the drying process after coating, while organic substances such as binders and dispersants
During the firing process, which is carried out for 2 hours at As a result, a dense dielectric layer is formed.

Here, the binder consists of resin and plasticizer,
The main component is dielectric ceramic powder 1009, and the amount of binder added is 18. An example of the formation of the dielectric paste used in this experiment ξ is shown below as j9. Table 811 In the present invention, the composition ratio of the binder is set to 1 in Table 1! Adjust the density of the dielectric paste coating layer by changing the koji example.
This eliminates the warpage that appears after firing.

This effect will be explained below with reference to Examples.

(6) Embodiment of the Invention The material constituting the dielectric paste is the first! ! Same as 1
4 by changing only the amount of binder added to ll1 body porcelain powder 1009 to 165.18p, 20.9 and 22g.
Create dielectric paste of different types and add binder 1i1
A chip capacitor having a 10-layer structure was manufactured by forming a lower dummy layer and a dielectric layer using the paste No. 6.9, and using pastes with different amounts of binder added for the upper dummy layer. In this case, the thickness of each dummy layer is 200 μm, the thickness of the dielectric layer is about 40 μm, and the size of the chip capacitor is 4.5×2. - Also, the firing conditions are 1250℃,
It is 2 hours.

As a result of experiments, the amount of the binder in the paste forming the upper dummy layer differs in the warpage l11K, but other phenomena such as delamination between the multilayer electrodes and element cracking also occur. When the present invention, in which the occurrence of warpage is controlled by the binder content, is put into practice, if the binder content is too large, the phenomenon of warping in the opposite direction to that of the conventional method may occur. Here, the amount of warpage can be quantitatively expressed by the height ΔX of the warp at the center when the chip is placed on a flat surface as shown in figure jg2.

Table 2 shows the results of these measurements.

Table 2 shows that in the case of this *m example, when using the conventional method, that is, when the amount of binder added was 16 g, warping of 0.3 m occurred, and phenomena such as delamination and element cracking occurred, but as the amount of added binder was increased, It can be seen that there is no warping and phenomena such as severe delamination are also eliminated.

However, if the amount added exceeds the appropriate amount, warping in the opposite direction will occur and phenomena such as delamination will occur.

(7) Effects of the Invention The present invention was made in order to eliminate warpage that occurs in the manufacture of chip capacitors, and by increasing the binder content in the dielectric paste used to form the upper dummy layer, the coating layer can be reduced. The main purpose is to increase the density and thereby offset the non-uniformity of density that occurs when forming multiple layers.

In this case, the appropriate binder content is 4.5 with a 10-layer structure.
X 2. For a chip capacitor with a size of Om 1
8 to 20p, that is, 11 to 22 inches more than the lower layer, but there are various chip sizes and calendar numbers, and the size of warpage is naturally proportional to the chip shape and number of layers. increases to

The present invention increases the binder content of the dielectric paste used for forming a single-layer lower dummy in consideration of the shape and dimensions of the chip capacitor to be manufactured and the number of laminated layers. This not only improves manufacturing yield but also improves the reliability of chip capacitors.

[Brief explanation of the drawing]

Figure 111EI is a cross-sectional view of a multilayer ceramic capacitor, C
B) is a front view, FIG. 2 is an explanatory diagram showing the warpage of a multilayer ceramic capacitor, and FIG. 3 is an explanatory diagram of the density distribution in the raw tube. In the figure, l is the lower dummy dielectric m, 2 is the electrode pattern, 3 is the dielectric layer, and 4 is the upper dummy dielectric layer Q'n.

Claims (1)

[Claims] A sorting structure is created in which electrode patterns are alternately formed between the dielectric layers by alternately screen printing a dielectric paste mainly composed of strong-electric ceramic powder and a conductor paste mainly composed of high-melting point noble metals. In the production of multilayer porcelain capacitors by cutting the sheet into predetermined dimensions and firing it, the amount of binder in the dielectric paste used when screen printing the upper dummy dielectric layer of the capacitor is 1. A method for manufacturing a multilayer image capacitor, characterized in that a dummy dielectric layer and an intermediate dielectric layer are formed using a 1IIE paste containing 1O to 30- more than the 1IIE paste used to form the dummy dielectric layer and the intermediate dielectric layer.